diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ef29925e33dd..31777883223c 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -64,6 +64,7 @@ enum riscv_csr_class
   CSR_CLASS_I,
   CSR_CLASS_I_32, /* rv32 only */
   CSR_CLASS_F, /* f-ext only */
+  CSR_CLASS_P, /* rvp only */
   CSR_CLASS_DEBUG /* debug CSR */
 };
 
@@ -868,6 +869,10 @@ riscv_csr_address (const char *csr_name,
       result = riscv_subset_supports ("f");
       need_check_version = FALSE;
       break;
+    case CSR_CLASS_P:
+      result = riscv_subset_supports ("zpn");
+      need_check_version = FALSE;
+      break;
     case CSR_CLASS_DEBUG:
       need_check_version = FALSE;
       break;
diff --git a/gas/testsuite/gas/riscv/insn-dsp.d b/gas/testsuite/gas/riscv/insn-dsp.d
index a7f85d53f8d1..de449e888429 100644
--- a/gas/testsuite/gas/riscv/insn-dsp.d
+++ b/gas/testsuite/gas/riscv/insn-dsp.d
@@ -1,6 +1,7 @@
 #as: -march=rv32gc_zpn_zpsf
 #source: insn-dsp.s
-#objdump: -d
+#objdump: -d -M no-aliases
+
 
 .*:[ 	]+file format .*
 
@@ -230,8 +231,8 @@ Disassembly of section .text:
 [ 	]+.*:[ 	]+.*[ 	]+uraddw[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+rsubw[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+ursubw[ 	]+a1,a2,a3
-[ 	]+.*:[ 	]+.*[ 	]+csrr[ 	]+a1,satp
-[ 	]+.*:[ 	]+.*[ 	]+csrrci[ 	]+a1,satp,1
+[ 	]+.*:[ 	]+.*[ 	]+csrrs[ 	]+a1,vxsat,zero
+[ 	]+.*:[ 	]+.*[ 	]+csrrci[ 	]+zero,vxsat,1
 [ 	]+.*:[ 	]+.*[ 	]+ave[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+sra.u[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+srai.u[ 	]+a1,a2,5
diff --git a/gas/testsuite/gas/riscv/insn-dsp.s b/gas/testsuite/gas/riscv/insn-dsp.s
index cfdd1f30e488..ff60490f90c8 100644
--- a/gas/testsuite/gas/riscv/insn-dsp.s
+++ b/gas/testsuite/gas/riscv/insn-dsp.s
@@ -266,8 +266,8 @@ dsp:
 	ursubw    a1, a2, a3
 
 	# Table 23. OV (Overflow) flag Set/Clear Instructions (2)
-	csrr      a1, satp	#rdov     a1
-	csrrci    a1, satp, 1	#clrov
+	rdov     a1
+	clrov
 
 	# Table 24. Non-SIMD Miscellaneous Instructions (9)
 	ave       a1, a2, a3
diff --git a/gas/testsuite/gas/riscv/rvp_csr.d b/gas/testsuite/gas/riscv/rvp_csr.d
new file mode 100644
index 000000000000..2787389a617a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/rvp_csr.d
@@ -0,0 +1,12 @@
+#as: -march=rv32gc_zpn
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <rvp>:
+[ 	]+[0-9a-f]+:[ 	]+00905073[ 	]+csrwi[ 	]+vxsat,0
+[ 	]+[0-9a-f]+:[ 	]+0090f073[ 	]+csrci[ 	]+vxsat,1
+[ 	]+[0-9a-f]+:[ 	]+009022f3[ 	]+csrr[ 	]+t0,vxsat
diff --git a/gas/testsuite/gas/riscv/rvp_csr.s b/gas/testsuite/gas/riscv/rvp_csr.s
new file mode 100644
index 000000000000..9820ca8dcdfd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/rvp_csr.s
@@ -0,0 +1,4 @@
+rvp:
+    csrwi vxsat,0
+    csrci vxsat,1
+    csrr t0,vxsat
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9fdf17dae36b..79bacd9a0415 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -1106,10 +1106,6 @@
 #define MASK_ZUNPKD831 0xfff0707f
 #define MATCH_ZUNPKD832 0xad700077
 #define MASK_ZUNPKD832 0xfff0707f
-#define MATCH_RDOV 0x80102073
-#define MASK_RDOV 0xfffff07f
-#define MATCH_CLROV 0x8010f073
-#define MASK_CLROV 0xffffffff
 #define MATCH_ADD32 0x40002077
 #define MASK_ADD32 0xfe00707f
 #define MATCH_CRAS32 0x44002077
@@ -1525,6 +1521,8 @@
 #define CSR_TCONTROL 0x7a5
 #define CSR_MCONTEXT 0x7a8
 #define CSR_SCONTEXT 0x7aa
+/* RVP CSR */
+#define CSR_VXSAT 0x009
 #endif /* RISCV_ENCODING_H */
 #ifdef DECLARE_INSN
 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
@@ -2060,8 +2058,6 @@ DECLARE_INSN(zunpkd820, MATCH_ZUNPKD820, MASK_ZUNPKD820)
 DECLARE_INSN(zunpkd830, MATCH_ZUNPKD830, MASK_ZUNPKD830)
 DECLARE_INSN(zunpkd831, MATCH_ZUNPKD831, MASK_ZUNPKD831)
 DECLARE_INSN(zunpkd832, MATCH_ZUNPKD832, MASK_ZUNPKD832)
-DECLARE_INSN(rdov, MATCH_RDOV, MASK_RDOV)
-DECLARE_INSN(clrov, MATCH_CLROV, MASK_CLROV)
 DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32)
 DECLARE_INSN(cras32, MATCH_CRAS32, MASK_CRAS32)
 DECLARE_INSN(crsa32, MATCH_CRSA32, MASK_CRSA32)
@@ -2081,7 +2077,6 @@ DECLARE_INSN(khmtt16, MATCH_KHMTT16, MASK_KHMTT16)
 DECLARE_INSN(kmabb32, MATCH_KMABB32, MASK_KMABB32)
 DECLARE_INSN(kmabt32, MATCH_KMABT32, MASK_KMABT32)
 DECLARE_INSN(kmatt32, MATCH_KMATT32, MASK_KMATT32)
-DECLARE_INSN(kmada32, MATCH_KMADA32, MASK_KMADA32)
 DECLARE_INSN(kmaxda32, MATCH_KMAXDA32, MASK_KMAXDA32)
 DECLARE_INSN(kmds32, MATCH_KMDA32, MASK_KMDA32)
 DECLARE_INSN(kmxda32, MATCH_KMXDA32, MASK_KMXDA32)
@@ -2398,6 +2393,7 @@ DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_C
 DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_P, ISA_SPEC_CLASS_DRAFT, PRIV_SPEC_CLASS_DRAFT)
 #endif /* DECLARE_CSR */
 #ifdef DECLARE_CSR_ALIAS
 DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b071820adc3a..860c353cee44 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -88,6 +88,9 @@ const char * const riscv_fpr_names_abi[NFPR] =
 #define MATCH_SHAMT_REV_64 (0b111111 << 20)
 #define MATCH_SHAMT_REV8_H (0b1000 << 20)
 #define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
+#define MATCH_CLROV (MATCH_CSRRCI | (CSR_VXSAT << OP_SH_CSR) | (1 << OP_SH_RS1))
+#define MATCH_RDOV (MATCH_CSRRS|(CSR_VXSAT << OP_SH_CSR))
+#define MASK_RDOV (0xffffffffU ^ MASK_RD)
 
 static int
 match_opcode (const struct riscv_opcode *op, insn_t insn)
@@ -1091,7 +1094,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"zunpkd831",   0, INSN_CLASS_ZPN, "d,s",       MATCH_ZUNPKD831, MASK_ZUNPKD831, match_opcode, 0 },
 {"zunpkd832",   0, INSN_CLASS_ZPN, "d,s",       MATCH_ZUNPKD832, MASK_ZUNPKD832, match_opcode, 0 },
 {"rdov",        0, INSN_CLASS_ZPN, "d",         MATCH_RDOV, MASK_RDOV, match_opcode, INSN_ALIAS },
-{"clrov",       0, INSN_CLASS_ZPN, "",          MATCH_CLROV, MASK_CLROV, match_opcode, INSN_ALIAS },
+{"clrov",       0, INSN_CLASS_ZPN, "",          MATCH_CLROV, 0xffffffffU, match_opcode, INSN_ALIAS },
 {"add32",      64, INSN_CLASS_ZPN, "d,s,t",     MATCH_ADD32, MASK_ADD32, match_opcode, 0 },
 {"cras32",     64, INSN_CLASS_ZPN, "d,s,t",     MATCH_CRAS32, MASK_CRAS32, match_opcode, 0 },
 {"crsa32",     64, INSN_CLASS_ZPN, "d,s,t",     MATCH_CRSA32, MASK_CRSA32, match_opcode, 0 },