Add .rv32 on rv32_zbs instructions

to be consistent with slli, srli, and srai. Signed-off-by: Hiroo HAYASHI <[email protected]>
riscv · Jan 8, 2024 · d653dc6 · d653dc6
1 parent a014979
commit d653dc6
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Showing 2 changed files with 8 additions and 4 deletions.
diff --git a/constants.py b/constants.py
@@ -220,4 +220,8 @@
     'mop_rr_7',
     'sspush_x1',
     'sspush_x5',
+    'bclri.rv32',
+    'bexti.rv32',
+    'binvi.rv32',
+    'bseti.rv32',
 ]
diff --git a/rv32_zbs b/rv32_zbs
@@ -1,5 +1,5 @@
-$pseudo_op rv64_zbs::bclri bclri rd rs1 31..25=0x24 shamtw 14..12=1 6..2=0x04 1..0=3
-$pseudo_op rv64_zbs::bexti bexti rd rs1 31..25=0x24 shamtw 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_zbs::binvi binvi rd rs1 31..25=0x34 shamtw 14..12=1 6..2=0x04 1..0=3
-$pseudo_op rv64_zbs::bseti bseti rd rs1 31..25=0x14 shamtw 14..12=1 6..2=0x04 1..0=3
+$pseudo_op rv64_zbs::bclri bclri.rv32 rd rs1 31..25=0x24 shamtw 14..12=1 6..2=0x04 1..0=3
+$pseudo_op rv64_zbs::bexti bexti.rv32 rd rs1 31..25=0x24 shamtw 14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv64_zbs::binvi binvi.rv32 rd rs1 31..25=0x34 shamtw 14..12=1 6..2=0x04 1..0=3
+$pseudo_op rv64_zbs::bseti bseti.rv32 rd rs1 31..25=0x14 shamtw 14..12=1 6..2=0x04 1..0=3