From 38a31d663cc044731d740520f0091822bafeee4c Mon Sep 17 00:00:00 2001
From: Thomas Hepworth <tomhepworth@hotmail.co.uk>
Date: Thu, 26 Oct 2023 10:42:34 +0100
Subject: [PATCH] Clarified syntax of regular instructions

See https://github.com/riscv/riscv-opcodes/issues/204

Before this change the text implied that bit encodings and variable arguments could not be mixed in the list of instruction arguments.

Signed-off-by: Thomas Hepworth <tomhepworth@hotmail.co.uk>
---
 README.md | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index dec6003b..96574847 100644
--- a/README.md
+++ b/README.md
@@ -46,8 +46,10 @@ Instruction syntaxes used in this project are broadly categorized into three:
 - **regular instructions** :- these are instructions which hold a unique opcode in the encoding space. A very generic syntax guideline 
   for these instructions is as follows:
   ```
-  <instruction name> <instruction args> <bit-encodings>
+  <instruction name> <arguments>
   ```
+  where `<argument>` is either `<bit encoding>` or `<variable argument>`.
+
   Examples:
   ```
   lui     rd imm20 6..2=0x0D 1..0=3