diff --git a/riscv/disasm.h b/riscv/disasm.h
index d4b8c2c40e..b9e870eb0d 100644
--- a/riscv/disasm.h
+++ b/riscv/disasm.h
@@ -52,6 +52,7 @@ class disasm_insn_t
     {
       bool next_arg_optional  = false;
       s += std::string(std::max(1, 8 - int(name.size())), ' ');
+
       for (size_t i = 0; i < args.size(); i++) {
         if (args[i] == nullptr) {
           next_arg_optional = true;
@@ -75,8 +76,9 @@ class disasm_insn_t
  private:
   uint32_t match;
   uint32_t mask;
-  std::vector<const arg_t*> args;
   std::string name;
+ public:
+  std::vector<const arg_t*> args;
 };
 
 class disassembler_t
diff --git a/riscv/execute.cc b/riscv/execute.cc
index 1fa6111f7a..e2ec2907a7 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -282,9 +282,18 @@ void processor_t::step(size_t n)
 
           in_wfi = false;
           insn_fetch_t fetch = mmu->load_insn(pc);
-          if (debug && !state.serialized)
+          if (debug && !state.serialized){
+            std::stringstream s{"before:\t"};
+            debug_output_log(&s);
+            print_involved_regs(fetch.insn);
             disasm(fetch.insn);
+          }
           pc = execute_insn_logged(this, pc, fetch);
+          if (debug && !state.serialized){
+            std::stringstream s{"after:\t"};
+            debug_output_log(&s);
+            print_involved_regs(fetch.insn);
+          }
           advance_pc();
 
           // Resume from debug mode in critical error
diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index 2701f49308..e6d0fe2364 100644
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -739,7 +739,7 @@ void sim_t::interactive_str(const std::string& cmd, const std::vector<std::strin
   char ch;
   while ((ch = mmu->load<uint8_t>(addr++)))
     out << ch;
-
+    
   out << std::endl;
 }
 
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 9260045bd3..a9f9500446 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -22,6 +22,7 @@
 #include <stdexcept>
 #include <string>
 #include <algorithm>
+#include <functional>
 
 #ifdef __GNUC__
 # pragma GCC diagnostic ignored "-Wunused-variable"
@@ -610,6 +611,65 @@ void processor_t::disasm(insn_t insn)
   }
 }
 
+void processor_t::print_all_regs(){
+  std::stringstream s;
+  unsigned max_xlen = isa.get_max_xlen();
+    for(int i=0;i<32;i+=4){
+      s << std::dec << std::setfill(' ') << std::setw(4) << i <<  std::hex << ": 0x" << std::setfill('0')<< std::setw(max_xlen / 4) << state.XPR[i]  <<"\t" 
+        << std::dec << std::setfill(' ') << std::setw(4) << i+1 <<  std::hex << ": 0x" << std::setfill('0')<< std::setw(max_xlen / 4) << state.XPR[i+1]<<"\t"  
+        << std::dec << std::setfill(' ') << std::setw(4) << i+2 <<  std::hex << ": 0x" << std::setfill('0')<< std::setw(max_xlen / 4) << state.XPR[i+2]<<"\t" 
+        << std::dec << std::setfill(' ') << std::setw(4) << i+3 <<  std::hex << ": 0x" << std::setfill('0')<< std::setw(max_xlen / 4) << state.XPR[i+3]<< "\n";
+    }
+  debug_output_log(&s);
+}
+
+void processor_t::print_involved_regs(insn_t insn)
+{
+  std::stringstream s;
+  std::function is_a_reg = [](std::string reg_str)->std::tuple<int,int>{
+    for(int i=0;i<32;i++){
+      if(reg_str==xpr_name[i]){
+        return {0,i};
+      }
+      else if(reg_str==fpr_name[i]){
+        return {1,i};
+      }
+      else if(reg_str==vr_name[i]){
+        return {2,i};
+      }
+    }
+    return {255,255};
+  };
+  
+  std::function float128_to_double=[](const float128_t& f) -> double {
+    double high = static_cast<double>(f.v[1]);
+    double low = static_cast<double>(f.v[0]) / (1ULL << 64);
+    return high + low; // This won't give you correct float128 representation!
+  };
+  
+  const disasm_insn_t* disasm_insn = disassembler->lookup(insn);
+
+  for(auto arg : disasm_insn->args){
+      auto reg_str=arg->to_string(insn);
+      int reg_num= is_a_register(reg_str);
+      // s<<state.XPR[reg_num];
+      auto [t,n]= is_a_reg(reg_str);
+      switch (t)
+      {
+      case 0:
+        s<<reg_str<<std::hex<<"=0x"<<state.XPR[n]<<"  ";
+        break;
+      case 1:
+        s<<reg_str<<" "<<std::setprecision(30)<<float128_to_double( state.FPR[n])<<"\t";
+        break;
+
+      default:
+        break;
+      }
+  };
+  s<<std::endl;
+  debug_output_log(&s);
+}
 int processor_t::paddr_bits()
 {
   unsigned max_xlen = isa.get_max_xlen();
diff --git a/riscv/processor.h b/riscv/processor.h
index 4f22cbdee5..717bc3fe63 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -405,6 +405,8 @@ class processor_t : public abstract_device_t
   void take_trap(trap_t& t, reg_t epc); // take an exception
   void take_trigger_action(triggers::action_t action, reg_t breakpoint_tval, reg_t epc, bool virt);
   void disasm(insn_t insn); // disassemble and print an instruction
+  void print_all_regs(); // print values of all registers
+  void print_involved_regs(insn_t insn); // print values of registers involved
   void register_insn(insn_desc_t, bool);
   int paddr_bits();