From 5cc162c48276d860a5a09e713c31b7b32008d9aa Mon Sep 17 00:00:00 2001 From: XYenChi Date: Wed, 20 Nov 2024 17:19:43 +0800 Subject: [PATCH] Fix format --- riscv/insns/vmulhu_vv.h | 2 +- riscv/insns/vredand_vs.h | 2 +- riscv/insns/vredmaxu_vs.h | 2 +- riscv/insns/vredmin_vs.h | 2 +- riscv/insns/vredminu_vs.h | 2 +- riscv/insns/vredor_vs.h | 2 +- riscv/insns/vredsum_vs.h | 2 +- riscv/insns/vredxor_vs.h | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h index 8e318edb75..0ff488c3b6 100644 --- a/riscv/insns/vmulhu_vv.h +++ b/riscv/insns/vmulhu_vv.h @@ -1,4 +1,4 @@ -// vmulhu vd ,vs2, vs1 +// vmulhu vd, vs2, vs1 VI_VV_ULOOP ({ vd = ((uint128_t)vs2 * vs1) >> sew; diff --git a/riscv/insns/vredand_vs.h b/riscv/insns/vredand_vs.h index 6c2d9089fa..2e111820da 100644 --- a/riscv/insns/vredand_vs.h +++ b/riscv/insns/vredand_vs.h @@ -1,4 +1,4 @@ -// vredand.vs vd, vs2 ,vs1 +// vredand.vs vd, vs2, vs1 VI_VV_LOOP_REDUCTION ({ vd_0_res &= vs2; diff --git a/riscv/insns/vredmaxu_vs.h b/riscv/insns/vredmaxu_vs.h index 960f486181..8499258df2 100644 --- a/riscv/insns/vredmaxu_vs.h +++ b/riscv/insns/vredmaxu_vs.h @@ -1,4 +1,4 @@ -// vredmaxu.vs vd, vs2 ,vs1 +// vredmaxu.vs vd, vs2, vs1 VI_VV_ULOOP_REDUCTION ({ vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2; diff --git a/riscv/insns/vredmin_vs.h b/riscv/insns/vredmin_vs.h index 50359b7a53..9cbfa42554 100644 --- a/riscv/insns/vredmin_vs.h +++ b/riscv/insns/vredmin_vs.h @@ -1,4 +1,4 @@ -// vredmin.vs vd, vs2 ,vs1 +// vredmin.vs vd, vs2, vs1 VI_VV_LOOP_REDUCTION ({ vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; diff --git a/riscv/insns/vredminu_vs.h b/riscv/insns/vredminu_vs.h index 708247592f..ac3c0806df 100644 --- a/riscv/insns/vredminu_vs.h +++ b/riscv/insns/vredminu_vs.h @@ -1,4 +1,4 @@ -// vredminu.vs vd, vs2 ,vs1 +// vredminu.vs vd, vs2, vs1 VI_VV_ULOOP_REDUCTION ({ vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2; diff --git a/riscv/insns/vredor_vs.h b/riscv/insns/vredor_vs.h index f7acd9aa9d..24e1496f72 100644 --- a/riscv/insns/vredor_vs.h +++ b/riscv/insns/vredor_vs.h @@ -1,4 +1,4 @@ -// vredor.vs vd, vs2 ,vs1 +// vredor.vs vd, vs2, vs1 VI_VV_LOOP_REDUCTION ({ vd_0_res |= vs2; diff --git a/riscv/insns/vredsum_vs.h b/riscv/insns/vredsum_vs.h index c4fefe57f6..d470ec038e 100644 --- a/riscv/insns/vredsum_vs.h +++ b/riscv/insns/vredsum_vs.h @@ -1,4 +1,4 @@ -// vredsum.vs vd, vs2 ,vs1 +// vredsum.vs vd, vs2, vs1 VI_VV_LOOP_REDUCTION ({ vd_0_res += vs2; diff --git a/riscv/insns/vredxor_vs.h b/riscv/insns/vredxor_vs.h index bb81ad9a4f..3b3709a565 100644 --- a/riscv/insns/vredxor_vs.h +++ b/riscv/insns/vredxor_vs.h @@ -1,4 +1,4 @@ -// vredxor.vs vd, vs2 ,vs1 +// vredxor.vs vd, vs2, vs1 VI_VV_LOOP_REDUCTION ({ vd_0_res ^= vs2;