diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 4a7a802ef5..e9aef1a822 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -413,14 +413,14 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
                 dmstatus.allresumeack = false;
               }
               auto hart = sim->get_harts().at(hart_id);
-              if (hart_state[hart_id].halted) {
-                dmstatus.allrunning = false;
-                dmstatus.anyhalted = true;
-                dmstatus.allunavail = false;
-              } else if (!hart_available(hart_id)) {
+              if (!hart_available(hart_id)) {
                 dmstatus.allrunning = false;
                 dmstatus.allhalted = false;
                 dmstatus.anyunavail = true;
+              } else if (hart_state[hart_id].halted) {
+                dmstatus.allrunning = false;
+                dmstatus.anyhalted = true;
+                dmstatus.allunavail = false;
               } else {
                 dmstatus.allhalted = false;
                 dmstatus.anyrunning = true;
@@ -579,6 +579,10 @@ bool debug_module_t::perform_abstract_command()
     abstractcs.cmderr = CMDERR_BUSY;
     return true;
   }
+  if (!hart_available(dmcontrol.hartsel)) {
+    abstractcs.cmderr = CMDERR_HALTRESUME;
+    return true;
+  }
 
   if ((command >> 24) == 0) {
     // register access