From b6c78558ef9b3f4939672ab13cdb60544ef59e05 Mon Sep 17 00:00:00 2001
From: YenHaoChen <howard25336284@gmail.com>
Date: Thu, 24 Oct 2024 15:44:46 +0800
Subject: [PATCH] zvk: Check VR index alignment constraint and vm constraint

The vector specification requires aligning the VR index regarding the
LMUL. Also, it requires that vd cannot be v0 when masking.

Although the vector crypto specification does not explicitly state those
two constraints, the deriving extension should include the general
constraints from the vector specification.

This commit checks the VR index and vm constraints on Zvk instructions.
---
 riscv/zvk_ext_macros.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/riscv/zvk_ext_macros.h b/riscv/zvk_ext_macros.h
index f094629835..6baf76a23d 100644
--- a/riscv/zvk_ext_macros.h
+++ b/riscv/zvk_ext_macros.h
@@ -276,6 +276,7 @@
 //
 #define VI_ZVK_VD_VS1_VS2_EGU32x4_NOVM_LOOP(PRELUDE, EG_BODY) \
   do { \
+    VI_CHECK_SSS(true); \
     require_element_groups_32x4; \
     require_no_vmask; \
     const reg_t vd_num = insn.rd(); \
@@ -331,6 +332,7 @@
 //
 #define VI_ZVK_VD_VS1_VS2_EGU32x8_NOVM_LOOP(PRELUDE, EG_BODY) \
   do { \
+    VI_CHECK_SSS(true); \
     require_element_groups_32x8;; \
     require_no_vmask; \
     const reg_t vd_num = insn.rd(); \
@@ -397,6 +399,7 @@
                                                                PRELOOP, \
                                                                EG_BODY) \
   do { \
+    VI_CHECK_SSS(true); \
     require_element_groups_32x4; \
     require_no_vmask; \
     const reg_t vd_num = insn.rd(); \
@@ -466,6 +469,7 @@
                                                            PRELOOP, \
                                                            EG_BODY) \
   do { \
+    VI_CHECK_SSS(false); \
     require_element_groups_32x4; \
     require_no_vmask; \
     const reg_t vd_num = insn.rd(); \
@@ -515,6 +519,7 @@
 //
 #define VI_ZVK_VD_VS2_EGU32x4_NOVM_LOOP(PRELUDE, EG_BODY) \
   do { \
+    VI_CHECK_SSS(false); \
     require_element_groups_32x4; \
     require_no_vmask; \
     const reg_t vd_num = insn.rd(); \
@@ -567,6 +572,7 @@
 //
 #define VI_ZVK_VD_VS2_ZIMM5_EGU32x4_NOVM_LOOP(PRELUDE, PRELOOP, EG_BODY) \
   do { \
+    VI_CHECK_SSS(false); \
     require_element_groups_32x4; \
     require_no_vmask; \
     const reg_t vd_num = insn.rd(); \
@@ -623,6 +629,7 @@
 //
 #define VI_ZVK_VD_VS2_ZIMM5_EGU32x8_NOVM_LOOP(PRELUDE, PRELOOP, EG_BODY) \
   do { \
+    VI_CHECK_SSS(false); \
     require_element_groups_32x8; \
     require_no_vmask; \
     const reg_t vd_num = insn.rd(); \
@@ -680,6 +687,7 @@
 //         in the 'vs2' vector register / vector register group.
 #define VI_ZVK_VD_VS1_VS2_EGU64x4_NOVM_LOOP(PRELUDE, EG_BODY) \
   do { \
+    VI_CHECK_SSS(true); \
     require_element_groups_64x4; \
     require_no_vmask; \
     const reg_t vd_num = insn.rd(); \