From 11dacaedc4b55ac1d79f1152a549ab9bfb170d2d Mon Sep 17 00:00:00 2001
From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Wed, 6 Jul 2022 10:51:36 +0800
Subject: [PATCH] add standalone class for fcsr and senvcfg csr

---
 riscv/csrs.cc      | 11 +++++++++++
 riscv/csrs.h       | 11 +++++++++++
 riscv/processor.cc |  4 ++--
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index c2bdf0a92c..1a23ff978c 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -1305,3 +1305,14 @@ void sstateen_csr_t::verify_permissions(insn_t insn, bool write) const {
   if (state->v && !(state->hstateen[index]->read() & HSTATEEN_SSTATEEN))
       throw trap_virtual_instruction(insn.bits());
 }
+
+// implement class fcsr_csr_t
+fcsr_csr_t::fcsr_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb):
+  composite_csr_t(proc, addr, upper_csr, lower_csr, upper_lsb) {
+}
+
+// implement class senvcfg_csr_t
+senvcfg_csr_t::senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask,
+                             const reg_t init):
+  masked_csr_t(proc, addr, mask, init) {
+}
diff --git a/riscv/csrs.h b/riscv/csrs.h
index 15f868c786..2b8a2fb758 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -695,4 +695,15 @@ class sstateen_csr_t: public hstateen_csr_t {
  protected:
   virtual bool unlogged_write(const reg_t val) noexcept override;
 };
+
+class fcsr_csr_t: public composite_csr_t {
+ public:
+  fcsr_csr_t(processor_t* const proc, const reg_t addr, csr_t_p upper_csr, csr_t_p lower_csr, const unsigned upper_lsb);
+};
+
+class senvcfg_csr_t final: public masked_csr_t {
+ public:
+  senvcfg_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init);
+};
+
 #endif
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 1c33911a85..5973baf2ff 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -375,7 +375,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_FFLAGS] = fflags = std::make_shared<float_csr_t>(proc, CSR_FFLAGS, FSR_AEXC >> FSR_AEXC_SHIFT, 0);
   csrmap[CSR_FRM] = frm = std::make_shared<float_csr_t>(proc, CSR_FRM, FSR_RD >> FSR_RD_SHIFT, 0);
   assert(FSR_AEXC_SHIFT == 0);  // composite_csr_t assumes fflags begins at bit 0
-  csrmap[CSR_FCSR] = std::make_shared<composite_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
+  csrmap[CSR_FCSR] = std::make_shared<fcsr_csr_t>(proc, CSR_FCSR, frm, fflags, FSR_RD_SHIFT);
 
   csrmap[CSR_SEED] = std::make_shared<seed_csr_t>(proc, CSR_SEED);
 
@@ -390,7 +390,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa)
   csrmap[CSR_MENVCFG] = menvcfg = std::make_shared<masked_csr_t>(proc, CSR_MENVCFG, menvcfg_mask, menvcfg_init);
   const reg_t senvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? SENVCFG_CBCFE | SENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? SENVCFG_CBZE : 0);
-  csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<masked_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
+  csrmap[CSR_SENVCFG] = senvcfg = std::make_shared<senvcfg_csr_t>(proc, CSR_SENVCFG, senvcfg_mask, 0);
   const reg_t henvcfg_mask = (proc->extension_enabled(EXT_ZICBOM) ? HENVCFG_CBCFE | HENVCFG_CBIE : 0) |
                              (proc->extension_enabled(EXT_ZICBOZ) ? HENVCFG_CBZE : 0) |
                              (proc->extension_enabled(EXT_SVPBMT) ? HENVCFG_PBMTE : 0);