From 8b41934c46aec04ed119fdba9a580499b68f76b0 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Wed, 9 Oct 2024 06:05:24 -0700 Subject: [PATCH 1/5] Fix Assembly Constraint Table Header Signed-off-by: Sam Elliott --- src/c-api.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/c-api.adoc b/src/c-api.adoc index 850af38..7e4d12a 100644 --- a/src/c-api.adoc +++ b/src/c-api.adoc @@ -736,7 +736,7 @@ statements, including both RISC-V specific and common operand constraints. .Constraints on Operands of Inline Assembly Statements [%autowidth] |=== -|*Constraint* | |*Note* +|*Constraint* |*Description* |*Note* |m |An address that is held in a general-purpose register with offset. | |A |An address that is held in a general-purpose register. | |r |General purpose register | From 45f02d429f2e69faeac85763e0cddcb2e48fe693 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Tue, 15 Oct 2024 10:10:30 -0700 Subject: [PATCH 2/5] Inline Asm Constraints and Modifiers We have customers with usecases that want more kinds of register constraints and modifiers. This change proposes support for these constraints and modifiers, and their names. Broadly, these are intended to make it easier for users who want to manually assemble instructions inside inline assembly blocks, either using the existing instruction formats, or using the raw form of the `.insn` directive. This makes it easier for hardware designers to experiment on new ISA extensions, and makes it easier to support the use of proprietary extensions with unmodified open-source toolchains. There are three groups of additions here: - Constraints for RVC-compatible registers. These use the `c` prefix on an existing register constraint, so `cr` gives a GPR between x8-x15, and `cf` does the same for an FPR between f8-f15. I'm not aware of compressed vector instructions, but we could add `cvr`, `cvd` and `cvm` in the future if the core architecture ends up having the concept of a vector register with an RVC encoding. - A modifier, `N`, to print the raw encoding of a register. This is used when using `.insn , `, where the user wants to pass a value to the instruction in a known register, but where the instruction doesn't follow the existing instruction formats, so the assembly parser is not expecting a register name, just a raw integer. - Constraints for even-odd pairs of registers. These use the `P` prefix on an existing register constraint. At the moment, this only defines `Pr` to mean an even-odd pair of GPRs. (We use `P` as a prefix as `p` already means "pointer" in GCC's target-independent constraints). I think this will print as the even register in the even-odd register pair, but I'm still working on the details around this. While the concept of even-odd register pairs is reasonably "new", there are places in the architecture where these already exist - the doubleword/quad CAS in Zacas, and they are also present in the Zilsd specification. Signed-off-by: Sam Elliott --- src/c-api.adoc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/c-api.adoc b/src/c-api.adoc index 7e4d12a..33034d0 100644 --- a/src/c-api.adoc +++ b/src/c-api.adoc @@ -746,6 +746,9 @@ statements, including both RISC-V specific and common operand constraints. |K |5-bit unsigned immediate integer operand | |J |Zero integer immediate operand | |s |symbol or label reference with a constant offset | +|cr |RVC general purpose register (`x8`-`x15`) | +|cf |RVC floating point register (`f8`-`f15`) | +|Pr |Even-odd general purpose register pair | |vr |Vector register | |vd |Vector register, excluding v0 | |vm |Vector register, only v0 | @@ -753,6 +756,8 @@ statements, including both RISC-V specific and common operand constraints. NOTE: Immediate value must be a compile-time constant. +NOTE: The `c*` and `P*` constraints are designed to be extensible to more kinds of registers in the future. + === The Difference Between `m` and `A` Constraints The difference between `m` and `A` is whether the operand can have an offset; @@ -809,6 +814,7 @@ statements, including both RISC-V specific and common operand modifiers. |*Modifiers* |*Description* |*Note* |z |Print `zero` (`x0`) register for immediate 0, typically used with constraints `J` | |i |Print `i` if corresponding operand is immediate. | +|N |Print register encoding as integer (0-31). | |=== [id=function-multi-version] From 3c32dcedd7832b04272b0cc983e02b7572a10895 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Wed, 13 Nov 2024 04:07:39 -0800 Subject: [PATCH 3/5] fixup! Inline Asm Constraints and Modifiers --- src/c-api.adoc | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/c-api.adoc b/src/c-api.adoc index 33034d0..e787263 100644 --- a/src/c-api.adoc +++ b/src/c-api.adoc @@ -733,6 +733,11 @@ Sign extension of 32-bit values on RV64 is not reflected in the interface. This section lists operand constraints that can be used with inline assembly statements, including both RISC-V specific and common operand constraints. +"Floating-point register" in both the `f` and `cf` rows means "a register +suitable for passing a floating-point value", so when using the `Zfinx`, +`Zdinx`, or `Zhinxmin` extensions this will allocate an X register. This is done +to aid portability of floating-point code. + .Constraints on Operands of Inline Assembly Statements [%autowidth] |=== @@ -747,13 +752,19 @@ statements, including both RISC-V specific and common operand constraints. |J |Zero integer immediate operand | |s |symbol or label reference with a constant offset | |cr |RVC general purpose register (`x8`-`x15`) | -|cf |RVC floating point register (`f8`-`f15`) | +|cf |RVC floating-point register (`f8`-`f15`) | |Pr |Even-odd general purpose register pair | |vr |Vector register | |vd |Vector register, excluding v0 | |vm |Vector register, only v0 | |=== +The `Pr` constraint should print as the even register in the pair, as this +matches how the `amocas.q` instruction (on RV64) or the `amocas.d` and `Zdinx` +instructions (on RV32) expect to parse their pair register operands. However, +both registers in the pair should be considered to be live or clobbered +together. + NOTE: Immediate value must be a compile-time constant. NOTE: The `c*` and `P*` constraints are designed to be extensible to more kinds of registers in the future. From bb49ede1d694fba36ee7b9d6a21aec2500339c91 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Wed, 13 Nov 2024 04:14:25 -0800 Subject: [PATCH 4/5] fixup! Inline Asm Constraints and Modifiers --- src/c-api.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/c-api.adoc b/src/c-api.adoc index e787263..22ff341 100644 --- a/src/c-api.adoc +++ b/src/c-api.adoc @@ -752,7 +752,7 @@ to aid portability of floating-point code. |J |Zero integer immediate operand | |s |symbol or label reference with a constant offset | |cr |RVC general purpose register (`x8`-`x15`) | -|cf |RVC floating-point register (`f8`-`f15`) | +|cf |RVC floating-point register (`f8`-`f15` or `x8-x15` with `Zfinx`) | |Pr |Even-odd general purpose register pair | |vr |Vector register | |vd |Vector register, excluding v0 | From e693b8c3140e462c5f53d418f33e1c25ed23e785 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Thu, 14 Nov 2024 05:27:00 -0800 Subject: [PATCH 5/5] fixup! Inline Asm Constraints and Modifiers --- src/c-api.adoc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/c-api.adoc b/src/c-api.adoc index 22ff341..e5f9b71 100644 --- a/src/c-api.adoc +++ b/src/c-api.adoc @@ -732,6 +732,7 @@ Sign extension of 32-bit values on RV64 is not reflected in the interface. This section lists operand constraints that can be used with inline assembly statements, including both RISC-V specific and common operand constraints. +Operand constraints are case-sensitive. "Floating-point register" in both the `f` and `cf` rows means "a register suitable for passing a floating-point value", so when using the `Zfinx`, @@ -753,13 +754,13 @@ to aid portability of floating-point code. |s |symbol or label reference with a constant offset | |cr |RVC general purpose register (`x8`-`x15`) | |cf |RVC floating-point register (`f8`-`f15` or `x8-x15` with `Zfinx`) | -|Pr |Even-odd general purpose register pair | +|R |Even-odd general purpose register pair | |vr |Vector register | |vd |Vector register, excluding v0 | |vm |Vector register, only v0 | |=== -The `Pr` constraint should print as the even register in the pair, as this +The `R` constraint should print as the even register in the pair, as this matches how the `amocas.q` instruction (on RV64) or the `amocas.d` and `Zdinx` instructions (on RV32) expect to parse their pair register operands. However, both registers in the pair should be considered to be live or clobbered @@ -767,7 +768,8 @@ together. NOTE: Immediate value must be a compile-time constant. -NOTE: The `c*` and `P*` constraints are designed to be extensible to more kinds of registers in the future. +NOTE: The `c*` constraints are designed to be extensible to more kinds of +RVC-compatible register constraints in the future. === The Difference Between `m` and `A` Constraints