From 381fae45ee011d5f36cb92f677bad594deab6fd9 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 27 Nov 2023 20:27:38 -0600 Subject: [PATCH 1/9] Merge https://github.com/riscv/riscv-smbios/blob/main/riscv-smbios.adoc Only the Type 44 content is added over, as the Type 4 content is already part of the SMBIOS spec. Further commits clean up the Type 44 structure. Signed-off-by: Andrei Warkentin --- smbios.adoc | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/smbios.adoc b/smbios.adoc index 97c933e..e83cb82 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -22,7 +22,84 @@ on top of cite:[SMBIOS], and is optional and recommended for BRS-B. Additional n | 41 | Onboard Devices Extended Information | Recommended | | 42 | Redfish Host Interface | Conditional | Required when Redfish host interface present. | 43 | TPM Device | Conditional | Required when TPM present. -| 44 | Standard Processor Additional Information | Required | +| 44 | Processor Additional Information | Required | | 45 | Firwmare Inventory Information | Recommended | | 46 | String Property | Recommended | |=== + +=== Type 44 Processor-Specific Data + +The following fields are defined to follow the standard processor-specific block fields (cite:[SMBIOS], Section 7.45.1). + +The structure is defined in a manner consistent with the DMTF specification +language (cite:[SMBIOS]). In addition, DQWORD is taken to mean a 128-bit value. + +The structure begins with a +a version field to allow for future extensibility in a backwards-compatible +manner. The version field is to be incremented any time fields are added. +The current version of the structure is 000Ah (v0.10). + +[cols="2,2,3,2,2,4", width=95%, align="center", options="header"] +|=== +| Offset | Version | Name | Length | Value | Description +| 00h|000Ah|Revision of RISC-V Processor-specific Block Structure|WORD|Varies|Bit 15:8 Major revision + +Bit 7:0 Minor revision + +The newer revision of RISC-V Processor-specific Block +Structure is backward compatible with older version of this structure. +|02h|000Ah|Structure Length|Byte|110|Length of Processor-specific Data +| 03h| 000Ah| Hart ID| DQWORD| Varies| The ID of this RISC-V Hart +| 13h| 000Ah| Boot Hart| BYTE| Boolean| 1: This is boot hart to boot system + +0: This is not the boot hart +| 14h| 000Ah| Machine Vendor ID | DQWORD| Varies| The vendor ID of this +RISC-V Hart +| 24h| 000Ah| Machine Architecture ID| DQWORD| Varies| Base +microarchitecture of the hart. Value of 0 is possible to indicate the field is +not implemented. The combination of Machine Architecture ID and Machine Vendor +ID should uniquely identify the type of hart microarchitecture that is implemented. +| 34h| 000Ah| Machine Implementation ID| DQWORD| Varies| Unique encoding +of the version of the processor implementation. Value of 0 is possible to indicate +the field is not implemented. The Implementation value should reflect the design of +the RISC-V Hart. +| 44h| 000Ah| Instruction set supported| DWORD| Bit-field | Bits [25:0] +encodes the presence of RISC-V standard extensions, which is equivalent to bits +[25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the +certain extensions of instruction set are supported on this hart. +| 48h| 000Ah| Privilege Level Supported| BYTE| Varies| The privilege levels +supported by this RISC-V Hart. + +Bit 0 Machine Mode + +BIT 1 Reserved + +BIT 2 Supervisor Mode + +Bit 3 User Mode + +BIT 6:4 Reserved + +BIT 7 Debug Mode +| 49H| 000Ah| Machine Exception Trap Delegation Information| DQWORD| Varies| +Bit set to one means the corresponding exception is delegated to supervisor execution +environment. Otherwise, supervisor execution environment must register the event +handler in Machine-Mode for the certain exceptions through environment call. +| 59H| 000Ah| Machine Interrupt Trap Delegation Information| DQWORD| Varies| +Bit set to one means the corresponding interrupt is delegated to supervisor execution +environment. Otherwise, supervisor execution environment must register the event +handler in Machine-Mode for the certain interrupts through environment. +| 69h| 000Ah| The register width (XLEN)| BYTE| ENUM| The width of register +supported by this RISC-V Hart +| 6Ah| 000Ah| Machine Mode native base integer ISA width (M-XLEN)| BYTE| ENUM| +The width (See below) of Machine Mode native base integer ISA supported by this RISC-V +Hart +| 6Bh| 000Ah| Reserved| BYTE| ENUM| Placeholder for Hypervisor Mode +| 6Ch| 000Ah| Supervisor Mode native base integer ISA width (S-XLEN)| BYTE| ENUM| +The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V +Hart +| 6Dh| 0000Ah| User Mode native base integer ISA width (U-XLEN)| BYTE| ENUM| The +width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart +|=== + +=== Encoding of RISC-V Native Base Integer ISA Width + +[cols="1,1", width=80%, align="center", options="header"] +|=== +| Byte Value | Meaning +| 00h| Unsupported +| 01h| 32-bit +| 02h| 64-bit +| 03h| 128-bit +|=== From 24b6234ad9331093dff000b55480775475d15f31 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 27 Nov 2023 20:40:29 -0600 Subject: [PATCH 2/9] smbios: remove structure len This field is unnecessary and redundant, because: a) type 44 header itself has a length field b) processor-specific block structure (7.5.4) contains another redundant length field An SMBIOS structure is limited by the width of the length field (byte), so we ought to make judicious use of the space, avoiding unnecessary redundancy. Signed-off-by: Andrei Warkentin --- smbios.adoc | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/smbios.adoc b/smbios.adoc index e83cb82..396b827 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -46,25 +46,24 @@ The current version of the structure is 000Ah (v0.10). Bit 7:0 Minor revision + The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure. -|02h|000Ah|Structure Length|Byte|110|Length of Processor-specific Data -| 03h| 000Ah| Hart ID| DQWORD| Varies| The ID of this RISC-V Hart -| 13h| 000Ah| Boot Hart| BYTE| Boolean| 1: This is boot hart to boot system + +| 02h| 000Ah| Hart ID| DQWORD| Varies| The ID of this RISC-V Hart +| 12h| 000Ah| Boot Hart| BYTE| Boolean| 1: This is boot hart to boot system + 0: This is not the boot hart -| 14h| 000Ah| Machine Vendor ID | DQWORD| Varies| The vendor ID of this +| 13h| 000Ah| Machine Vendor ID | DQWORD| Varies| The vendor ID of this RISC-V Hart -| 24h| 000Ah| Machine Architecture ID| DQWORD| Varies| Base +| 23h| 000Ah| Machine Architecture ID| DQWORD| Varies| Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. -| 34h| 000Ah| Machine Implementation ID| DQWORD| Varies| Unique encoding +| 33h| 000Ah| Machine Implementation ID| DQWORD| Varies| Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. -| 44h| 000Ah| Instruction set supported| DWORD| Bit-field | Bits [25:0] +| 43h| 000Ah| Instruction set supported| DWORD| Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. -| 48h| 000Ah| Privilege Level Supported| BYTE| Varies| The privilege levels +| 47h| 000Ah| Privilege Level Supported| BYTE| Varies| The privilege levels supported by this RISC-V Hart. + Bit 0 Machine Mode + BIT 1 Reserved + @@ -72,24 +71,24 @@ BIT 2 Supervisor Mode + Bit 3 User Mode + BIT 6:4 Reserved + BIT 7 Debug Mode -| 49H| 000Ah| Machine Exception Trap Delegation Information| DQWORD| Varies| +| 48H| 000Ah| Machine Exception Trap Delegation Information| DQWORD| Varies| Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call. -| 59H| 000Ah| Machine Interrupt Trap Delegation Information| DQWORD| Varies| +| 58H| 000Ah| Machine Interrupt Trap Delegation Information| DQWORD| Varies| Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. -| 69h| 000Ah| The register width (XLEN)| BYTE| ENUM| The width of register +| 68h| 000Ah| The register width (XLEN)| BYTE| ENUM| The width of register supported by this RISC-V Hart -| 6Ah| 000Ah| Machine Mode native base integer ISA width (M-XLEN)| BYTE| ENUM| +| 69h| 000Ah| Machine Mode native base integer ISA width (M-XLEN)| BYTE| ENUM| The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart -| 6Bh| 000Ah| Reserved| BYTE| ENUM| Placeholder for Hypervisor Mode -| 6Ch| 000Ah| Supervisor Mode native base integer ISA width (S-XLEN)| BYTE| ENUM| +| 6Ah| 000Ah| Reserved| BYTE| ENUM| Placeholder for Hypervisor Mode +| 6Bh| 000Ah| Supervisor Mode native base integer ISA width (S-XLEN)| BYTE| ENUM| The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart -| 6Dh| 0000Ah| User Mode native base integer ISA width (U-XLEN)| BYTE| ENUM| The +| 6Ch| 0000Ah| User Mode native base integer ISA width (U-XLEN)| BYTE| ENUM| The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart |=== From 2fa0f5e8d87d5774afca9b64d6beb218f7aab870 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 27 Nov 2023 20:44:37 -0600 Subject: [PATCH 3/9] smbios: remove 128-bit RV support for Type 44 entries It is really expensive to pad every CSR-like field to 16 bytes, especially since every structure is limited to 249 bytes (4 byte TLV header + 2 byte processor block header). - RV128 is not ratified. * It's not clear if the affected CSR values would really need to be padded. * Further changes may be needed to accommodate RV128 once ratified. * No one in the PRS/BRS groups is working on 128-bit designs, thus there is no need to complicate things. - SMBIOS itself is not 128-bit clean. * E.g. memory (type 16, type type 17) entries cannot encode a 128-bit memory size. * _SM3_ locator structure is not 128-bit clean * A lot more work is needed on 128-bit support, so bail on it for the time being. - We should err on the side of caution and attempt to minimize overall structure length. Technically the defined structure is sound for RV32, but the BRS document only focuses on RV64. Signed-off-by: Andrei Warkentin --- smbios.adoc | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/smbios.adoc b/smbios.adoc index 396b827..3961f5a 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -32,12 +32,10 @@ on top of cite:[SMBIOS], and is optional and recommended for BRS-B. Additional n The following fields are defined to follow the standard processor-specific block fields (cite:[SMBIOS], Section 7.45.1). The structure is defined in a manner consistent with the DMTF specification -language (cite:[SMBIOS]). In addition, DQWORD is taken to mean a 128-bit value. +language (cite:[SMBIOS]), and is valid for processors of architecture 07h (RV64) only. -The structure begins with a -a version field to allow for future extensibility in a backwards-compatible -manner. The version field is to be incremented any time fields are added. -The current version of the structure is 000Ah (v0.10). +The structure begins with a version field to allow for future extensibility in a backwards-compatible +manner. The version field is to be incremented any time fields are added. The current version of the structure is 000Ah (v0.10). [cols="2,2,3,2,2,4", width=95%, align="center", options="header"] |=== @@ -46,24 +44,24 @@ The current version of the structure is 000Ah (v0.10). Bit 7:0 Minor revision + The newer revision of RISC-V Processor-specific Block Structure is backward compatible with older version of this structure. -| 02h| 000Ah| Hart ID| DQWORD| Varies| The ID of this RISC-V Hart -| 12h| 000Ah| Boot Hart| BYTE| Boolean| 1: This is boot hart to boot system + +| 02h| 000Ah| Hart ID| QWORD| Varies| The ID of this RISC-V Hart +| 0Ah| 000Ah| Boot Hart| BYTE| Boolean| 1: This is boot hart to boot system + 0: This is not the boot hart -| 13h| 000Ah| Machine Vendor ID | DQWORD| Varies| The vendor ID of this +| 0Bh| 000Ah| Machine Vendor ID | QWORD| Varies| The vendor ID of this RISC-V Hart -| 23h| 000Ah| Machine Architecture ID| DQWORD| Varies| Base +| 13h| 000Ah| Machine Architecture ID| QWORD| Varies| Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. -| 33h| 000Ah| Machine Implementation ID| DQWORD| Varies| Unique encoding +| 1Bh| 000Ah| Machine Implementation ID| QWORD| Varies| Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. -| 43h| 000Ah| Instruction set supported| DWORD| Bit-field | Bits [25:0] +| 23h| 000Ah| Instruction set supported| DWORD| Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. -| 47h| 000Ah| Privilege Level Supported| BYTE| Varies| The privilege levels +| 27h| 000Ah| Privilege Level Supported| BYTE| Varies| The privilege levels supported by this RISC-V Hart. + Bit 0 Machine Mode + BIT 1 Reserved + @@ -71,24 +69,24 @@ BIT 2 Supervisor Mode + Bit 3 User Mode + BIT 6:4 Reserved + BIT 7 Debug Mode -| 48H| 000Ah| Machine Exception Trap Delegation Information| DQWORD| Varies| +| 28h| 000Ah| Machine Exception Trap Delegation Information| QWORD| Varies| Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call. -| 58H| 000Ah| Machine Interrupt Trap Delegation Information| DQWORD| Varies| +| 30h| 000Ah| Machine Interrupt Trap Delegation Information| QWORD| Varies| Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. -| 68h| 000Ah| The register width (XLEN)| BYTE| ENUM| The width of register +| 38h| 000Ah| The register width (XLEN)| BYTE| ENUM| The width of register supported by this RISC-V Hart -| 69h| 000Ah| Machine Mode native base integer ISA width (M-XLEN)| BYTE| ENUM| +| 39h| 000Ah| Machine Mode native base integer ISA width (M-XLEN)| BYTE| ENUM| The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart -| 6Ah| 000Ah| Reserved| BYTE| ENUM| Placeholder for Hypervisor Mode -| 6Bh| 000Ah| Supervisor Mode native base integer ISA width (S-XLEN)| BYTE| ENUM| +| 3Ah| 000Ah| Reserved| BYTE| ENUM| Placeholder for Hypervisor Mode +| 3Bh| 000Ah| Supervisor Mode native base integer ISA width (S-XLEN)| BYTE| ENUM| The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart -| 6Ch| 0000Ah| User Mode native base integer ISA width (U-XLEN)| BYTE| ENUM| The +| 3Ch| 0000Ah| User Mode native base integer ISA width (U-XLEN)| BYTE| ENUM| The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart |=== @@ -100,5 +98,5 @@ width (See below) of the User Mode native base integer ISA supported by this RIS | 00h| Unsupported | 01h| 32-bit | 02h| 64-bit -| 03h| 128-bit +| 03h| Unsupported |=== From cf37a704fb6854a2994dfe78920f3143c4096c35 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 27 Nov 2023 21:11:22 -0600 Subject: [PATCH 4/9] smbios: rework revision handling It's obvious at some point there may be incompatible changes. Allow for this by only treating minor rev increments as being backwards compatible. Major changes are treated as breaking changes. Also add a separate table to list revision changes. Since this patch set changes the PSD definitions, increment the major revision and clear the minor. This puts us at v1.0 (the original version for definitions at https://github.com/riscv/riscv-smbios/blob/main/riscv-smbios.adoc is v0.10). Signed-off-by: Andrei Warkentin --- smbios.adoc | 58 ++++++++++++++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 23 deletions(-) diff --git a/smbios.adoc b/smbios.adoc index 3961f5a..b43e322 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -29,39 +29,34 @@ on top of cite:[SMBIOS], and is optional and recommended for BRS-B. Additional n === Type 44 Processor-Specific Data -The following fields are defined to follow the standard processor-specific block fields (cite:[SMBIOS], Section 7.45.1). +The processor-specific data structure fields are defined to follow the standard Processor-Specific Block fields (cite:[SMBIOS], Section 7.45.1). The structure is defined in a manner consistent with the DMTF specification -language (cite:[SMBIOS]), and is valid for processors of architecture 07h (RV64) only. - -The structure begins with a version field to allow for future extensibility in a backwards-compatible -manner. The version field is to be incremented any time fields are added. The current version of the structure is 000Ah (v0.10). +language (cite:[SMBIOS]), and is valid for processors declared as +architecture 07h (64-bit RISC-V) only. [cols="2,2,3,2,2,4", width=95%, align="center", options="header"] |=== | Offset | Version | Name | Length | Value | Description -| 00h|000Ah|Revision of RISC-V Processor-specific Block Structure|WORD|Varies|Bit 15:8 Major revision + -Bit 7:0 Minor revision + -The newer revision of RISC-V Processor-specific Block -Structure is backward compatible with older version of this structure. -| 02h| 000Ah| Hart ID| QWORD| Varies| The ID of this RISC-V Hart -| 0Ah| 000Ah| Boot Hart| BYTE| Boolean| 1: This is boot hart to boot system + +| 00h| 0100h|Revision|WORD|Varies|See <>. +| 02h| 0100h| Hart ID| QWORD| Varies| The ID of this RISC-V Hart +| 0Ah| 0100h| Boot Hart| BYTE| Boolean| 1: This is boot hart to boot system + 0: This is not the boot hart -| 0Bh| 000Ah| Machine Vendor ID | QWORD| Varies| The vendor ID of this +| 0Bh| 0100h| Machine Vendor ID | QWORD| Varies| The vendor ID of this RISC-V Hart -| 13h| 000Ah| Machine Architecture ID| QWORD| Varies| Base +| 13h| 0100h| Machine Architecture ID| QWORD| Varies| Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. -| 1Bh| 000Ah| Machine Implementation ID| QWORD| Varies| Unique encoding +| 1Bh| 0100h| Machine Implementation ID| QWORD| Varies| Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. -| 23h| 000Ah| Instruction set supported| DWORD| Bit-field | Bits [25:0] +| 23h| 0100h| Instruction set supported| DWORD| Bit-field | Bits [25:0] encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. -| 27h| 000Ah| Privilege Level Supported| BYTE| Varies| The privilege levels +| 27h| 0100h| Privilege Level Supported| BYTE| Varies| The privilege levels supported by this RISC-V Hart. + Bit 0 Machine Mode + BIT 1 Reserved + @@ -69,27 +64,44 @@ BIT 2 Supervisor Mode + Bit 3 User Mode + BIT 6:4 Reserved + BIT 7 Debug Mode -| 28h| 000Ah| Machine Exception Trap Delegation Information| QWORD| Varies| +| 28h| 0100h| Machine Exception Trap Delegation Information| QWORD| Varies| Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call. -| 30h| 000Ah| Machine Interrupt Trap Delegation Information| QWORD| Varies| +| 30h| 0100h| Machine Interrupt Trap Delegation Information| QWORD| Varies| Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. -| 38h| 000Ah| The register width (XLEN)| BYTE| ENUM| The width of register +| 38h| 0100h| The register width (XLEN)| BYTE| ENUM| The width of register supported by this RISC-V Hart -| 39h| 000Ah| Machine Mode native base integer ISA width (M-XLEN)| BYTE| ENUM| +| 39h| 0100h| Machine Mode native base integer ISA width (M-XLEN)| BYTE| ENUM| The width (See below) of Machine Mode native base integer ISA supported by this RISC-V Hart -| 3Ah| 000Ah| Reserved| BYTE| ENUM| Placeholder for Hypervisor Mode -| 3Bh| 000Ah| Supervisor Mode native base integer ISA width (S-XLEN)| BYTE| ENUM| +| 3Ah| 0100h| Reserved| BYTE| ENUM| Placeholder for Hypervisor Mode +| 3Bh| 0100h| Supervisor Mode native base integer ISA width (S-XLEN)| BYTE| ENUM| The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V Hart -| 3Ch| 0000Ah| User Mode native base integer ISA width (U-XLEN)| BYTE| ENUM| The +| 3Ch| 00100h| User Mode native base integer ISA width (U-XLEN)| BYTE| ENUM| The width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart |=== +[[smbios-psd-ver]] +=== Processor-Specific Data Structure Versioning + +The processor-specific data structure begins with a revision field to allow for future extensibility in a backwards-compatible manner. + +The minor revision is to be incremented anytime new fields are added in a backwards-compatible manner. The major revision is to be incremented on backwards-incompatible changes. + +[cols="1,1,1,1,3", width=95%, align="center", options="header"] +|=== +| Version | Bits 15:8+ +Major revision +| Bits 7:0+ +Minor revision +| Combined | Description +| v1.0 | 01h | 00h | 0100h | First BRS-defined definition +|=== + === Encoding of RISC-V Native Base Integer ISA Width [cols="1,1", width=80%, align="center", options="header"] From 40e5d7dfc68decc847a4bf9fc88fdad7bc825754 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 27 Nov 2023 21:15:36 -0600 Subject: [PATCH 5/9] smbios: nuke the XLEN fields SMBIOS is used to describe physical assets of a system. For a processor this may include uArch/SoC/vendor versioning, but the XLEN fields themselves aren't useful - and if they are, they belong in other specs that are critical to OS startup. As mentioned previously, SMBIOS struct len is a bit of a premium so there needs to be a great reason to include particular info. Signed-off-by: Andrei Warkentin --- smbios.adoc | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/smbios.adoc b/smbios.adoc index b43e322..6f7cf16 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -72,17 +72,6 @@ handler in Machine-Mode for the certain exceptions through environment call. Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. -| 38h| 0100h| The register width (XLEN)| BYTE| ENUM| The width of register -supported by this RISC-V Hart -| 39h| 0100h| Machine Mode native base integer ISA width (M-XLEN)| BYTE| ENUM| -The width (See below) of Machine Mode native base integer ISA supported by this RISC-V -Hart -| 3Ah| 0100h| Reserved| BYTE| ENUM| Placeholder for Hypervisor Mode -| 3Bh| 0100h| Supervisor Mode native base integer ISA width (S-XLEN)| BYTE| ENUM| -The width (See below) of Supervisor Mode native base integer ISA supported by this RISC-V -Hart -| 3Ch| 00100h| User Mode native base integer ISA width (U-XLEN)| BYTE| ENUM| The -width (See below) of the User Mode native base integer ISA supported by this RISC-V Hart |=== [[smbios-psd-ver]] @@ -101,14 +90,3 @@ Minor revision | Combined | Description | v1.0 | 01h | 00h | 0100h | First BRS-defined definition |=== - -=== Encoding of RISC-V Native Base Integer ISA Width - -[cols="1,1", width=80%, align="center", options="header"] -|=== -| Byte Value | Meaning -| 00h| Unsupported -| 01h| 32-bit -| 02h| 64-bit -| 03h| Unsupported -|=== From 29331ad250a26c43064392d8ec1505d915a39e88 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 27 Nov 2023 21:18:20 -0600 Subject: [PATCH 6/9] smbios: remove Privilege Level Supported Similarly to the XLEN fields, the priv. level is not at all interesting from a physical asset standpoint. If an OS needs to know this info, it needs to get it via DT/ACPI. Signed-off-by: Andrei Warkentin --- smbios.adoc | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/smbios.adoc b/smbios.adoc index 6f7cf16..7d03363 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -56,19 +56,11 @@ the RISC-V Hart. encodes the presence of RISC-V standard extensions, which is equivalent to bits [25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the certain extensions of instruction set are supported on this hart. -| 27h| 0100h| Privilege Level Supported| BYTE| Varies| The privilege levels -supported by this RISC-V Hart. + -Bit 0 Machine Mode + -BIT 1 Reserved + -BIT 2 Supervisor Mode + -Bit 3 User Mode + -BIT 6:4 Reserved + -BIT 7 Debug Mode -| 28h| 0100h| Machine Exception Trap Delegation Information| QWORD| Varies| +| 27h| 0100h| Machine Exception Trap Delegation Information| QWORD| Varies| Bit set to one means the corresponding exception is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain exceptions through environment call. -| 30h| 0100h| Machine Interrupt Trap Delegation Information| QWORD| Varies| +| 2fh| 0100h| Machine Interrupt Trap Delegation Information| QWORD| Varies| Bit set to one means the corresponding interrupt is delegated to supervisor execution environment. Otherwise, supervisor execution environment must register the event handler in Machine-Mode for the certain interrupts through environment. From 11b7e6d464467c076b62710a2cbc742550d65b62 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 27 Nov 2023 21:20:58 -0600 Subject: [PATCH 7/9] smbios: remove misa and M-mode delegation info Similarly to XLEN and priv-level, this info is not interesting from an asset/physical perspective. If an OS needs it, it needs to be provided via DT/ACPI. Signed-off-by: Andrei Warkentin --- smbios.adoc | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/smbios.adoc b/smbios.adoc index 7d03363..180fae8 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -52,18 +52,6 @@ ID should uniquely identify the type of hart microarchitecture that is implement of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V Hart. -| 23h| 0100h| Instruction set supported| DWORD| Bit-field | Bits [25:0] -encodes the presence of RISC-V standard extensions, which is equivalent to bits -[25:0] in RISC-V Machine ISA Register (**misa** CSR). Bits set to one mean the -certain extensions of instruction set are supported on this hart. -| 27h| 0100h| Machine Exception Trap Delegation Information| QWORD| Varies| -Bit set to one means the corresponding exception is delegated to supervisor execution -environment. Otherwise, supervisor execution environment must register the event -handler in Machine-Mode for the certain exceptions through environment call. -| 2fh| 0100h| Machine Interrupt Trap Delegation Information| QWORD| Varies| -Bit set to one means the corresponding interrupt is delegated to supervisor execution -environment. Otherwise, supervisor execution environment must register the event -handler in Machine-Mode for the certain interrupts through environment. |=== [[smbios-psd-ver]] From ebc77cd4c3e59bdd68336eb8ab926beedbbfbf89 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 27 Nov 2023 21:27:23 -0600 Subject: [PATCH 8/9] smbios: cleanup Hart->hart Also clarify the mimpid-derived value is not per-hart, it is per-processor (matches the ISA spec, but ought to be clarified that a processor may be a SoC?) Signed-off-by: Andrei Warkentin --- smbios.adoc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/smbios.adoc b/smbios.adoc index 180fae8..281a72b 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -39,11 +39,11 @@ architecture 07h (64-bit RISC-V) only. |=== | Offset | Version | Name | Length | Value | Description | 00h| 0100h|Revision|WORD|Varies|See <>. -| 02h| 0100h| Hart ID| QWORD| Varies| The ID of this RISC-V Hart -| 0Ah| 0100h| Boot Hart| BYTE| Boolean| 1: This is boot hart to boot system + -0: This is not the boot hart +| 02h| 0100h| Hart ID| QWORD| Varies| The ID of this RISC-V hart +| 0Ah| 0100h| Boot hart| BYTE| Boolean| 1: This is the boot hart. + +0: This is not the boot hart. | 0Bh| 0100h| Machine Vendor ID | QWORD| Varies| The vendor ID of this -RISC-V Hart +RISC-V hart | 13h| 0100h| Machine Architecture ID| QWORD| Varies| Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor @@ -51,7 +51,7 @@ ID should uniquely identify the type of hart microarchitecture that is implement | 1Bh| 0100h| Machine Implementation ID| QWORD| Varies| Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of -the RISC-V Hart. +the RISC-V processor and not the surrounding system. |=== [[smbios-psd-ver]] From acd497ed3b5b49f478059da924649240069bad4a Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Mon, 4 Dec 2023 14:24:03 -0600 Subject: [PATCH 9/9] smbios: remove boot hart info Dups info already available to boot software (via UEFI) and not useful from an asset tracking perspective. Signed-off-by: Andrei Warkentin --- smbios.adoc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/smbios.adoc b/smbios.adoc index 281a72b..0db3412 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -40,15 +40,13 @@ architecture 07h (64-bit RISC-V) only. | Offset | Version | Name | Length | Value | Description | 00h| 0100h|Revision|WORD|Varies|See <>. | 02h| 0100h| Hart ID| QWORD| Varies| The ID of this RISC-V hart -| 0Ah| 0100h| Boot hart| BYTE| Boolean| 1: This is the boot hart. + -0: This is not the boot hart. -| 0Bh| 0100h| Machine Vendor ID | QWORD| Varies| The vendor ID of this +| 0Ah| 0100h| Machine Vendor ID | QWORD| Varies| The vendor ID of this RISC-V hart -| 13h| 0100h| Machine Architecture ID| QWORD| Varies| Base +| 12h| 0100h| Machine Architecture ID| QWORD| Varies| Base microarchitecture of the hart. Value of 0 is possible to indicate the field is not implemented. The combination of Machine Architecture ID and Machine Vendor ID should uniquely identify the type of hart microarchitecture that is implemented. -| 1Bh| 0100h| Machine Implementation ID| QWORD| Varies| Unique encoding +| 1Ah| 0100h| Machine Implementation ID| QWORD| Varies| Unique encoding of the version of the processor implementation. Value of 0 is possible to indicate the field is not implemented. The Implementation value should reflect the design of the RISC-V processor and not the surrounding system.