From 4da60201c3779c9f17232be761e3920d203cc244 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Fri, 31 May 2024 12:49:22 -0500 Subject: [PATCH] Fix https://github.com/riscv-non-isa/riscv-brs/issues/168 (#171) Describes the scheme by which JEP-106 codes are compressed to fit within a 32-bit value. Signed-off-by: Andrei Warkentin --- smbios.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/smbios.adoc b/smbios.adoc index 246de5e..e7b5ba0 100644 --- a/smbios.adoc +++ b/smbios.adoc @@ -44,7 +44,7 @@ A processor is a grouping of harts in a physical package. In modern designs this For RISC-V class CPUs, the `Processor ID` field contains two `DWORD`-formatted values describing the overall physical processor package vendor and version. For some implementations this may also be known as the SoC ID. The first `DWORD` (offsets 08h-0Bh) is the JEP-106 code for -the vendor. The second `DWORD` (offsets 0Ch-0Fh) reflects vendor-specific part versioning. +the vendor, where bits 6:0 is the ID without the parity and bits 31:7 represent the number of continuation codes. The second `DWORD` (offsets 0Ch-0Fh) reflects vendor-specific part versioning. For hart-specific vendor and revision information, please see Type 44 Processor-Specific Data structures.