From 19d9faa568688604f14623987977e2c62d4fa8b0 Mon Sep 17 00:00:00 2001 From: Daniel Maslowski Date: Mon, 16 Oct 2023 19:25:32 +0200 Subject: [PATCH] Add initial notes on trap handlers Signed-off-by: Daniel Maslowski --- trap-handlers.adoc | 59 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 trap-handlers.adoc diff --git a/trap-handlers.adoc b/trap-handlers.adoc new file mode 100644 index 0000000..380752e --- /dev/null +++ b/trap-handlers.adoc @@ -0,0 +1,59 @@ +[[trap-handlers]] +== Machine-Level Interrupts and Exceptions + +=== Delegation + +A RISC-V Machine mode execution environment may delegate handling interrupts and exceptions to the Supervisor or Hypervisor mode execution environment. + +For reference, see https://github.com/riscv/riscv-isa-manual/blob/main/src/machine.adoc#machine-cause-register-mcause[the definitions in the RISC-V ISA spec]. + +==== Interrupts +[%autowidth,float="center",align="center",cols=">,>,<",options="header",] +|=== +| Code / Description |OpenSBI |oreboot SBI +|0 _Reserved_ + +1 Supervisor software interrupt + +2 _Reserved_ + +3 Machine software interrupt + +4 _Reserved_ + +5 Supervisor timer interrupt + +6 _Reserved_ + +7 Machine timer interrupt + +8 _Reserved_ + +9 Supervisor external interrupt + +10 _Reserved_ + +11 Machine external interrupt +12-15 _Reserved_ + +≥16 _Designated for platform use_ +| O + +O + +O + +O + +O + +O + +O + +O + +O + +O + +O + +O + +O +| O + +O + +O + +O + +O + +O + +O + +O + +O + +O + +O + +O + +O + +X = explicitly set +O = explicitly unset +I = initial value unchanged + +==== Exceptions