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PLIC on SAIL model #34
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Hi, @ptprasanna, I've added the SOW template to your first comment and moved your text into the requirements section. Let's edit it there as-needed. Thanks! |
What's the point of having a PLIC without any devices attached to it that can generate interrupts? |
Today's DevPartners meeting suggested that this work is on-going to create a PLIC infrastructure in SAIL and it will include a basic framework for testing interrupts. The open question for the DevPartner's meeting is to determine how much to track here so as not to duplicate work. At this time, I view this item as FYI for us. |
PLIC : Algorithm has been completed and coding in progress. Hoping to get this done by this week and will send the code to Bill for review. Testing : Sail(PLIC) will be listening on a certain port. And an external software will send the interrupt messages to PLIC on that port. We'll use system call for this. |
@ptprasanna, do we have a target date by which all work is anticipated to be done, including PR acceptance? |
NB: Bill doesn't review the code, the community does |
@jrtc27, indeed. I suspect that because the person is new, they're actually "pre-reviewing" the code with Bill. Everyone understands that the community will review the code, comment, and ultimately accept the PR. |
Ack |
Planning to submit the ongoing work for peer review by this week. |
@billmcspadden-riscv, if you could provide and outlook on when a review of the code might be expected, that would help @ptprasanna. Thanks!!! |
@billmcspadden-riscv promises feedback this week. Thanks, Bill!!! |
@ptprasanna, please see the email to your gmail account on Bill's needs. |
@ptprasanna, I would like an update in the issue, by the next meeting on December 12, 2023, please. |
@anuani21, can you see if there's any status here. @billmcspadden-riscv, is this the issue stalled behind the test framework work? |
Hi Jeff,
I will check with my team and update the status on this item.
Regards,
Anusha
…On Tue, 30 Jan, 2024, 4:55 pm Jeff Scheel, ***@***.***> wrote:
@anuani21 <https://github.com/anuani21>, can you see if there's any
status here. @billmcspadden-riscv <https://github.com/billmcspadden-riscv>,
is this the issue stalled behind the test framework work?
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Thanks, @anuani21. Please post when you have information. |
Per @anuani21, the developer working on this has been pulled away with other activities. Anusha can we please get an outlook for when they might be back? Additionally, it would be helpful to add the developer as an assignee to the issue. Are they in Groups.IO as a RISC-V member? If not, we should get them there too so as to receive the mailing list information for the group. |
++saravanan
…On Thu, Feb 22, 2024 at 7:29 PM Jeff Scheel ***@***.***> wrote:
Per @anuani21 <https://github.com/anuani21>, the developer working on
this has been pulled away with other activities. Anusha can we please get
an outlook for when they might be back?
Additionally, it would be helpful to add the developer as an assignee to
the issue. Are they in Groups.IO as a RISC-V member? If not, we should get
them there too so as to receive the mailing list information for the group.
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@ptprasanna, @anuani21, would you kindly provide status for the August 20 meeting on this item. Thanks! |
Hi Sir , |
Thanks, Jayanth. I've asked @billmcspadden-riscv to reach out to you via your personal email. When you get your IITM email, we'll get you authorized to things. Please let me know. Thanks for getting started on this!!! |
Updates , @jjscheel No progress since last call , was working on Zce ACT |
Updates from IIT-M , Made changes suggested by bill here (https://github.com/saravanakumarsastra/sail-riscv/tree/billmc-comments) in my github repo and shared it for review Github link : https://github.com/JAYANTH-IITM/sail-riscv |
Hi @billmcspadden-riscv , |
Status Update : Sent for review to bill after making the suggested changes. |
Technical Group
PLIC
ratification-pkg
PLIC
Technical Liaison
Prasanna
Task Category
SAIL
Task Sub Category
Ratification Target
2022
Statement of Work (SOW)
Component names:
Requirements:
Developing PLIC extension of Riscv Specification, on Sail model using sail programming language. By implementing memory mapped registers on sail for handling the externally generated interrupts (platform generated interrupts).
Deliverables:
...
Acceptance Criteria:
...
Projected timeframe: (best guess date)
SOW Signoffs:
Waiver
Pull Request Details
No response
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