From d9c615122cd56aa7cdcb48ef76b1d5fa2eae2251 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 11 Sep 2024 16:18:10 -0500
Subject: [PATCH 01/10] Change div_int_frac methods to be suffixed by the
 number of bits of fact; e.g. div_int_frac8

---
 src/rp2_common/hardware_clocks/clocks.c       | 10 ++++--
 .../hardware_clocks/include/hardware/clocks.h | 32 ++++++++++++++---
 .../hardware_pio/include/hardware/pio.h       | 14 +++++---
 .../hardware_pwm/include/hardware/pwm.h       | 36 ++++++++++++-------
 4 files changed, 70 insertions(+), 22 deletions(-)

diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c
index e04cebefc..dce26ee12 100644
--- a/src/rp2_common/hardware_clocks/clocks.c
+++ b/src/rp2_common/hardware_clocks/clocks.c
@@ -228,7 +228,7 @@ void clocks_enable_resus(resus_callback_t resus_callback) {
     clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout;
 }
 
-void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac) {
+void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t div_frac16) {
     // Bit messy but it's as much code to loop through a lookup
     // table. The sources for each gpout generators are the same
     // so just call with the sources from GP0
@@ -248,7 +248,13 @@ void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div
     // Set up the gpclk generator
     clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |
                                  CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS;
-    clocks_hw->clk[gpclk].div = (div_int << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) | div_frac;
+#if CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB - CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB == 15
+    clocks_hw->clk[gpclk].div = (div_int << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) | (div_frac16 << CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB);
+#elif CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB - CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB == 7
+    clocks_hw->clk[gpclk].div = (div_int << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) | ((div_frac16>>8u) << CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB);
+#else
+#error unsupported number of fractional bits
+#endif
 
     // Set gpio pin to gpclock function
     gpio_set_function(gpio, GPIO_FUNC_GPCK);
diff --git a/src/rp2_common/hardware_clocks/include/hardware/clocks.h b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
index 7ad577e87..d1cee576e 100644
--- a/src/rp2_common/hardware_clocks/include/hardware/clocks.h
+++ b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
@@ -354,9 +354,26 @@ void clocks_enable_resus(resus_callback_t resus_callback);
  * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
  * \param src  The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
  * \param div_int  The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. this is in range of 1..2^24-1.
- * \param div_frac The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).
+ * \param div_frac16 The fractional part of the value to divide the source clock by. This is in range of 0..65536 (/65536).
  */
-void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac);
+void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t div_frac16);
+
+/*! \brief Output an optionally divided clock to the specified gpio pin.
+ *  \ingroup hardware_clocks
+ *
+ * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
+ * \param src  The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
+ * \param div_int  The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. this is in range of 1..2^24-1.
+ * \param div_frac8 The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).
+ */
+static inline void clock_gpio_init_int_frac8(uint gpio, uint src, uint32_t div_int, uint8_t div_frac8) {
+    return clock_gpio_init_int_frac16(gpio, src, div_int, div_frac8 << 8u);
+}
+
+// backwards compatibility
+static inline void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac8) {
+    return clock_gpio_init_int_frac8(gpio, src, div_int, div_frac8);
+}
 
 /*! \brief Output an optionally divided clock to the specified gpio pin.
  *  \ingroup hardware_clocks
@@ -368,8 +385,15 @@ void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div
 static inline void clock_gpio_init(uint gpio, uint src, float div)
 {
     uint div_int = (uint)div;
-    uint8_t frac = (uint8_t)((div - (float)div_int) * (1u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB));
-    clock_gpio_init_int_frac(gpio, src, div_int, frac);
+#if CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB - CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB == 15
+    uint16_t frac = (uint16_t)((div - (float)div_int) * (1u << 16));
+    clock_gpio_init_int_frac16(gpio, src, div_int, frac);
+#elif CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB - CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB == 7
+    uint8_t frac = (uint8_t)((div - (float)div_int) * (1u << 8));
+    clock_gpio_init_int_frac8(gpio, src, div_int, frac);
+#else
+#error unsupported number of fractional bits
+#endif
 }
 
 /*! \brief Configure a clock to come from a gpio input
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index 5d51237b1..1bad3f296 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -1643,17 +1643,23 @@ void pio_sm_drain_tx_fifo(PIO pio, uint sm);
  * \param pio The PIO instance; e.g. \ref pio0 or \ref pio1
  * \param sm State machine index (0..3)
  * \param div_int the integer part of the clock divider
- * \param div_frac the fractional part of the clock divider in 1/256s
+ * \param div_frac8 the fractional part of the clock divider in 1/256s
  */
-static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) {
+static inline void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac8) {
     check_pio_param(pio);
     check_sm_param(sm);
-    invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0);
+    invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
+    static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
     pio->sm[sm].clkdiv =
-            (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
+            (((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
             (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
 }
 
+// backwards compatibility
+static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac8) {
+    pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac8);
+}
+
 /*! \brief set the current clock divider for a state machine
  *  \ingroup hardware_pio
  *
diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
index d4da7e52b..50dac53fe 100644
--- a/src/rp2_common/hardware_pwm/include/hardware/pwm.h
+++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
@@ -162,17 +162,23 @@ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
  *  \ingroup hardware_pwm
  *
  * \param c PWM configuration struct to modify
- * \param integer 8 bit integer part of the clock divider. Must be greater than or equal to 1.
- * \param fract 4 bit fractional part of the clock divider
+ * \param div_int 8 bit integer part of the clock divider. Must be greater than or equal to 1.
+ * \param div_frac4 4 bit fractional part of the clock divider
  *
  * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
  * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
  * before passing them on to the PWM counter.
  */
-static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t fract) {
-    valid_params_if(HARDWARE_PWM, integer >= 1);
-    valid_params_if(HARDWARE_PWM, fract < 16);
-    c->div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
+static inline void pwm_config_set_clkdiv_int_frac4(pwm_config *c, uint8_t div_int, uint8_t div_frac4) {
+    valid_params_if(HARDWARE_PWM, div_int >= 1);
+    static_assert(PWM_CH0_DIV_FRAC_MSB - PWM_CH0_DIV_FRAC_LSB == 3, "");
+    valid_params_if(HARDWARE_PWM, div_frac4 < 16);
+    c->div = (((uint)div_int) << PWM_CH0_DIV_INT_LSB) | (((uint)div_frac4) << PWM_CH0_DIV_FRAC_LSB);
+}
+
+// backwards compatibility
+static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t frac4) {
+    pwm_config_set_clkdiv_int_frac4(c, integer, frac4);
 }
 
 /** \brief Set PWM clock divider in a PWM configuration
@@ -427,14 +433,20 @@ static inline void pwm_retard_count(uint slice_num) {
  * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
  *
  * \param slice_num PWM slice number
- * \param integer  8 bit integer part of the clock divider
- * \param fract 4 bit fractional part of the clock divider
+ * \param div_int  8 bit integer part of the clock divider
+ * \param div_frac4 4 bit fractional part of the clock divider
  */
-static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) {
+static inline void pwm_set_clkdiv_int_frac4(uint slice_num, uint8_t div_int, uint8_t div_frac4) {
     check_slice_num_param(slice_num);
-    valid_params_if(HARDWARE_PWM, integer >= 1);
-    valid_params_if(HARDWARE_PWM, fract < 16);
-    pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
+    valid_params_if(HARDWARE_PWM, div_int >= 1);
+    static_assert(PWM_CH0_DIV_FRAC_MSB - PWM_CH0_DIV_FRAC_LSB == 3, "");
+    valid_params_if(HARDWARE_PWM, div_frac4 < 16);
+    pwm_hw->slice[slice_num].div = (((uint)div_int) << PWM_CH0_DIV_INT_LSB) | (((uint)div_frac4) << PWM_CH0_DIV_FRAC_LSB);
+}
+
+// backwards compatibility
+static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t div_int, uint8_t div_frac4) {
+    pwm_set_clkdiv_int_frac4(slice_num, div_int, div_frac4);
 }
 
 /** \brief Set PWM clock divider

From 765aeb860781715b0b129fd15298bfd5389711d1 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 11 Sep 2024 16:55:36 -0500
Subject: [PATCH 02/10] catch some more uses of int_frac, add some assertions
 to catch possible future h/w change regresions

---
 .../hardware_pio/include/hardware/pio.h       | 31 +++++++++++++------
 .../hardware_pwm/include/hardware/pwm.h       |  9 +++---
 .../pico_cyw43_driver/cyw43_bus_pio_spi.c     | 10 +++---
 .../include/pico/cyw43_driver.h               | 19 +++++++++---
 4 files changed, 45 insertions(+), 24 deletions(-)

diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index 1bad3f296..cb4d8fd77 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -468,19 +468,29 @@ static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool
  *
  * \param c Pointer to the configuration structure to modify
  * \param div_int Integer part of the divisor
- * \param div_frac Fractional part in 1/256ths
+ * \param div_frac8 Fractional part in 1/256ths
  * \sa sm_config_set_clkdiv()
  */
-static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) {
-    invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0);
+static inline void sm_config_set_clkdiv_int_frac8(pio_sm_config *c, uint16_t div_int, uint8_t div_frac8) {
+    invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
+    static_assert(PIO_SM0_CLKDIV_INT_MSB - PIO_SM0_CLKDIV_INT_LSB == 15, "");
+    static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
     c->clkdiv =
-            (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
+            (((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
             (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
 }
 
-static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) {
+// backwards compatibility
+static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac8) {
+    sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
+}
+
+static inline void pio_calculate_clkdiv8_from_float(float div, uint16_t *div_int, uint8_t *div_frac) {
     valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536);
     *div_int = (uint16_t)div;
+    // not a strictly necessary check, but if this changes, then this method should
+    // probably no longer be used in favor of one with a larger fraction
+    static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
     if (*div_int == 0) {
         *div_frac = 0;
     } else {
@@ -506,8 +516,8 @@ static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int,
 static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) {
     uint16_t div_int;
     uint8_t div_frac;
-    pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
-    sm_config_set_clkdiv_int_frac(c, div_int, div_frac);
+    pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac);
+    sm_config_set_clkdiv_int_frac8(c, div_int, div_frac);
 }
 
 /*! \brief Set the wrap addresses in a state machine configuration
@@ -664,7 +674,7 @@ static inline pio_sm_config pio_get_default_sm_config(void) {
 #if PICO_PIO_USE_GPIO_BASE
     c.pinhi = -1;
 #endif
-    sm_config_set_clkdiv_int_frac(&c, 1, 0);
+    sm_config_set_clkdiv_int_frac8(&c, 1, 0);
     sm_config_set_wrap(&c, 0, 31);
     sm_config_set_in_shift(&c, true, false, 32);
     sm_config_set_out_shift(&c, true, false, 32);
@@ -1649,6 +1659,7 @@ static inline void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint16_t div_in
     check_pio_param(pio);
     check_sm_param(sm);
     invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
+    static_assert(PIO_SM0_CLKDIV_INT_MSB - PIO_SM0_CLKDIV_INT_LSB == 15, "");
     static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
     pio->sm[sm].clkdiv =
             (((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
@@ -1672,8 +1683,8 @@ static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
     check_sm_param(sm);
     uint16_t div_int;
     uint8_t div_frac;
-    pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
-    pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac);
+    pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac);
+    pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac);
 }
 
 /*! \brief Clear a state machine's TX and RX FIFOs
diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
index 50dac53fe..684c0c1c0 100644
--- a/src/rp2_common/hardware_pwm/include/hardware/pwm.h
+++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
@@ -171,14 +171,15 @@ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
  */
 static inline void pwm_config_set_clkdiv_int_frac4(pwm_config *c, uint8_t div_int, uint8_t div_frac4) {
     valid_params_if(HARDWARE_PWM, div_int >= 1);
+    static_assert(PWM_CH0_DIV_INT_MSB - PWM_CH0_DIV_INT_LSB == 7, "");
     static_assert(PWM_CH0_DIV_FRAC_MSB - PWM_CH0_DIV_FRAC_LSB == 3, "");
     valid_params_if(HARDWARE_PWM, div_frac4 < 16);
     c->div = (((uint)div_int) << PWM_CH0_DIV_INT_LSB) | (((uint)div_frac4) << PWM_CH0_DIV_FRAC_LSB);
 }
 
 // backwards compatibility
-static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t frac4) {
-    pwm_config_set_clkdiv_int_frac4(c, integer, frac4);
+static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t div_int, uint8_t div_frac4) {
+    pwm_config_set_clkdiv_int_frac4(c, div_int, div_frac4);
 }
 
 /** \brief Set PWM clock divider in a PWM configuration
@@ -193,7 +194,7 @@ static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer
  */
 static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
     valid_params_if(HARDWARE_PWM, div >= 1 && div < 256);
-    pwm_config_set_clkdiv_int_frac(c, (uint8_t)div, 0);
+    pwm_config_set_clkdiv_int_frac8(c, (uint8_t)div, 0);
 }
 
 /** \brief Set PWM counting mode in a PWM configuration
@@ -462,7 +463,7 @@ static inline void pwm_set_clkdiv(uint slice_num, float divider) {
     valid_params_if(HARDWARE_PWM, divider >= 1.f && divider < 256.f);
     uint8_t i = (uint8_t)divider;
     uint8_t f = (uint8_t)((divider - i) * (0x01 << 4));
-    pwm_set_clkdiv_int_frac(slice_num, i, f);
+    pwm_set_clkdiv_int_frac8(slice_num, i, f);
 }
 
 /** \brief Set PWM output polarity
diff --git a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
index d9265dd0b..2d827632e 100644
--- a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
+++ b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
@@ -43,14 +43,14 @@ static_assert((CYW43_PIN_WL_DATA_OUT < 32 && CYW43_PIN_WL_DATA_IN < 32 && CYW43_
 
 #if !CYW43_PIO_CLOCK_DIV_DYNAMIC
 #define cyw43_pio_clock_div_int CYW43_PIO_CLOCK_DIV_INT
-#define cyw43_pio_clock_div_frac CYW43_PIO_CLOCK_DIV_FRAC
+#define cyw43_pio_clock_div_frac8 CYW43_PIO_CLOCK_DIV_FRAC8
 #else
 static uint16_t cyw43_pio_clock_div_int = CYW43_PIO_CLOCK_DIV_INT;
-static uint8_t cyw43_pio_clock_div_frac = CYW43_PIO_CLOCK_DIV_FRAC;
+static uint8_t cyw43_pio_clock_div_frac8 = CYW43_PIO_CLOCK_DIV_FRAC8;
 
-void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac) {
+void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac8) {
     cyw43_pio_clock_div_int = clock_div_int;
-    cyw43_pio_clock_div_frac = clock_div_frac;
+    cyw43_pio_clock_div_frac8 = clock_div_frac8;
 }
 #endif
 
@@ -114,7 +114,7 @@ int cyw43_spi_init(cyw43_int_t *self) {
     }
     pio_sm_config config = SPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC(bus_data->pio_offset);
 
-    sm_config_set_clkdiv_int_frac(&config, cyw43_pio_clock_div_int, cyw43_pio_clock_div_frac);
+    sm_config_set_clkdiv_int_frac8(&config, cyw43_pio_clock_div_int, cyw43_pio_clock_div_frac8);
     hw_write_masked(&pads_bank0_hw->io[CYW43_PIN_WL_CLOCK],
                     (uint)PADS_DRIVE_STRENGTH << PADS_BANK0_GPIO0_DRIVE_LSB,
                     PADS_BANK0_GPIO0_DRIVE_BITS
diff --git a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
index 633c7ad1f..6de3f1b92 100644
--- a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
+++ b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
@@ -58,9 +58,13 @@ void cyw43_driver_deinit(struct async_context *context);
 #endif
 #endif
 
-// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC, Fractional part of the clock divider for communication with the wireless chip, type=bool, default=0, group=pico_cyw43_driver
-#ifndef CYW43_PIO_CLOCK_DIV_FRAC
-#define CYW43_PIO_CLOCK_DIV_FRAC 0
+// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC8, Fractional part of the clock divider for communication with the wireless chip 0-255, type=bool, default=0, group=pico_cyw43_driver
+#ifndef CYW43_PIO_CLOCK_DIV_FRAC8
+#ifdef CYW43_PIO_CLOCK_DIV_FRAC
+#define CYW43_PIO_CLOCK_DIV_FRAC8 CYW43_PIO_CLOCK_DIV_FRAC
+#else
+#define CYW43_PIO_CLOCK_DIV_FRAC8 0
+#endif
 #endif
 
 #if CYW43_PIO_CLOCK_DIV_DYNAMIC
@@ -72,9 +76,14 @@ void cyw43_driver_deinit(struct async_context *context);
  * This function is only available if \ref CYW43_PIO_CLOCK_DIV_DYNAMIC is true
  *
  * \param clock_div_int Integer part of the divisor
- * \param clock_div_frac Fractional part in 1/256ths
+ * \param clock_div_frac8 Fractional part in 1/256ths
 */
-void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac);
+void cyw43_set_pio_clock_divider_int_frac8(uint16_t clock_div_int, uint8_t clock_div_frac8);
+
+// backwards compatibility
+static inline void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac8) {
+   return cyw43_set_pio_clock_divider_int_frac8(clock_div_int, clock_div_frac8);
+}
 #endif
 
 #if CYW43_PIN_WL_DYNAMIC

From f2e738f3256984d01e1e1e129184f84983a9f98d Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 11 Sep 2024 16:59:10 -0500
Subject: [PATCH 03/10] use consistent with sdk naming skeep for new
 cyw43_driver method... fix build

---
 src/rp2_common/hardware_pwm/include/hardware/pwm.h           | 4 ++--
 src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c         | 2 +-
 src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
index 684c0c1c0..57f54b39b 100644
--- a/src/rp2_common/hardware_pwm/include/hardware/pwm.h
+++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
@@ -194,7 +194,7 @@ static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t div_int
  */
 static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
     valid_params_if(HARDWARE_PWM, div >= 1 && div < 256);
-    pwm_config_set_clkdiv_int_frac8(c, (uint8_t)div, 0);
+    pwm_config_set_clkdiv_int_frac4(c, (uint8_t)div, 0);
 }
 
 /** \brief Set PWM counting mode in a PWM configuration
@@ -463,7 +463,7 @@ static inline void pwm_set_clkdiv(uint slice_num, float divider) {
     valid_params_if(HARDWARE_PWM, divider >= 1.f && divider < 256.f);
     uint8_t i = (uint8_t)divider;
     uint8_t f = (uint8_t)((divider - i) * (0x01 << 4));
-    pwm_set_clkdiv_int_frac8(slice_num, i, f);
+    pwm_set_clkdiv_int_frac4(slice_num, i, f);
 }
 
 /** \brief Set PWM output polarity
diff --git a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
index 2d827632e..eec734841 100644
--- a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
+++ b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
@@ -48,7 +48,7 @@ static_assert((CYW43_PIN_WL_DATA_OUT < 32 && CYW43_PIN_WL_DATA_IN < 32 && CYW43_
 static uint16_t cyw43_pio_clock_div_int = CYW43_PIO_CLOCK_DIV_INT;
 static uint8_t cyw43_pio_clock_div_frac8 = CYW43_PIO_CLOCK_DIV_FRAC8;
 
-void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac8) {
+void cyw43_set_pio_clkdiv_int_frac8(uint16_t clock_div_int, uint8_t clock_div_frac8) {
     cyw43_pio_clock_div_int = clock_div_int;
     cyw43_pio_clock_div_frac8 = clock_div_frac8;
 }
diff --git a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
index 6de3f1b92..29d72fee4 100644
--- a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
+++ b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
@@ -78,11 +78,11 @@ void cyw43_driver_deinit(struct async_context *context);
  * \param clock_div_int Integer part of the divisor
  * \param clock_div_frac8 Fractional part in 1/256ths
 */
-void cyw43_set_pio_clock_divider_int_frac8(uint16_t clock_div_int, uint8_t clock_div_frac8);
+void cyw43_set_pio_clkdiv_int_frac8(uint16_t clock_div_int, uint8_t clock_div_frac8);
 
 // backwards compatibility
 static inline void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac8) {
-   return cyw43_set_pio_clock_divider_int_frac8(clock_div_int, clock_div_frac8);
+    return cyw43_set_pio_clkdiv_int_frac8(clock_div_int, clock_div_frac8);
 }
 #endif
 

From 4d4964e18ebcf83b11c7c80622acc2df48f51580 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 11 Sep 2024 17:11:30 -0500
Subject: [PATCH 04/10] add missing backwards compatibility; minor var rename

---
 .../hardware_clocks/include/hardware/clocks.h         |  2 +-
 src/rp2_common/hardware_pio/include/hardware/pio.h    | 11 ++++++++---
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/rp2_common/hardware_clocks/include/hardware/clocks.h b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
index d1cee576e..6851f035d 100644
--- a/src/rp2_common/hardware_clocks/include/hardware/clocks.h
+++ b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
@@ -367,7 +367,7 @@ void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t
  * \param div_frac8 The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).
  */
 static inline void clock_gpio_init_int_frac8(uint gpio, uint src, uint32_t div_int, uint8_t div_frac8) {
-    return clock_gpio_init_int_frac16(gpio, src, div_int, div_frac8 << 8u);
+    return clock_gpio_init_int_frac16(gpio, src, div_int, (uint16_t)(div_frac8 << 8u));
 }
 
 // backwards compatibility
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index cb4d8fd77..3e30c05f2 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -485,19 +485,24 @@ static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_
     sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
 }
 
-static inline void pio_calculate_clkdiv8_from_float(float div, uint16_t *div_int, uint8_t *div_frac) {
+static inline void pio_calculate_clkdiv8_from_float(float div, uint16_t *div_int, uint8_t *div_frac8) {
     valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536);
     *div_int = (uint16_t)div;
     // not a strictly necessary check, but if this changes, then this method should
     // probably no longer be used in favor of one with a larger fraction
     static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
     if (*div_int == 0) {
-        *div_frac = 0;
+        *div_frac8 = 0;
     } else {
-        *div_frac = (uint8_t)((div - (float)*div_int) * (1u << 8u));
+        *div_frac8 = (uint8_t)((div - (float)*div_int) * (1u << 8u));
     }
 }
 
+// backwards compatibility
+static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac8) {
+    pio_calculate_clkdiv8_from_float(div, div_int, div_frac8);
+}
+
 /*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration
  *  \ingroup sm_config
  *

From e5f3ea6291d7374a39491154d8559e78bdc0b5b7 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 11 Sep 2024 17:24:05 -0500
Subject: [PATCH 05/10] standardize for the new int_frac<n> methods that the
 integer part is uint32_t for future proofing

---
 src/rp2_common/hardware_clocks/clocks.c       |  2 ++
 .../hardware_pio/include/hardware/pio.h       | 28 +++++++++++--------
 .../hardware_pwm/include/hardware/pwm.h       | 11 ++++----
 .../pico_cyw43_driver/cyw43_bus_pio_spi.c     |  4 +--
 .../include/pico/cyw43_driver.h               |  2 +-
 5 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c
index dce26ee12..af4c96943 100644
--- a/src/rp2_common/hardware_clocks/clocks.c
+++ b/src/rp2_common/hardware_clocks/clocks.c
@@ -245,6 +245,8 @@ void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t
         invalid_params_if(HARDWARE_CLOCKS, true);
     }
 
+    static_assert(CLOCKS_CLK_GPOUT0_DIV_INT_MSB - CLOCKS_CLK_GPOUT0_DIV_INT_LSB == 15, "");
+    invalid_params_if(HARDWARE_CLOCKS, div_int >> 16);
     // Set up the gpclk generator
     clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |
                                  CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS;
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index 3e30c05f2..817fee76e 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -471,9 +471,10 @@ static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool
  * \param div_frac8 Fractional part in 1/256ths
  * \sa sm_config_set_clkdiv()
  */
-static inline void sm_config_set_clkdiv_int_frac8(pio_sm_config *c, uint16_t div_int, uint8_t div_frac8) {
-    invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
+static inline void sm_config_set_clkdiv_int_frac8(pio_sm_config *c, uint32_t div_int, uint8_t div_frac8) {
     static_assert(PIO_SM0_CLKDIV_INT_MSB - PIO_SM0_CLKDIV_INT_LSB == 15, "");
+    invalid_params_if(HARDWARE_PIO, div_int >> 16);
+    invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
     static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
     c->clkdiv =
             (((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
@@ -485,7 +486,7 @@ static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_
     sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
 }
 
-static inline void pio_calculate_clkdiv8_from_float(float div, uint16_t *div_int, uint8_t *div_frac8) {
+static inline void pio_calculate_clkdiv8_from_float(float div, uint32_t *div_int, uint8_t *div_frac8) {
     valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536);
     *div_int = (uint16_t)div;
     // not a strictly necessary check, but if this changes, then this method should
@@ -499,8 +500,10 @@ static inline void pio_calculate_clkdiv8_from_float(float div, uint16_t *div_int
 }
 
 // backwards compatibility
-static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac8) {
-    pio_calculate_clkdiv8_from_float(div, div_int, div_frac8);
+static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int16, uint8_t *div_frac8) {
+    uint32_t div_int;
+    pio_calculate_clkdiv8_from_float(div, &div_int, div_frac8);
+    *div_int16 = (uint16_t) div_int;
 }
 
 /*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration
@@ -519,10 +522,10 @@ static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int,
  *  although it will depend on the use case.
  */
 static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) {
-    uint16_t div_int;
-    uint8_t div_frac;
-    pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac);
-    sm_config_set_clkdiv_int_frac8(c, div_int, div_frac);
+    uint32_t div_int;
+    uint8_t div_frac8;
+    pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac8);
+    sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
 }
 
 /*! \brief Set the wrap addresses in a state machine configuration
@@ -1660,11 +1663,12 @@ void pio_sm_drain_tx_fifo(PIO pio, uint sm);
  * \param div_int the integer part of the clock divider
  * \param div_frac8 the fractional part of the clock divider in 1/256s
  */
-static inline void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac8) {
+static inline void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint32_t div_int, uint8_t div_frac8) {
     check_pio_param(pio);
     check_sm_param(sm);
-    invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
     static_assert(PIO_SM0_CLKDIV_INT_MSB - PIO_SM0_CLKDIV_INT_LSB == 15, "");
+    invalid_params_if(HARDWARE_PIO, div_int >> 16);
+    invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
     static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
     pio->sm[sm].clkdiv =
             (((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
@@ -1686,7 +1690,7 @@ static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int
 static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
     check_pio_param(pio);
     check_sm_param(sm);
-    uint16_t div_int;
+    uint32_t div_int;
     uint8_t div_frac;
     pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac);
     pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac);
diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
index 57f54b39b..285f434d3 100644
--- a/src/rp2_common/hardware_pwm/include/hardware/pwm.h
+++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
@@ -169,9 +169,9 @@ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
  * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
  * before passing them on to the PWM counter.
  */
-static inline void pwm_config_set_clkdiv_int_frac4(pwm_config *c, uint8_t div_int, uint8_t div_frac4) {
-    valid_params_if(HARDWARE_PWM, div_int >= 1);
+static inline void pwm_config_set_clkdiv_int_frac4(pwm_config *c, uint32_t div_int, uint8_t div_frac4) {
     static_assert(PWM_CH0_DIV_INT_MSB - PWM_CH0_DIV_INT_LSB == 7, "");
+    valid_params_if(HARDWARE_PWM, div_int >= 1 && div_int < 256);
     static_assert(PWM_CH0_DIV_FRAC_MSB - PWM_CH0_DIV_FRAC_LSB == 3, "");
     valid_params_if(HARDWARE_PWM, div_frac4 < 16);
     c->div = (((uint)div_int) << PWM_CH0_DIV_INT_LSB) | (((uint)div_frac4) << PWM_CH0_DIV_FRAC_LSB);
@@ -186,15 +186,14 @@ static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t div_int
  *  \ingroup hardware_pwm
  *
  * \param c PWM configuration struct to modify
- * \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
+ * \param div_int Integer value to reduce counting rate by. Must be greater than or equal to 1 annd less than 256.
  *
  * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
  * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
  * before passing them on to the PWM counter.
  */
-static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
-    valid_params_if(HARDWARE_PWM, div >= 1 && div < 256);
-    pwm_config_set_clkdiv_int_frac4(c, (uint8_t)div, 0);
+static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint32_t div_int) {
+    pwm_config_set_clkdiv_int_frac4(c, div_int, 0);
 }
 
 /** \brief Set PWM counting mode in a PWM configuration
diff --git a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
index eec734841..8f8254854 100644
--- a/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
+++ b/src/rp2_common/pico_cyw43_driver/cyw43_bus_pio_spi.c
@@ -45,10 +45,10 @@ static_assert((CYW43_PIN_WL_DATA_OUT < 32 && CYW43_PIN_WL_DATA_IN < 32 && CYW43_
 #define cyw43_pio_clock_div_int CYW43_PIO_CLOCK_DIV_INT
 #define cyw43_pio_clock_div_frac8 CYW43_PIO_CLOCK_DIV_FRAC8
 #else
-static uint16_t cyw43_pio_clock_div_int = CYW43_PIO_CLOCK_DIV_INT;
+static uint32_t cyw43_pio_clock_div_int = CYW43_PIO_CLOCK_DIV_INT;
 static uint8_t cyw43_pio_clock_div_frac8 = CYW43_PIO_CLOCK_DIV_FRAC8;
 
-void cyw43_set_pio_clkdiv_int_frac8(uint16_t clock_div_int, uint8_t clock_div_frac8) {
+void cyw43_set_pio_clkdiv_int_frac8(uint32_t clock_div_int, uint8_t clock_div_frac8) {
     cyw43_pio_clock_div_int = clock_div_int;
     cyw43_pio_clock_div_frac8 = clock_div_frac8;
 }
diff --git a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
index 29d72fee4..1c204a989 100644
--- a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
+++ b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
@@ -78,7 +78,7 @@ void cyw43_driver_deinit(struct async_context *context);
  * \param clock_div_int Integer part of the divisor
  * \param clock_div_frac8 Fractional part in 1/256ths
 */
-void cyw43_set_pio_clkdiv_int_frac8(uint16_t clock_div_int, uint8_t clock_div_frac8);
+void cyw43_set_pio_clkdiv_int_frac8(uint32_t clock_div_int, uint8_t clock_div_frac8);
 
 // backwards compatibility
 static inline void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac8) {

From b3552b8a3616d43c4773cafb93b56216527f35ba Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 11 Sep 2024 17:36:54 -0500
Subject: [PATCH 06/10] extra extra... assertion catches bug

---
 src/rp2_common/hardware_clocks/clocks.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c
index af4c96943..56e136128 100644
--- a/src/rp2_common/hardware_clocks/clocks.c
+++ b/src/rp2_common/hardware_clocks/clocks.c
@@ -245,7 +245,9 @@ void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t
         invalid_params_if(HARDWARE_CLOCKS, true);
     }
 
+#if !PICO_RP2040 // assert currently broken on RP2040, but we know that hardware has 16 bit integer part
     static_assert(CLOCKS_CLK_GPOUT0_DIV_INT_MSB - CLOCKS_CLK_GPOUT0_DIV_INT_LSB == 15, "");
+#endif
     invalid_params_if(HARDWARE_CLOCKS, div_int >> 16);
     // Set up the gpclk generator
     clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |

From 5dd0e1bf98d662dc0fa98a40b607e8b7340689ee Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 11 Sep 2024 17:37:29 -0500
Subject: [PATCH 07/10] typo

---
 src/rp2_common/hardware_clocks/clocks.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c
index 56e136128..b3f871abe 100644
--- a/src/rp2_common/hardware_clocks/clocks.c
+++ b/src/rp2_common/hardware_clocks/clocks.c
@@ -245,7 +245,7 @@ void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t
         invalid_params_if(HARDWARE_CLOCKS, true);
     }
 
-#if !PICO_RP2040 // assert currently broken on RP2040, but we know that hardware has 16 bit integer part
+#if !PICO_RP2040 // assert currently broken on RP2040, but we know that hardware has 16-bit integer part
     static_assert(CLOCKS_CLK_GPOUT0_DIV_INT_MSB - CLOCKS_CLK_GPOUT0_DIV_INT_LSB == 15, "");
 #endif
     invalid_params_if(HARDWARE_CLOCKS, div_int >> 16);

From 128396a943b5b6622cce66d0d283b4448f2fa7cd Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 11 Nov 2024 10:54:15 -0600
Subject: [PATCH 08/10] some review fixes

---
 src/rp2_common/hardware_clocks/clocks.c                  | 5 +----
 src/rp2_common/hardware_clocks/include/hardware/clocks.h | 7 ++++---
 src/rp2_common/hardware_pio/include/hardware/pio.h       | 6 +++---
 src/rp2_common/hardware_pwm/include/hardware/pwm.h       | 2 +-
 src/rp2_common/pico_cyw43_driver/CMakeLists.txt          | 6 +++---
 5 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/src/rp2_common/hardware_clocks/clocks.c b/src/rp2_common/hardware_clocks/clocks.c
index b3f871abe..1800164f0 100644
--- a/src/rp2_common/hardware_clocks/clocks.c
+++ b/src/rp2_common/hardware_clocks/clocks.c
@@ -245,10 +245,7 @@ void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t
         invalid_params_if(HARDWARE_CLOCKS, true);
     }
 
-#if !PICO_RP2040 // assert currently broken on RP2040, but we know that hardware has 16-bit integer part
-    static_assert(CLOCKS_CLK_GPOUT0_DIV_INT_MSB - CLOCKS_CLK_GPOUT0_DIV_INT_LSB == 15, "");
-#endif
-    invalid_params_if(HARDWARE_CLOCKS, div_int >> 16);
+    invalid_params_if(HARDWARE_CLOCKS, div_int >> (CLOCKS_CLK_GPOUT0_DIV_INT_MSB - CLOCKS_CLK_GPOUT0_DIV_INT_LSB + 1));
     // Set up the gpclk generator
     clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |
                                  CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS;
diff --git a/src/rp2_common/hardware_clocks/include/hardware/clocks.h b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
index 6851f035d..f7fa8cd5c 100644
--- a/src/rp2_common/hardware_clocks/include/hardware/clocks.h
+++ b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
@@ -353,7 +353,8 @@ void clocks_enable_resus(resus_callback_t resus_callback);
  *
  * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
  * \param src  The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
- * \param div_int  The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. this is in range of 1..2^24-1.
+ * \param div_int  The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. This is in range of 1..2^24-1 on RP2040
+ *                 and 1..2^16-1 on RP2350
  * \param div_frac16 The fractional part of the value to divide the source clock by. This is in range of 0..65536 (/65536).
  */
 void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t div_frac16);
@@ -363,8 +364,8 @@ void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t
  *
  * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
  * \param src  The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
- * \param div_int  The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. this is in range of 1..2^24-1.
- * \param div_frac8 The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).
+ * \param div_int  The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. This is in range of 1..2^24-1 on RP2040
+ *                 and 1..2^16-1 on RP2350
  */
 static inline void clock_gpio_init_int_frac8(uint gpio, uint src, uint32_t div_int, uint8_t div_frac8) {
     return clock_gpio_init_int_frac16(gpio, src, div_int, (uint16_t)(div_frac8 << 8u));
diff --git a/src/rp2_common/hardware_pio/include/hardware/pio.h b/src/rp2_common/hardware_pio/include/hardware/pio.h
index 817fee76e..4bc4971e5 100644
--- a/src/rp2_common/hardware_pio/include/hardware/pio.h
+++ b/src/rp2_common/hardware_pio/include/hardware/pio.h
@@ -1691,9 +1691,9 @@ static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
     check_pio_param(pio);
     check_sm_param(sm);
     uint32_t div_int;
-    uint8_t div_frac;
-    pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac);
-    pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac);
+    uint8_t div_frac8;
+    pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac8);
+    pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac8);
 }
 
 /*! \brief Clear a state machine's TX and RX FIFOs
diff --git a/src/rp2_common/hardware_pwm/include/hardware/pwm.h b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
index 285f434d3..cce5464f7 100644
--- a/src/rp2_common/hardware_pwm/include/hardware/pwm.h
+++ b/src/rp2_common/hardware_pwm/include/hardware/pwm.h
@@ -186,7 +186,7 @@ static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t div_int
  *  \ingroup hardware_pwm
  *
  * \param c PWM configuration struct to modify
- * \param div_int Integer value to reduce counting rate by. Must be greater than or equal to 1 annd less than 256.
+ * \param div_int Integer value to reduce counting rate by. Must be greater than or equal to 1 and less than 256.
  *
  * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
  * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
diff --git a/src/rp2_common/pico_cyw43_driver/CMakeLists.txt b/src/rp2_common/pico_cyw43_driver/CMakeLists.txt
index d4a06aa77..cfc6ba1f3 100644
--- a/src/rp2_common/pico_cyw43_driver/CMakeLists.txt
+++ b/src/rp2_common/pico_cyw43_driver/CMakeLists.txt
@@ -84,9 +84,9 @@ if (EXISTS ${PICO_CYW43_DRIVER_PATH}/${CYW43_DRIVER_TEST_FILE})
         # PICO_CMAKE_CONFIG: CYW43_PIO_CLOCK_DIV_INT, integer component of pio clock divider used for cyw43 comms, type=int, default=2, group=pico_cyw43_driver
         target_compile_definitions(cyw43_driver_picow INTERFACE CYW43_PIO_CLOCK_DIV_INT=${CYW43_PIO_CLOCK_DIV_INT})
     endif()
-    if (CYW43_PIO_CLOCK_DIV_FRAC)
-        # PICO_CMAKE_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC, fractional component of pio clock divider used for cyw43 comms, type=int, default=0, group=pico_cyw43_driver
-        target_compile_definitions(cyw43_driver_picow INTERFACE CYW43_PIO_CLOCK_DIV_FRAC=${CYW43_PIO_CLOCK_DIV_FRAC})
+    if (CYW43_PIO_CLOCK_DIV_FRAC8)
+        # PICO_CMAKE_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC, fractional component of pio clock divider used for cyw43 comms in range 0-255, type=int, default=0, group=pico_cyw43_driver
+        target_compile_definitions(cyw43_driver_picow INTERFACE CYW43_PIO_CLOCK_DIV_FRAC8=${CYW43_PIO_CLOCK_DIV_FRAC8})
     endif()
     if (CYW43_PIO_CLOCK_DIV_DYNAMIC)
         # PICO_CMAKE_CONFIG: CYW43_PIO_CLOCK_DIV_DYNAMIC, flag used to enable dynamic pio clock divider API, type=bool, default=false, group=pico_cyw43_driver

From 063c7c8d92c51079fc89d2e048df0cae04931dbf Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 11 Nov 2024 12:25:41 -0600
Subject: [PATCH 09/10] more doc fixes

---
 src/rp2_common/hardware_clocks/include/hardware/clocks.h     | 2 +-
 src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/rp2_common/hardware_clocks/include/hardware/clocks.h b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
index f7fa8cd5c..ce6090a73 100644
--- a/src/rp2_common/hardware_clocks/include/hardware/clocks.h
+++ b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
@@ -355,7 +355,7 @@ void clocks_enable_resus(resus_callback_t resus_callback);
  * \param src  The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
  * \param div_int  The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. This is in range of 1..2^24-1 on RP2040
  *                 and 1..2^16-1 on RP2350
- * \param div_frac16 The fractional part of the value to divide the source clock by. This is in range of 0..65536 (/65536).
+ * \param div_frac16 The fractional part of the value to divide the source clock by. This is in range of 0..65535 (/65536).
  */
 void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t div_frac16);
 
diff --git a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
index 1c204a989..7a26b5527 100644
--- a/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
+++ b/src/rp2_common/pico_cyw43_driver/include/pico/cyw43_driver.h
@@ -48,7 +48,7 @@ void cyw43_driver_deinit(struct async_context *context);
 #define CYW43_PIO_CLOCK_DIV_DYNAMIC 0
 #endif
 
-// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_INT, Integer part of the clock divider for communication with the wireless chip, type=bool, default=2, group=pico_cyw43_driver
+// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_INT, Integer part of the clock divider for communication with the wireless chip, type=int, default=2, group=pico_cyw43_driver
 #ifndef CYW43_PIO_CLOCK_DIV_INT
 // backwards compatibility using old define
 #ifdef CYW43_PIO_CLOCK_DIV
@@ -58,7 +58,7 @@ void cyw43_driver_deinit(struct async_context *context);
 #endif
 #endif
 
-// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC8, Fractional part of the clock divider for communication with the wireless chip 0-255, type=bool, default=0, group=pico_cyw43_driver
+// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC8, Fractional part of the clock divider for communication with the wireless chip 0-255, type=int, min=0, max=255, default=0, group=pico_cyw43_driver
 #ifndef CYW43_PIO_CLOCK_DIV_FRAC8
 #ifdef CYW43_PIO_CLOCK_DIV_FRAC
 #define CYW43_PIO_CLOCK_DIV_FRAC8 CYW43_PIO_CLOCK_DIV_FRAC

From 7f77b13e4c745204347c394d2b481c722bf3ac6f Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 11 Nov 2024 12:26:49 -0600
Subject: [PATCH 10/10] more doc fixes

---
 src/rp2_common/hardware_clocks/include/hardware/clocks.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/rp2_common/hardware_clocks/include/hardware/clocks.h b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
index ce6090a73..c2a9df716 100644
--- a/src/rp2_common/hardware_clocks/include/hardware/clocks.h
+++ b/src/rp2_common/hardware_clocks/include/hardware/clocks.h
@@ -366,6 +366,7 @@ void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t
  * \param src  The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
  * \param div_int  The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. This is in range of 1..2^24-1 on RP2040
  *                 and 1..2^16-1 on RP2350
+ * \param div_frac8 The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).
  */
 static inline void clock_gpio_init_int_frac8(uint gpio, uint src, uint32_t div_int, uint8_t div_frac8) {
     return clock_gpio_init_int_frac16(gpio, src, div_int, (uint16_t)(div_frac8 << 8u));