Tywaves crashes with SRAMInterface of 0 number of ports

[rameloni]

This issue continues the conversation in #42.

Tywaves fails when generating debug information with some Chisel default constructs. This is a failing example that @bathtub-01 discovered here (#42). Firtool raises a stack dump error while using an SRAMInterface.

val io = IO(new SRAMInterface(64, UInt(4.W), 0, 0, 2))
io :<>= SRAM(64, UInt(4.W), 0, 0, 2)

[rameloni]

After running a few more experiments I noticed that the error raises when "0 ports" are used in the SRAMInterface.
In fact, the following code works fine with 0.4.2-SNAPSHOT:

val io = IO(new SRAMInterface(64, UInt(4.W), numReadPorts = 1, numWritePorts = 1, numReadwritePorts = 2))
io :<>= SRAM(64, UInt(4.W), numReadPorts = 1, numWritePorts = 1, numReadwritePorts = 2)

But the following configuration fails:

val io = IO(new SRAMInterface(64, UInt(4.W), numReadPorts = 0, numWritePorts = 1, numReadwritePorts = 2))
io :<>= SRAM(64, UInt(4.W), numReadPorts = 0, numWritePorts = 1, numReadwritePorts = 2)

[rameloni]

@bathtub-01 I fixed it. It's not available yet, I'd like to run more experiments first before creating a new release (#45). Let me know if you would need to test it soon. If it's the case I will release a tmp binary that you can use.

[bathtub-01]

@bathtub-01 I fixed it. It's not available yet, I'd like to run more experiments first before creating a new release (#45). Let me know if you would need to test it soon. If it's the case I will release a tmp binary that you can use.

Thank you so much. I think I am OK to wait for your formal release :)