From 414744337430d87963255da3410e7e8fc0481f19 Mon Sep 17 00:00:00 2001 From: Raffaele Meloni Date: Sun, 2 Jun 2024 12:36:51 +0200 Subject: [PATCH] Update version from v0.2.0 to v0.2.1 - Bump surfer-tywaves from v0.2.0-tywaves-dev-SNAPSHOT to v0.2.1-tywaves-dev-SNAPSHOT - Add Chisel fork versioning to Makefile - Add scala-cli running example --- Makefile | 5 +- build.sbt | 2 +- example/gcd.test.scala | 75 +++++++++++++++++++ src/test/scala/bar/Bar.scala | 2 +- src/test/scala/foo/FooTest.scala | 1 + .../scala/hierarchicalmodules/Blink.scala | 2 +- .../simulator/TywavesSimulatorSpec.scala | 18 +++-- 7 files changed, 93 insertions(+), 12 deletions(-) create mode 100644 example/gcd.test.scala diff --git a/Makefile b/Makefile index 4cd9ba7..8e349ea 100644 --- a/Makefile +++ b/Makefile @@ -1,10 +1,11 @@ .PHONY: all download-surfer clean TYWAVES_SURFER_REPO=https://gitlab.com/rameloni/surfer-tywaves-demo.git -TYWAVES_BRANCH=tywaves +TYWAVES_BRANCH=v0.2.1-tywaves-dev-SNAPSHOT TYWAVES_NAME=surfer-tywaves-demo CHISEL_FORK_REPO=https://github.com/rameloni/chisel.git +CHISEL_FORK_BRANCH=v6.1.0-tywaves-SNAPSHOT all: install-surfer-tywaves install-chisel-fork clean install-tywaves-backend @@ -19,7 +20,7 @@ clean: @rm -rf tmp/ install-chisel-fork: create-tmp - @cd tmp/ && git clone $(CHISEL_FORK_REPO) + @cd tmp/ && git clone $(CHISEL_FORK_REPO) && cd chisel && git checkout $(CHISEL_FORK_BRANCH) @cd tmp/chisel && sbt "unipublish / publishLocal" install-tywaves-backend: diff --git a/build.sbt b/build.sbt index d561039..740b452 100644 --- a/build.sbt +++ b/build.sbt @@ -7,7 +7,7 @@ Compile / scalaSource := baseDirectory.value / "src/main/scala" Test / scalaSource := baseDirectory.value / "src/test/scala" ThisBuild / organization := "com.github.rameloni" -ThisBuild / version := "0.2.0-SNAPSHOT" +ThisBuild / version := "0.2.1-SNAPSHOT" ThisBuild / scalaVersion := "2.13.12" enablePlugins(ScalafmtPlugin) diff --git a/example/gcd.test.scala b/example/gcd.test.scala new file mode 100644 index 0000000..f44a248 --- /dev/null +++ b/example/gcd.test.scala @@ -0,0 +1,75 @@ +//> using scala "2.13.12" +//> using dep "com.github.rameloni::tywaves-demo-backend:0.2.1-SNAPSHOT" +//> using dep "org.chipsalliance::chisel:6.3.0" +//> using plugin "org.chipsalliance:::chisel-plugin:6.3.0" +//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations" +//> using dep "org.scalatest::scalatest:3.2.18" + +// DO NOT EDIT THE ORTHER OF THESE IMPORTS (it will be solved in future versions) +import tywaves.simulator._ +import tywaves.simulator.ParametricSimulator._ +import tywaves.simulator.simulatorSettings._ +import chisel3._ + + +// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._ +//import _root_.circt.stage.ChiselStage +import org.scalatest.funspec.AnyFunSpec +import org.scalatest.matchers.should.Matchers + +/** A simple module useful for testing Chisel generation and testing */ +class GCD extends Module { + val io = IO(new Bundle { + val a = Input(UInt(32.W)) + val b = Input(UInt(32.W)) + val loadValues = Input(Bool()) + val result = Output(UInt(32.W)) + val resultIsValid = Output(Bool()) + }) + + val x = Reg(UInt(32.W)) + val y = Reg(UInt(32.W)) + + when(x > y)(x := x -% y).otherwise(y := y -% x) + + when(io.loadValues) { x := io.a; y := io.b } + + io.result := x + io.resultIsValid := y === 0.U +} + +class GCDTest extends AnyFunSpec with Matchers { + describe("ParametricSimulator") { + it("runs GCD correctly") { + simulate(new GCD(), Seq(VcdTrace, SaveWorkdirFile("aaa"))) { gcd => + gcd.io.a.poke(24.U) + gcd.io.b.poke(36.U) + gcd.io.loadValues.poke(1.B) + gcd.clock.step() + gcd.io.loadValues.poke(0.B) + gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10) + gcd.io.resultIsValid.expect(true.B) + gcd.io.result.expect(12) + } + } + } + + describe("TywavesSimulator") { + it("runs GCD correctly") { + import TywavesSimulator._ + + simulate(new GCD(), Seq(VcdTrace, WithTywavesWaveforms(true)), simName = "runs_GCD_correctly_launch_tywaves") { + gcd => + gcd.io.a.poke(24.U) + gcd.io.b.poke(36.U) + gcd.io.loadValues.poke(1.B) + gcd.clock.step() + gcd.io.loadValues.poke(0.B) + gcd.clock.stepUntil(sentinelPort = gcd.io.resultIsValid, sentinelValue = 1, maxCycles = 10) + gcd.io.resultIsValid.expect(true.B) + gcd.io.result.expect(12) + } + } + } + +} diff --git a/src/test/scala/bar/Bar.scala b/src/test/scala/bar/Bar.scala index f8e6279..49aaca8 100644 --- a/src/test/scala/bar/Bar.scala +++ b/src/test/scala/bar/Bar.scala @@ -28,7 +28,7 @@ class Bar extends Module { val cable = Wire(Bool()) // do not use reserved verilog words as val names (val wire) -> tywaves-demo does not work for them yet - cable := io.a & io.b + cable := io.a & io.b io.out := cable } diff --git a/src/test/scala/foo/FooTest.scala b/src/test/scala/foo/FooTest.scala index ecf7901..a23e628 100644 --- a/src/test/scala/foo/FooTest.scala +++ b/src/test/scala/foo/FooTest.scala @@ -6,6 +6,7 @@ import org.scalatest.flatspec.AnyFlatSpec import tywaves.simulator.simulatorSettings._ object RunFoo { + /** Run multiple times */ def apply(c: => Foo): Unit = { // Inputs and expected results diff --git a/src/test/scala/hierarchicalmodules/Blink.scala b/src/test/scala/hierarchicalmodules/Blink.scala index 45c8437..12430a9 100644 --- a/src/test/scala/hierarchicalmodules/Blink.scala +++ b/src/test/scala/hierarchicalmodules/Blink.scala @@ -7,7 +7,7 @@ class Blink(period: Int) extends Module { assert(period > 0, "limit must be greater than 0") val io = IO(new Bundle { val enable: Bool = Input(Bool()) - val led : Bool = Output(Bool()) + val led: Bool = Output(Bool()) }) val cnt: Counter = Counter(period) diff --git a/src/test/scala/tywaves/simulator/TywavesSimulatorSpec.scala b/src/test/scala/tywaves/simulator/TywavesSimulatorSpec.scala index 95dc7b1..b41ddfb 100644 --- a/src/test/scala/tywaves/simulator/TywavesSimulatorSpec.scala +++ b/src/test/scala/tywaves/simulator/TywavesSimulatorSpec.scala @@ -26,8 +26,9 @@ class TywavesSimulatorSpec extends AnyFunSpec with Matchers { resetBeforeEachRun() it("runs GCD with waveform generation") { - simulate(new GCD(), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_gcd_with_waveform_generation") { gcd => - gcdTb(gcd) + simulate(new GCD(), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_gcd_with_waveform_generation") { + gcd => + gcdTb(gcd) } assert(Files.exists(Paths.get("test_run_dir/GCD/TywavesSimulator/runs_gcd_with_waveform_generation/trace.vcd"))) @@ -39,7 +40,11 @@ class TywavesSimulatorSpec extends AnyFunSpec with Matchers { } it("runs GCD with waveform generation and custom name trace") { - simulate(new GCD(), Seq(VcdTrace, NameTrace("gcdTest"), WithTywavesWaveforms(false)), simName = "runs_gcd_with_waveform_generation") { gcd => + simulate( + new GCD(), + Seq(VcdTrace, NameTrace("gcdTest"), WithTywavesWaveforms(false)), + simName = "runs_gcd_with_waveform_generation", + ) { gcd => gcdTb(gcd) } @@ -52,12 +57,11 @@ class TywavesSimulatorSpec extends AnyFunSpec with Matchers { } it("raises an exception when Tywaves is used without VcdTrace") { - intercept[Exception] { - simulate(new GCD(), Seq(WithTywavesWaveforms(false)))(_ => gcdTb _) - } + intercept[Exception] { + simulate(new GCD(), Seq(WithTywavesWaveforms(false)))(_ => gcdTb _) + } } - } describe("Tywaves with ParametricSimulator Functionalities") {