diff --git a/Makefile b/Makefile
index 8004aab..b8f9032 100644
--- a/Makefile
+++ b/Makefile
@@ -14,7 +14,7 @@ CHISEL_FORK_TAG=v6.4.3-tywaves-SNAPSHOT
 
 # Circt (firtool) information
 CIRCT_FIRTOOL_ZIP_NAME=firtool-bin-linux-x64.tar.gz
-CIRCT_FORK_VERSION=0.1.4
+CIRCT_FORK_VERSION=0.1.5
 CIRCT_FORK_TAG=v${CIRCT_FORK_VERSION}-tywaves-SNAPSHOT
 CIRCT_FORK_FIRTOOL_ZIP_LINK=https://github.com/rameloni/circt/releases/download/${CIRCT_FORK_TAG}/${CIRCT_FIRTOOL_ZIP_NAME}
 CIRCT_FIRTOOL_NAME=firtool-type-dbg-info-${CIRCT_FORK_VERSION}
diff --git a/README.md b/README.md
index 2eea2d7..20dde30 100644
--- a/README.md
+++ b/README.md
@@ -268,7 +268,8 @@ Use the new name of the library in your sbt dependencies: `com.github.rameloni::
 > **IMPORTANT NOTE**: Always use the latest version of Tywaves
 
 | Release                                                                                        | Chisel fork version (from `rameloni/chisel`)                                                       | Firtool fork version (from `rameloni/circt`)                                     | Tywaves-rs version                                                            | Surfer-tywaves version                                                                                                |
-| :--------------------------------------------------------------------------------------------- | :------------------------------------------------------------------------------------------------- | :------------------------------------------------------------------------------- | :---------------------------------------------------------------------------- | :-------------------------------------------------------------------------------------------------------------------- |
+|:-----------------------------------------------------------------------------------------------| :------------------------------------------------------------------------------------------------- |:---------------------------------------------------------------------------------| :---------------------------------------------------------------------------- | :-------------------------------------------------------------------------------------------------------------------- |
+| [0.4.2-SNAPSHOT](https://github.com/rameloni/tywaves-chisel-demo/releases/tag/v0.4.2-SNAPSHOT) | [v6.4.3-tywaves-SNAPSHOT](https://github.com/rameloni/chisel/releases/tag/v6.4.3-tywaves-SNAPSHOT) | [v0.1.5](https://github.com/rameloni/circt/releases/tag/v0.1.5-tywaves-SNAPSHOT) | [v0.1.4](https://github.com/rameloni/tywaves-rs/releases/tag/v0.1.4-SNAPSHOT) | [v0.3.2-tywaves-dev-SNAPSHOT](https://gitlab.com/rameloni/surfer-tywaves-demo/-/releases/v0.3.2-tywaves-SNAPSHOT)     |
 | [0.4.1-SNAPSHOT](https://github.com/rameloni/tywaves-chisel-demo/releases/tag/v0.4.1-SNAPSHOT) | [v6.4.3-tywaves-SNAPSHOT](https://github.com/rameloni/chisel/releases/tag/v6.4.3-tywaves-SNAPSHOT) | [v0.1.4](https://github.com/rameloni/circt/releases/tag/v0.1.4-tywaves-SNAPSHOT) | [v0.1.4](https://github.com/rameloni/tywaves-rs/releases/tag/v0.1.4-SNAPSHOT) | [v0.3.2-tywaves-dev-SNAPSHOT](https://gitlab.com/rameloni/surfer-tywaves-demo/-/releases/v0.3.2-tywaves-SNAPSHOT)     |
 | [0.4.0-SNAPSHOT](https://github.com/rameloni/tywaves-chisel-demo/releases/tag/v0.4.0-SNAPSHOT) | [v6.4.3-tywaves-SNAPSHOT](https://github.com/rameloni/chisel/releases/tag/v6.4.3-tywaves-SNAPSHOT) | [v0.1.3](https://github.com/rameloni/circt/releases/tag/v0.1.3-tywaves-SNAPSHOT) | [v0.1.4](https://github.com/rameloni/tywaves-rs/releases/tag/v0.1.4-SNAPSHOT) | [v0.3.2-tywaves-dev-SNAPSHOT](https://gitlab.com/rameloni/surfer-tywaves-demo/-/releases/v0.3.2-tywaves-SNAPSHOT)     |
 | [0.3.0-SNAPSHOT](https://github.com/rameloni/tywaves-chisel-demo/releases/tag/v0.3.0-SNAPSHOT) | [v6.4.2-tywaves-SNAPSHOT](https://github.com/rameloni/chisel/releases/tag/v6.4.2-tywaves-SNAPSHOT) | [v0.1.1](https://github.com/rameloni/circt/releases/tag/v0.1.1-tywaves-SNAPSHOT) | [v0.1.1](https://github.com/rameloni/tywaves-rs/releases/tag/v0.1.1-SNAPSHOT) | [v0.3.0-tywaves-dev-SNAPSHOT](https://gitlab.com/rameloni/surfer-tywaves-demo/-/releases/v0.3.0-tywaves-dev-SNAPSHOT) |
diff --git a/build.sbt b/build.sbt
index 41de084..d294310 100644
--- a/build.sbt
+++ b/build.sbt
@@ -2,7 +2,7 @@ val chiselVersion    = "6.4.3-tywaves-SNAPSHOT" // Local version of chisel
 val scalatestVersion = "3.2.16"
 val circeVersion     = "0.14.6"
 
-val firtoolVersion  = "0.1.4"
+val firtoolVersion  = "0.1.5"
 val firtoolFullName = "firtool-type-dbg-info-" ++ firtoolVersion
 
 val surferTywavesVersion  = "0.3.2"
@@ -13,7 +13,7 @@ Compile / scalaSource := baseDirectory.value / "src/main/scala"
 Test / scalaSource := baseDirectory.value / "src/test/scala"
 
 ThisBuild / organization := "com.github.rameloni"
-ThisBuild / version      := "0.4.1-SNAPSHOT"
+ThisBuild / version      := "0.4.2-SNAPSHOT"
 ThisBuild / scalaVersion := "2.13.14"
 
 enablePlugins(ScalafmtPlugin)
diff --git a/example/detect2ones.test.scala b/example/detect2ones.test.scala
index 475d205..0ba1137 100644
--- a/example/detect2ones.test.scala
+++ b/example/detect2ones.test.scala
@@ -1,5 +1,5 @@
 //> using scala "2.13.14"
-//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.0-SNAPSHOT"
+//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT"
 //> using dep "org.chipsalliance::chisel:6.4.0"
 //> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
 //> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
diff --git a/example/gcd.test.scala b/example/gcd.test.scala
index c583bc9..29d27e0 100644
--- a/example/gcd.test.scala
+++ b/example/gcd.test.scala
@@ -1,5 +1,5 @@
 //> using scala "2.13.14"
-//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.0-SNAPSHOT"
+//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT"
 //> using dep "org.chipsalliance::chisel:6.4.0"
 //> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
 //> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
diff --git a/example/myfsm.test.scala b/example/myfsm.test.scala
index 7368b28..a3f277b 100644
--- a/example/myfsm.test.scala
+++ b/example/myfsm.test.scala
@@ -1,5 +1,5 @@
 //> using scala "2.13.14"
-//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.0-SNAPSHOT"
+//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT"
 //> using dep "org.chipsalliance::chisel:6.4.0"
 //> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
 //> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
diff --git a/example/tydi-example-meaningfulnames.test.scala b/example/tydi-example-meaningfulnames.test.scala
index ee1eb90..67acd37 100644
--- a/example/tydi-example-meaningfulnames.test.scala
+++ b/example/tydi-example-meaningfulnames.test.scala
@@ -1,5 +1,5 @@
 //> using scala "2.13.14"
-//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.0-SNAPSHOT"
+//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT"
 //> using dep "nl.tudelft::tydi-chisel::0.1.0"
 //> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
 //> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
diff --git a/example/tydi-example.test.scala b/example/tydi-example.test.scala
index ed18fcf..e506358 100644
--- a/example/tydi-example.test.scala
+++ b/example/tydi-example.test.scala
@@ -1,5 +1,5 @@
 //> using scala "2.13.14"
-//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.0-SNAPSHOT"
+//> using dep "com.github.rameloni::tywaves-chisel-api:0.4.2-SNAPSHOT"
 //> using dep "nl.tudelft::tydi-chisel::0.1.0"
 //> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
 //> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
diff --git a/src/test/scala/memories/BlockMem.scala b/src/test/scala/memories/BlockMem.scala
new file mode 100644
index 0000000..0c24076
--- /dev/null
+++ b/src/test/scala/memories/BlockMem.scala
@@ -0,0 +1,26 @@
+package memories
+
+import chisel3._
+import chisel3.util.log2Ceil
+
+
+class MemIOBundle[T <: Data](depth: Int, t: T) extends Bundle {
+  val rdAddr = Input(UInt(log2Ceil(depth).W))
+  val rdData = Output(t)
+  val wrEna  = Input(Bool())
+  val wrData = Input(t)
+  val wrAddr = Input(UInt(log2Ceil(depth).W))
+}
+
+/** A simple  module for testing memories in Tywaves */
+class BlockMem[T <: Data](depth: Int, t: T) extends Module {
+  val io = IO(new MemIOBundle(depth, t))
+
+  val mem = SyncReadMem(depth, t)
+  io.rdData := mem.read(io.rdAddr)
+
+  when(io.wrEna) {
+    mem.write(io.wrAddr, io.wrData)
+  }
+}
+
diff --git a/src/test/scala/memories/BlockMemTest.scala b/src/test/scala/memories/BlockMemTest.scala
new file mode 100644
index 0000000..b08986f
--- /dev/null
+++ b/src/test/scala/memories/BlockMemTest.scala
@@ -0,0 +1,84 @@
+package memories
+
+import org.scalatest.funspec.AnyFunSpec
+import org.scalatest.matchers.must.Matchers
+
+import tywaves.simulator._
+import tywaves.simulator.simulatorSettings._
+import chisel3._
+
+class BlockMemTest extends AnyFunSpec with Matchers {
+  describe("TywavesSimulator") {
+    import TywavesSimulator._
+
+    it("runs BlockMem of UInt8") {
+      val t = UInt(8.W)
+      simulate(new BlockMem(15, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_uint8")(dut =>
+        dut.clock.step(2)
+      )
+    }
+
+    it("runs BlockMem of Bundle") {
+
+      class ComplexElement extends Bundle {
+        val a = new Bundle {
+          val subA1 = UInt(8.W)
+          val subA2 = SInt(8.W)
+        }
+        val payload = Bits(8.W)
+      }
+
+      val t = new ComplexElement
+      simulate(
+        new BlockMem(4, t),
+        Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile("workdir")),
+        simName = "runs_mem_bundle",
+      )(dut => dut.clock.step(2))
+    }
+
+    it("runs BlockMem of Vec") {
+      val t = Vec(4, UInt(8.W))
+      simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_vec")(dut =>
+        dut.clock.step(2)
+      )
+    }
+
+    it("runs BlockMem of Enum") {
+      object SelType extends ChiselEnum { val A, B, C = Value }
+      val t = SelType()
+      simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum")(dut =>
+        dut.clock.step(2)
+      )
+    }
+
+    it("runs BlockMem of Enum in Bundle") {
+      object SelType extends ChiselEnum { val A, B, C = Value }
+      class ComplexElement extends Bundle {
+        val sel     = SelType()
+        val payload = Bits(8.W)
+      }
+
+      val t = new ComplexElement
+      simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_bundle")(dut =>
+        dut.clock.step(2)
+      )
+    }
+
+    it("runs BlockMem of Enum in Vec") {
+      object SelType extends ChiselEnum { val A, B, C = Value }
+      val t = Vec(4, SelType())
+      simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_vec")(dut =>
+        dut.clock.step(2)
+      )
+    }
+
+    it("runs BlockMem of Enum in 2D-Vec") {
+      object SelType extends ChiselEnum { val A, B, C = Value }
+      val t = Vec(4, Vec(2, SelType()))
+      simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_2d_vec")(dut =>
+        dut.clock.step(2)
+      )
+    }
+
+  }
+}