Regarding Runtime in ReGDS paper

[natrajbhargav]

Dear Rachel, I use freePDK Skywater 130nm for ISCAS'85 benchmark circuits. I still need to get the less runtime you mentioned in the paper. My point is that you have much less runtime. Can you tell me a hint, please,

suppose one design has 70k transistors. You applied your vf2 subgraph isomorphism algorithm; obviously, it will take more runtime to convert logic gates. Inside the vf2 algorithm, if there are any optimization techniques you used, please suggest how to reduce the runtime. I need your suggestions, madam. Please tell me. I'm looking forward to hearing back from you.

In my case, I applied my proposed customized C++ Subgraph isomorphism algorithm. It takes more time than your runtime, as mentioned in your paper. I am trying to understand what I will do. Please show me the path, madam.