Regarding runtime for c499 benchmark ckt

[natrajbhargav]

Dear Rachel,

i am applying the c499_flat.sp netlist into your github code: it taking 30 seconds, and in your ReGDS paper its given 0.03s.

How is it possible? Please tell me ...
c499_flat.txt

(base) natraj@Natraj:~/Desktop/ReGDS-Logic-Gate-Extraction/bin$ ./LGE --lib=0 --sp=../examples/c499_flat.sp
[INF 2024-08-28 21:41:12 0.00 sec] ----- Command-Line Options -----
[INF 2024-08-28 21:41:12 0.00 sec] Parsing file ../examples/c499_flat.sp
[INF 2024-08-28 21:41:12 0.12 sec] Completed parsing file ../examples/c499_flat.sp
[INF 2024-08-28 21:41:12 0.12 sec] Analysis of SPICE netlist completed
[INF 2024-08-28 21:41:12 0.12 sec] Port propagation completed
[INF 2024-08-28 21:41:43 30.84 sec] Completed hierarchical logic gate extraction
[INF 2024-08-28 21:41:43 30.84 sec] Completed writing verilog file