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Timing-Driven FPGA Placer

The timing-driven placer runs on both CPU and GPU.

Sample FPGA01 Benchmark

FPGA01 design from the ISPD'2016 benchmarks is included with the below additional files to enable interface with Vivado:

  • design.edf: This file contains design information, which can be generated by loading design.dcp to Vivado using the 'write_edif' command.
  • constr_FPGA01.xdc: This file contains the timing constraints for the design. The value is set to critical path delay (CPD) + worst slack (WS) obtained by Vivado in Table II of the FCCM'24 paper.

Running the timing-driven placer

Choose the corresponding input .json file for timing-driven placement. Go to the root directory and run with the JSON configuration file.

python dreamplacefpga/Placer.py test/timing_FPGA01.json

Note: If your machine does not have an NVIDIA GPU, set the 'gpu' flag in the JSON configuration file to '0' to run on the CPU.

JSON Configurations

The options corresponding to timing-driven placement in the JSON file are listed below. For the complete list of available options, please refer to paramsFPGA.json.

JSON Parameter Default Description
timing_driven_flag 0 enable timing-driven placement
inflation_ratio 1.0 used for better routability when exporting to Vivado router
timing_file_dir required timing files for the data-driven timing model
enableTimingPreclustering 0 enable timing-driven preclustering in packing-legalization
timing_constraint required timing constraint in ps for our placer
write_tcl_flag 0 enable writing out the placement solution as Vivado Tcl script
write_io_placement_flag 0 enable writing out fixed io placements as Vivado Tcl script

Timing Constraints

A stricter timing constraint is employed in the input .json file for the ISPD'2016 benchmarks than in the constraint .xdc file used by Vivado.

Benchmark Timing Constraint (ps)
FPGA01 3600
FPGA02 4100
FPGA03 8200
FPGA04 11200
FPGA05 19400
FPGA06 15300
FPGA07 25500
FPGA08 8800
FPGA09 23200
FPGA10 20300
FPGA11 18500
FPGA12 18700

Running Vivado

Baseline Place-and-Route Run in Vivado

While a patch was available for Vivado2015.4 that allowed placement solution to be read in as a .pl file, newer Vivado versions do not support it. To run the ISPD'2016 benchmarks on newer Vivado versions, the IO locations must be fixed as specified in the design.pl file.

Set the write_io_placement_flag in .json to generate place_io_cells.tcl that can be loaded to Vivado. To run placement and routing in Vivado, follow the below steps:

read_edif benchmarks/sample_ispd2016_benchmarks/FPGA01/design.edf
link_design -part xcvu095-ffva2104-2-e
read_xdc benchmarks/sample_ispd2016_benchmarks/FPGA01/constr_FPGA01.xdc
source place_io_cells.tcl
place_design
route_design -directive AggressiveExplore
report_timing_summary
report_route_status

Interface with Vivado

To interface our placement solution with Vivado, we generate a TCL file with locations of all the design instances by setting the write_tcl_flag in the .json to generate place_cells.tcl.

In our experiments, we employed Vivado2022.1 to load our placement solution, followed by routing and post-route timing evaluation by Vivado using the below steps:

read_edif benchmarks/sample_ispd2016_benchmarks/FPGA01/design.edf
link_design -part xcvu095-ffva2104-2-e
read_xdc benchmarks/sample_ispd2016_benchmarks/FPGA01/constr_FPGA01.xdc
source place_cells.tcl
route_design -directive AggressiveExplore
report_timing_summary
report_route_status