diff --git a/src/fpga/tc_clk_xilinx.sv b/src/fpga/tc_clk_xilinx.sv
index e45885b..7a84249 100644
--- a/src/fpga/tc_clk_xilinx.sv
+++ b/src/fpga/tc_clk_xilinx.sv
@@ -57,19 +57,28 @@ module tc_clk_inverter (
 
 endmodule
 
-module tc_clk_mux2 (
+module tc_clk_mux2 #(
+  /// Using BUFGMUX on FPGA can allocate limited clock ressources
+  /// to non clock signals. It can be disabled with
+  /// IS_FUNCTIONAL = 0
+  parameter bit IS_FUNCTIONAL = 1'b0
+)(
   input  logic clk0_i,
   input  logic clk1_i,
   input  logic clk_sel_i,
   output logic clk_o
 );
 
-  BUFGMUX i_BUFGMUX (
-    .S  ( clk_sel_i ),
-    .I0 ( clk0_i    ),
-    .I1 ( clk1_i    ),
-    .O  ( clk_o     )
-  );
+  if (IS_FUNCTIONAL) begin
+    BUFGMUX i_BUFGMUX (
+      .S  ( clk_sel_i ),
+      .I0 ( clk0_i    ),
+      .I1 ( clk1_i    ),
+      .O  ( clk_o     )
+    );
+  end else begin
+    assign clk_o = clk_sel_i ? clk1_i : clk0_i;
+  end
 
 endmodule