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Likely RTL / post-synthesis mismatch in Vregfile #5

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FrancescoConti opened this issue Nov 20, 2023 · 1 comment
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Likely RTL / post-synthesis mismatch in Vregfile #5

FrancescoConti opened this issue Nov 20, 2023 · 1 comment

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@FrancescoConti
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FrancescoConti commented Nov 20, 2023 •
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This always_latch

spatz/hw/ip/spatz/src/vregfile.sv

Line 101 in 31d651d

always_latch begin

introduces a very likely simulation-to-synthesis mismatch.
The vregfile is resetted in RTL simulation, but the latches are (correctly) not resetted when synthesized.
In my opinion, the resetting should be removed also from the simulation.
@suehtamacv suehtamacv mentioned this issue Dec 5, 2023
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Solved with #6, thanks for reporting the issue!

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@suehtamacv @FrancescoConti