From 09fede72df45d327542dc6055e0b30ba942697c8 Mon Sep 17 00:00:00 2001 From: Thierry Dubochet Date: Tue, 14 May 2024 09:30:48 +0200 Subject: [PATCH 1/6] Eliminated Non-Resettable FFs. --- FindNonResettableFFs.py | 27 ++++++++++++ hw/reqrsp_interface/src/axi_to_reqrsp.sv | 12 ++--- hw/snitch/src/snitch.sv | 13 +++--- hw/snitch/src/snitch_l0_tlb.sv | 8 ++-- hw/snitch/src/snitch_regfile_ff.sv | 19 +++++--- hw/snitch/src/snitch_regfile_fpga.sv | 11 ++--- hw/snitch/src/snitch_regfile_latch.sv | 4 +- hw/snitch_cluster/src/snitch_amo_shim.sv | 10 ++--- hw/snitch_cluster/src/snitch_clkdiv2.sv | 7 ++- hw/snitch_cluster/src/snitch_cluster.sv | 5 ++- hw/snitch_cluster/src/snitch_fp_ss.sv | 1 + hw/snitch_cluster/src/snitch_sequencer.sv | 3 +- hw/snitch_cluster/src/snitch_shared_muldiv.sv | 44 ++++++------------- hw/snitch_ipu/src/snitch_int_ss.sv | 3 +- hw/snitch_ssr/src/snitch_ssr.sv | 2 +- hw/snitch_ssr/src/snitch_ssr_addr_gen.sv | 36 +++++++-------- hw/snitch_ssr/src/snitch_ssr_indirector.sv | 10 ++--- hw/snitch_vm/src/snitch_ptw.sv | 8 ++-- 18 files changed, 124 insertions(+), 99 deletions(-) create mode 100644 FindNonResettableFFs.py diff --git a/FindNonResettableFFs.py b/FindNonResettableFFs.py new file mode 100644 index 000000000..ae6e820f0 --- /dev/null +++ b/FindNonResettableFFs.py @@ -0,0 +1,27 @@ +import os + +text = 'amo_op_e' +path = '/scratch/bsc24f10/Documents/MonocerosGithubRepo/monoceros/snitch_cluster/hw' + +def searchText(path): + + os.chdir(path) + files = os.listdir(path) + #print(files) + + for file_name in files: + abs_path = os.path.join(path, file_name) + #print('is '+ abs_path + ' directory? : ') + if os.path.isdir(abs_path): + #print("Directory found: " + abs_path) + searchText(abs_path) + + if os.path.isfile(abs_path): + #print("File found: " + abs_path) + with open(abs_path, 'r') as f: + if text in f.read(): + final_path = os.path.abspath(file_name) + print(text + " word found in this path " + final_path) + pass +searchText(path) +print("DONE") diff --git a/hw/reqrsp_interface/src/axi_to_reqrsp.sv b/hw/reqrsp_interface/src/axi_to_reqrsp.sv index 82c6deeaf..4f03adc78 100644 --- a/hw/reqrsp_interface/src/axi_to_reqrsp.sv +++ b/hw/reqrsp_interface/src/axi_to_reqrsp.sv @@ -371,12 +371,12 @@ module axi_to_reqrsp #( }; // Registers - `FFARN(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni) - `FFARN(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni) - `FFARN(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni) - `FFARN(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni) - `FFARN(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni) - `FFARN(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni) + `FF(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni) + `FF(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni) + `FF(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni) + `FF(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni) + `FF(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni) + `FF(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni) // Assertions // Make sure that write is never set for AMOs. diff --git a/hw/snitch/src/snitch.sv b/hw/snitch/src/snitch.sv index fb46914e8..29fd2b2f7 100644 --- a/hw/snitch/src/snitch.sv +++ b/hw/snitch/src/snitch.sv @@ -282,10 +282,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( logic [31:0] dscratch_d, dscratch_q; logic debug_d, debug_q; - `FFNR(scratch_q, scratch_d, clk_i) - `FFNR(tvec_q, tvec_d, clk_i) - `FFNR(epc_q, epc_d, clk_i) - `FFNR(satp_q, satp_d, clk_i) + `FFAR(scratch_q, scratch_d, '0, clk_i, rst_i) + `FFAR(tvec_q, tvec_d, '0, clk_i, rst_i) + `FFAR(epc_q, epc_d, '0, clk_i, rst_i) + `FFAR(satp_q, satp_d, '0, clk_i, rst_i) `FFAR(cause_q, cause_d, '0, clk_i, rst_i) `FFAR(cause_irq_q, cause_irq_d, '0, clk_i, rst_i) `FFAR(priv_lvl_q, priv_lvl_d, snitch_pkg::PrivLvlM, clk_i, rst_i) @@ -305,8 +305,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( if (DebugSupport) begin : gen_debug `FFAR(dcsr_q, dcsr_d, '0, clk_i, rst_i) - `FFNR(dpc_q, dpc_d, clk_i) - `FFNR(dscratch_q, dscratch_d, clk_i) + `FFAR(dpc_q, dpc_d, '0, clk_i, rst_i) + `FFAR(dscratch_q, dscratch_d, '0, clk_i, rst_i) `FFAR(debug_q, debug_d, '0, clk_i, rst_i) // Debug mode end else begin : gen_no_debug assign dcsr_q = '0; @@ -2630,6 +2630,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( .ADDR_WIDTH ( RegWidth ) ) i_snitch_regfile ( .clk_i, + .rst_ni ( ~rst_i ), .raddr_i ( gpr_raddr ), .rdata_o ( gpr_rdata ), .waddr_i ( gpr_waddr ), diff --git a/hw/snitch/src/snitch_l0_tlb.sv b/hw/snitch/src/snitch_l0_tlb.sv index 48ab01545..373cd9399 100644 --- a/hw/snitch/src/snitch_l0_tlb.sv +++ b/hw/snitch/src/snitch_l0_tlb.sv @@ -2,9 +2,11 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 -`include "common_cells/registers.svh" // Author: Florian Zaruba +`include "common_cells/registers.svh" +`include "common_cells/assertions.svh" + // MMU w/ L0 TLB module snitch_l0_tlb import snitch_pkg::*; #( parameter int unsigned NrEntries = 1, @@ -66,8 +68,8 @@ module snitch_l0_tlb import snitch_pkg::*; #( l0_pte_t pte; `FFAR(tag_valid_q, tag_valid_d, '0, clk_i, rst_i) - `FFNR(tag_q, tag_d, clk_i) - `FFNR(pte_q, pte_d, clk_i) + `FFAR(tag_q, tag_d, '0, clk_i, rst_i) + `FFAR(pte_q, pte_d, '0, clk_i, rst_i) logic [NrEntries-1:0] hit; logic miss_d, miss_q; // we got a miss diff --git a/hw/snitch/src/snitch_regfile_ff.sv b/hw/snitch/src/snitch_regfile_ff.sv index cceecb246..601ef991a 100644 --- a/hw/snitch/src/snitch_regfile_ff.sv +++ b/hw/snitch/src/snitch_regfile_ff.sv @@ -14,6 +14,7 @@ module snitch_regfile #( ) ( // clock and reset input logic clk_i, + input logic rst_ni, // read port input logic [NR_READ_PORTS-1:0][ADDR_WIDTH-1:0] raddr_i, output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, @@ -38,19 +39,23 @@ module snitch_regfile #( end end - // loop from 1 to NumWords-1 as R0 is nil - always_ff @(posedge clk_i) begin : register_write_behavioral - for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin - for (int unsigned i = 0; i < NumWords; i++) begin + // loop from 1 to NumWords-1 as R0 is nil + always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral + for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin + for (int unsigned i = 0; i < NumWords; i++) begin + if (~rst_ni) begin + mem[i] <= '0; + end else begin if (we_dec[j][i]) begin mem[i] <= wdata_i[j]; end end - if (ZERO_REG_ZERO) begin - mem[0] <= '0; - end + end + if (ZERO_REG_ZERO) begin + mem[0] <= '0; end end + end for (genvar i = 0; i < NR_READ_PORTS; i++) begin : gen_read_port assign rdata_o[i] = mem[raddr_i[i]]; diff --git a/hw/snitch/src/snitch_regfile_fpga.sv b/hw/snitch/src/snitch_regfile_fpga.sv index d24368632..bee0569b5 100644 --- a/hw/snitch/src/snitch_regfile_fpga.sv +++ b/hw/snitch/src/snitch_regfile_fpga.sv @@ -30,6 +30,7 @@ module snitch_regfile #( )( // clock and reset input logic clk_i, + input logic rst_ni, // read port input logic [NR_READ_PORTS-1:0][4:0] raddr_i, output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, @@ -83,18 +84,12 @@ module snitch_regfile #( end // block selector flops - always_ff @(posedge clk_i) begin - mem_block_sel_q <= mem_block_sel; - end + `FF(mem_block_sel_q, mem_block_sel, '0, clk_i, rst_ni) // distributed RAM blocks logic [NR_READ_PORTS-1:0] [DATA_WIDTH-1:0] mem_read [NR_WRITE_PORTS]; for (genvar j=0; j // Author: Fabian Schuiki +`include "common_cells/registers.svh" +`include "common_cells/assertions.svh" + (* no_ungroup *) (* no_boundary_optimization *) module snitch_clkdiv2 ( input logic clk_i, + input logic rst_ni, input logic test_mode_i, input logic bypass_i, output logic clk_o @@ -53,7 +57,8 @@ module snitch_clkdiv2 ( assign clk_div_del = clk_div; `endif - always_ff @(posedge clk_i) clk_div <= ~clk_div; + `FF(clk_div, ~clk_div, '0, clk_i, rst_ni) + assign clk_o = (test_mode_i | bypass_i) ? clk_i : clk_div_del; endmodule diff --git a/hw/snitch_cluster/src/snitch_cluster.sv b/hw/snitch_cluster/src/snitch_cluster.sv index 4e4c4b00c..30d72b9e1 100644 --- a/hw/snitch_cluster/src/snitch_cluster.sv +++ b/hw/snitch_cluster/src/snitch_cluster.sv @@ -824,6 +824,7 @@ module snitch_cluster if (IsoCrossing) begin : gen_clk_divider snitch_clkdiv2 i_snitch_clkdiv2 ( .clk_i, + .rst_ni (rst_ni), .test_mode_i (1'b0), .bypass_i ( clk_d2_bypass_i ), .clk_o (clk_d2) @@ -1280,8 +1281,8 @@ module snitch_cluster // -------------------- logic [NrTCDMPortsCores-1:0] flat_acc, flat_con; for (genvar i = 0; i < NrTCDMPortsCores; i++) begin : gen_event_counter - `FFARN(flat_acc[i], tcdm_req[i].q_valid, '0, clk_i, rst_ni) - `FFARN(flat_con[i], tcdm_req[i].q_valid & ~tcdm_rsp[i].q_ready, '0, clk_i, rst_ni) + `FF(flat_acc[i], tcdm_req[i].q_valid, '0, clk_i, rst_ni) + `FF(flat_con[i], tcdm_req[i].q_valid & ~tcdm_rsp[i].q_ready, '0, clk_i, rst_ni) end popcount #( diff --git a/hw/snitch_cluster/src/snitch_fp_ss.sv b/hw/snitch_cluster/src/snitch_fp_ss.sv index 1df5b0793..d2e51e189 100644 --- a/hw/snitch_cluster/src/snitch_fp_ss.sv +++ b/hw/snitch_cluster/src/snitch_fp_ss.sv @@ -2420,6 +2420,7 @@ module snitch_fp_ss import snitch_pkg::*; #( .ADDR_WIDTH ( 5 ) ) i_ff_regfile ( .clk_i, + .rst_ni ( ~rst_i ), .raddr_i ( fpr_raddr ), .rdata_o ( fpr_rdata ), .waddr_i ( fpr_waddr ), diff --git a/hw/snitch_cluster/src/snitch_sequencer.sv b/hw/snitch_cluster/src/snitch_sequencer.sv index f3a3d53ff..a36010290 100644 --- a/hw/snitch_cluster/src/snitch_sequencer.sv +++ b/hw/snitch_cluster/src/snitch_sequencer.sv @@ -43,6 +43,7 @@ module snitch_sequencer import snitch_pkg::*; #( input logic streamctl_valid_i, output logic streamctl_ready_o ); + localparam int RptBits = 16; typedef struct packed { @@ -104,7 +105,7 @@ module snitch_sequencer import snitch_pkg::*; #( rb_empty = (rb_rd_pointer ^ rb_wr_pointer) == '0; end - `FFNR(mem_q, mem_d, clk_i) + `FFAR(mem_q, mem_d, '0, clk_i, rst_i) /// Compute ringbuffer addresses. logic [DepthBits:0] rd_pointer_d, rd_pointer_q; diff --git a/hw/snitch_cluster/src/snitch_shared_muldiv.sv b/hw/snitch_cluster/src/snitch_shared_muldiv.sv index 228b312fb..fd7c10b2a 100644 --- a/hw/snitch_cluster/src/snitch_shared_muldiv.sv +++ b/hw/snitch_cluster/src/snitch_shared_muldiv.sv @@ -196,9 +196,9 @@ module snitch_shared_muldiv_multiplier #( end `FF(valid_q, valid_d, '0) // Pipe-line registers - `FFLNR(id_q, id_i, (valid_i & ready_o), clk_i) - `FFLNR(result_q, result_d, (valid_i & ready_o), clk_i) - `FFLNR(select_upper_q, select_upper_d, (valid_i & ready_o), clk_i) + `FFL(id_q, id_i, (valid_i & ready_o), '0, clk_i, rst_ni) + `FFL(result_q, result_d, (valid_i & ready_o), '0, clk_i, rst_ni) + `FFL(select_upper_q, select_upper_d, (valid_i & ready_o), '0, clk_i, rst_ni) assign id_o = id_q; assign valid_o = valid_q; @@ -416,32 +416,16 @@ module snitch_shared_muldiv_serdiv #( assign op_b_d = (b_reg_en) ? b_mux : op_b_q; assign res_d = (load_en) ? '0 : (res_reg_en) ? {res_q[$high(res_q)-1:0], ab_comp} : res_q; - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (!rst_ni) begin - state_q <= IDLE; - op_a_q <= '0; - op_b_q <= '0; - res_q <= '0; - cnt_q <= '0; - id_q <= '0; - rem_sel_q <= 1'b0; - comp_inv_q <= 1'b0; - res_inv_q <= 1'b0; - op_b_zero_q <= 1'b0; - div_res_zero_q <= 1'b0; - end else begin - state_q <= state_d; - op_a_q <= op_a_d; - op_b_q <= op_b_d; - res_q <= res_d; - cnt_q <= cnt_d; - id_q <= id_d; - rem_sel_q <= rem_sel_d; - comp_inv_q <= comp_inv_d; - res_inv_q <= res_inv_d; - op_b_zero_q <= op_b_zero_d; - div_res_zero_q <= div_res_zero_d; - end - end + `FF(state_q, state_d, IDLE, clk_i, rst_ni) + `FF(op_a_q, op_a_d, '0, clk_i, rst_ni) + `FF(op_b_q, op_b_d, '0, clk_i, rst_ni) + `FF(res_q, res_d, '0, clk_i, rst_ni) + `FF(cnt_q, cnt_d, '0, clk_i, rst_ni) + `FF(id_q, id_d, '0, clk_i, rst_ni) + `FF(rem_sel_q, rem_sel_d, '0, clk_i, rst_ni) + `FF(comp_inv_q, comp_inv_d, '0, clk_i, rst_ni) + `FF(res_inv_q, res_inv_d, '0, clk_i, rst_ni) + `FF(op_b_zero_q, op_b_zero_d, '0, clk_i, rst_ni) + `FF(div_res_zero_q, div_res_zero_d, '0, clk_i, rst_ni) endmodule diff --git a/hw/snitch_ipu/src/snitch_int_ss.sv b/hw/snitch_ipu/src/snitch_int_ss.sv index 011aa6bfc..6a43e2ed3 100644 --- a/hw/snitch_ipu/src/snitch_int_ss.sv +++ b/hw/snitch_ipu/src/snitch_int_ss.sv @@ -601,7 +601,7 @@ module snitch_int_ss import riscv_instr::*; import snitch_ipu_pkg::*; import sni ); for (genvar i = 0; i < 2; i++) begin : gen_multi_cycle_buffer - `FFLNR(imd_val_q[i], imd_val_q[i], imd_val_we[i], clk_i) + `FFL(imd_val_q[i], imd_val_q[i], imd_val_we[i], '0, clk_i, rst_i) end // --------------- @@ -615,6 +615,7 @@ module snitch_int_ss import riscv_instr::*; import snitch_ipu_pkg::*; import sni .ADDR_WIDTH ( 5 ) ) i_ipu_regfile ( .clk_i, + .rst_ni (~rst_i), .raddr_i ( int_raddr ), .rdata_o ( int_rdata ), .waddr_i ( int_waddr ), diff --git a/hw/snitch_ssr/src/snitch_ssr.sv b/hw/snitch_ssr/src/snitch_ssr.sv index d48f686d0..f7c891977 100644 --- a/hw/snitch_ssr/src/snitch_ssr.sv +++ b/hw/snitch_ssr/src/snitch_ssr.sv @@ -110,7 +110,7 @@ module snitch_ssr import snitch_ssr_pkg::*; #( // When the SSR reverses direction, the inflight data *must* be vacated before any // requests can be issued (i.e. addresses consumed) to prevent stream corruption. logic agen_write_q, agen_write_reversing, agen_flush, dm_write; - `FFLARN(agen_write_q, agen_write, agen_valid & agen_ready, '0, clk_i, rst_ni) + `FFL(agen_write_q, agen_write, agen_valid & agen_ready, '0, clk_i, rst_ni) // When direction reverses, deassert agen readiness until credits replenished. // The datamover must preserve its directional muxing until the flush is complete. diff --git a/hw/snitch_ssr/src/snitch_ssr_addr_gen.sv b/hw/snitch_ssr/src/snitch_ssr_addr_gen.sv index c6ff0f06f..af1384923 100644 --- a/hw/snitch_ssr/src/snitch_ssr_addr_gen.sv +++ b/hw/snitch_ssr/src/snitch_ssr_addr_gen.sv @@ -158,14 +158,14 @@ module snitch_ssr_addr_gen import snitch_ssr_pkg::*; #( }; // Config registers - `FFARN(idx_shift_sq, idx_shift_sd, '0, clk_i, rst_ni) - `FFLARN(idx_shift_q, idx_shift_sd, config_q.done, '0, clk_i, rst_ni) - `FFARN(idx_base_sq, idx_base_sd, '0, clk_i, rst_ni) - `FFLARN(idx_base_q, idx_base_sd, config_q.done, '0, clk_i, rst_ni) - `FFARN(idx_size_sq, idx_size_sd, '0, clk_i, rst_ni) - `FFLARN(idx_size_q, idx_size_sd, config_q.done, '0, clk_i, rst_ni) - `FFARN(idx_flags_sq, idx_flags_sd, '0, clk_i, rst_ni) - `FFLARN(idx_flags_q, idx_flags_sd, config_q.done, '0, clk_i, rst_ni) + `FF(idx_shift_sq, idx_shift_sd, '0, clk_i, rst_ni) + `FFL(idx_shift_q, idx_shift_sd, config_q.done, '0, clk_i, rst_ni) + `FF(idx_base_sq, idx_base_sd, '0, clk_i, rst_ni) + `FFL(idx_base_q, idx_base_sd, config_q.done, '0, clk_i, rst_ni) + `FF(idx_size_sq, idx_size_sd, '0, clk_i, rst_ni) + `FFL(idx_size_q, idx_size_sd, config_q.done, '0, clk_i, rst_ni) + `FF(idx_flags_sq, idx_flags_sd, '0, clk_i, rst_ni) + `FFL(idx_flags_q, idx_flags_sd, config_q.done, '0, clk_i, rst_ni) // Delay register for last iteration of base loop, in case additional iteration needed. `FFLARNC(natit_base_last_q, natit_base_last_d, enable, natit_done, 1'b0, clk_i, rst_ni) @@ -309,10 +309,10 @@ module snitch_ssr_addr_gen import snitch_ssr_pkg::*; #( bound_sd[i] = cfg_wdata_i; end - `FFARN(stride_sq[i], stride_sd[i], '0, clk_i, rst_ni) - `FFLARN(stride_q[i], stride_sd[i], config_q.done, '0, clk_i, rst_ni) - `FFARN(bound_sq[i], bound_sd[i], '0, clk_i, rst_ni) - `FFLARN(bound_q[i], bound_sd[i], config_q.done, '0, clk_i, rst_ni) + `FF(stride_sq[i], stride_sd[i], '0, clk_i, rst_ni) + `FFL(stride_q[i], stride_sd[i], config_q.done, '0, clk_i, rst_ni) + `FF(bound_sq[i], bound_sd[i], '0, clk_i, rst_ni) + `FFL(bound_q[i], bound_sd[i], config_q.done, '0, clk_i, rst_ni) assign index_ena = enable & loop_enabled[i]; @@ -335,8 +335,8 @@ module snitch_ssr_addr_gen import snitch_ssr_pkg::*; #( rep_sd = cfg_wdata_i; end - `FFARN(rep_sq, rep_sd, '0, clk_i, rst_ni) - `FFLARN(rep_q, rep_sd, config_q.done, '0, clk_i, rst_ni) + `FF(rep_sq, rep_sd, '0, clk_i, rst_ni) + `FFL(rep_q, rep_sd, config_q.done, '0, clk_i, rst_ni) assign reg_rep_o = rep_q; @@ -379,10 +379,10 @@ module snitch_ssr_addr_gen import snitch_ssr_pkg::*; #( end end - `FFARN(pointer_q, pointer_qn, '0, clk_i, rst_ni) - `FFARN(pointer_sq, pointer_sqn, '0, clk_i, rst_ni) - `FFARN(config_q, config_qn, '{done: 1, default: '0}, clk_i, rst_ni) - `FFARN(config_sq, config_sqn, '{done: 1, default: '0}, clk_i, rst_ni) + `FF(pointer_q, pointer_qn, '0, clk_i, rst_ni) + `FF(pointer_sq, pointer_sqn, '0, clk_i, rst_ni) + `FF(config_q, config_qn, '{done: 1, default: '0}, clk_i, rst_ni) + `FF(config_sq, config_sqn, '{done: 1, default: '0}, clk_i, rst_ni) always_comb begin pointer_qn = pointer_q; diff --git a/hw/snitch_ssr/src/snitch_ssr_indirector.sv b/hw/snitch_ssr/src/snitch_ssr_indirector.sv index a5e84aa94..49e553f38 100644 --- a/hw/snitch_ssr/src/snitch_ssr_indirector.sv +++ b/hw/snitch_ssr/src/snitch_ssr_indirector.sv @@ -136,7 +136,7 @@ module snitch_ssr_indirector import snitch_ssr_pkg::*; #( index_t isect_cnt; assign isect_slv_up_hs = isect_slv_rsp_i.valid & isect_slv_req_o.ready; assign isect_cnt_swap = isect_slv_up_hs & isect_slv_rsp_i.done; - `FFLARN(cfg_idx_isect_o, isect_cnt, isect_cnt_swap, '0, clk_i, rst_ni) + `FFL(cfg_idx_isect_o, isect_cnt, isect_cnt_swap, '0, clk_i, rst_ni) // Counter for number of elements emitted by intersector counter #( @@ -200,8 +200,8 @@ module snitch_ssr_indirector import snitch_ssr_pkg::*; #( assign idx_word_valid_d = idx_bytecnt_rovr | (~idx_bytecnt_rovr_q & isect_slv_done); assign idx_word_clr = idx_q_hs & ~isect_slv_hs; - `FFLARN(idx_data_q, idx_data_d, idx_bytecnt_ena, 1'b0, clk_i, rst_ni) - `FFLARN(idx_strb_q, idx_strb_d, idx_bytecnt_ena, 1'b0, clk_i, rst_ni) + `FFL(idx_data_q, idx_data_d, idx_bytecnt_ena, 1'b0, clk_i, rst_ni) + `FFL(idx_strb_q, idx_strb_d, idx_bytecnt_ena, 1'b0, clk_i, rst_ni) `FFLARNC(idx_word_valid_q, idx_word_valid_d, isect_slv_hs, idx_word_clr, 1'b0, clk_i, rst_ni) // Track done and decouple address emission from index write @@ -442,7 +442,7 @@ module snitch_ssr_indirector import snitch_ssr_pkg::*; #( if (cfg_done_i) idx_isect_d = '0; else if (idx_isect_ena) idx_isect_d = idx_isect_q + 1; end - `FFARN(idx_isect_q, idx_isect_d, '0, clk_i, rst_ni) + `FF(idx_isect_q, idx_isect_d, '0, clk_i, rst_ni) end else begin : gen_no_isect_ctr assign idx_isect_q = '0; end @@ -461,7 +461,7 @@ module snitch_ssr_indirector import snitch_ssr_pkg::*; #( else if (idx_bytecnt_ena) idx_bytecnt_d = idx_bytecnt_next; end - `FFARN(idx_bytecnt_q, idx_bytecnt_d, '0, clk_i, rst_ni) + `FF(idx_bytecnt_q, idx_bytecnt_d, '0, clk_i, rst_ni) assign idx_bytecnt_next = idx_bytecnt_q + bytecnt_t'(1 << cfg_size_i); diff --git a/hw/snitch_vm/src/snitch_ptw.sv b/hw/snitch_vm/src/snitch_ptw.sv index 4f8b79e80..3b06224b0 100644 --- a/hw/snitch_vm/src/snitch_ptw.sv +++ b/hw/snitch_vm/src/snitch_ptw.sv @@ -51,16 +51,16 @@ module snitch_ptw import snitch_pkg::*; #( logic [1:0] lvl_d, lvl_q; - `FFARN(state_q, state_d, Idle, clk_i, rst_ni) + `FF(state_q, state_d, Idle, clk_i, rst_ni) pte_sv32_t pte; l0_pte_t pte_d, pte_q; logic is_4mega_d, is_4mega_q; assign pte = pte_sv32_t'(data_rsp_i.p.data[$size(pte_sv32_t)-1:0]); - `FFLNR(pte_q, pte_d, (data_rsp_i.p_valid & data_req_o.p_ready), clk_i) - `FFNR(is_4mega_q, is_4mega_d, clk_i) + `FFL(pte_q, pte_d, (data_rsp_i.p_valid & data_req_o.p_ready), '0, clk_i, rst_ni) + `FF(is_4mega_q, is_4mega_d, '0, clk_i, rst_ni) - `FFNR(lvl_q, lvl_d, clk_i) + `FF(lvl_q, lvl_d, '0, clk_i, rst_ni) assign pte_o = pte_q; assign is_4mega_o = is_4mega_q; From a7a305fa318fe6af50fb46d253aaabe1776e91f4 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 3 Jul 2024 14:06:44 +0200 Subject: [PATCH 2/6] Remove script to discover non-resetable FFs --- FindNonResettableFFs.py | 27 --------------------------- 1 file changed, 27 deletions(-) delete mode 100644 FindNonResettableFFs.py diff --git a/FindNonResettableFFs.py b/FindNonResettableFFs.py deleted file mode 100644 index ae6e820f0..000000000 --- a/FindNonResettableFFs.py +++ /dev/null @@ -1,27 +0,0 @@ -import os - -text = 'amo_op_e' -path = '/scratch/bsc24f10/Documents/MonocerosGithubRepo/monoceros/snitch_cluster/hw' - -def searchText(path): - - os.chdir(path) - files = os.listdir(path) - #print(files) - - for file_name in files: - abs_path = os.path.join(path, file_name) - #print('is '+ abs_path + ' directory? : ') - if os.path.isdir(abs_path): - #print("Directory found: " + abs_path) - searchText(abs_path) - - if os.path.isfile(abs_path): - #print("File found: " + abs_path) - with open(abs_path, 'r') as f: - if text in f.read(): - final_path = os.path.abspath(file_name) - print(text + " word found in this path " + final_path) - pass -searchText(path) -print("DONE") From 121e592079a05a3f47e401cf57f99bfa148b970d Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 3 Jul 2024 14:59:04 +0200 Subject: [PATCH 3/6] Use CamelCase parameters in `snitch_regfile` --- hw/snitch/src/snitch.sv | 10 +++--- hw/snitch/src/snitch_regfile_ff.sv | 48 ++++++++++++------------- hw/snitch/src/snitch_regfile_fpga.sv | 48 ++++++++++++------------- hw/snitch/src/snitch_regfile_latch.sv | 50 +++++++++++++-------------- hw/snitch_cluster/src/snitch_fp_ss.sv | 10 +++--- hw/snitch_ipu/src/snitch_int_ss.sv | 10 +++--- 6 files changed, 88 insertions(+), 88 deletions(-) diff --git a/hw/snitch/src/snitch.sv b/hw/snitch/src/snitch.sv index 29fd2b2f7..59723954a 100644 --- a/hw/snitch/src/snitch.sv +++ b/hw/snitch/src/snitch.sv @@ -2623,11 +2623,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( // pragma translate_on snitch_regfile #( - .DATA_WIDTH ( 32 ), - .NR_READ_PORTS ( 2 ), - .NR_WRITE_PORTS ( 1 ), - .ZERO_REG_ZERO ( 1 ), - .ADDR_WIDTH ( RegWidth ) + .DataWidth ( 32 ), + .NrReadPorts ( 2 ), + .NrWritePorts ( 1 ), + .ZeroRegZero ( 1 ), + .AddrWidth ( RegWidth ) ) i_snitch_regfile ( .clk_i, .rst_ni ( ~rst_i ), diff --git a/hw/snitch/src/snitch_regfile_ff.sv b/hw/snitch/src/snitch_regfile_ff.sv index 601ef991a..f32a4b645 100644 --- a/hw/snitch/src/snitch_regfile_ff.sv +++ b/hw/snitch/src/snitch_regfile_ff.sv @@ -6,42 +6,42 @@ // Description: Variable Register File // verilog_lint: waive module-filename module snitch_regfile #( - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned NR_READ_PORTS = 2, - parameter int unsigned NR_WRITE_PORTS = 1, - parameter bit ZERO_REG_ZERO = 0, - parameter int unsigned ADDR_WIDTH = 4 + parameter int unsigned DataWidth = 32, + parameter int unsigned NrReadPorts = 2, + parameter int unsigned NrWritePorts = 1, + parameter bit ZeroRegZero = 0, + parameter int unsigned AddrWidth = 4 ) ( // clock and reset - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // read port - input logic [NR_READ_PORTS-1:0][ADDR_WIDTH-1:0] raddr_i, - output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, + input logic [NrReadPorts-1:0][AddrWidth-1:0] raddr_i, + output logic [NrReadPorts-1:0][DataWidth-1:0] rdata_o, // write port - input logic [NR_WRITE_PORTS-1:0][ADDR_WIDTH-1:0] waddr_i, - input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i, - input logic [NR_WRITE_PORTS-1:0] we_i + input logic [NrWritePorts-1:0][AddrWidth-1:0] waddr_i, + input logic [NrWritePorts-1:0][DataWidth-1:0] wdata_i, + input logic [NrWritePorts-1:0] we_i ); - localparam int unsigned NumWords = 2**ADDR_WIDTH; + localparam int unsigned NumWords = 2**AddrWidth; - logic [NumWords-1:0][DATA_WIDTH-1:0] mem; - logic [NR_WRITE_PORTS-1:0][NumWords-1:0] we_dec; + logic [NumWords-1:0][DataWidth-1:0] mem; + logic [NrWritePorts-1:0][NumWords-1:0] we_dec; - always_comb begin : we_decoder - for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin - for (int unsigned i = 0; i < NumWords; i++) begin - if (waddr_i[j] == i) we_dec[j][i] = we_i[j]; - else we_dec[j][i] = 1'b0; - end + always_comb begin : we_decoder + for (int unsigned j = 0; j < NrWritePorts; j++) begin + for (int unsigned i = 0; i < NumWords; i++) begin + if (waddr_i[j] == i) we_dec[j][i] = we_i[j]; + else we_dec[j][i] = 1'b0; end end + end // loop from 1 to NumWords-1 as R0 is nil always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral - for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin + for (int unsigned j = 0; j < NrWritePorts; j++) begin for (int unsigned i = 0; i < NumWords; i++) begin if (~rst_ni) begin mem[i] <= '0; @@ -51,13 +51,13 @@ module snitch_regfile #( end end end - if (ZERO_REG_ZERO) begin + if (ZeroRegZero) begin mem[0] <= '0; end end end - for (genvar i = 0; i < NR_READ_PORTS; i++) begin : gen_read_port + for (genvar i = 0; i < NrReadPorts; i++) begin : gen_read_port assign rdata_o[i] = mem[raddr_i[i]]; end diff --git a/hw/snitch/src/snitch_regfile_fpga.sv b/hw/snitch/src/snitch_regfile_fpga.sv index bee0569b5..b2249d463 100644 --- a/hw/snitch/src/snitch_regfile_fpga.sv +++ b/hw/snitch/src/snitch_regfile_fpga.sv @@ -22,42 +22,42 @@ // verilog_lint: waive module-filename module snitch_regfile #( - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned NR_READ_PORTS = 2, - parameter int unsigned NR_WRITE_PORTS = 1, - parameter bit ZERO_REG_ZERO = 0, - parameter int unsigned ADDR_WIDTH = 4 + parameter int unsigned DataWidth = 32, + parameter int unsigned NrReadPorts = 2, + parameter int unsigned NrWritePorts = 1, + parameter bit ZeroRegZero = 0, + parameter int unsigned AddrWidth = 4 )( // clock and reset - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // read port - input logic [NR_READ_PORTS-1:0][4:0] raddr_i, - output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, + input logic [NrReadPorts-1:0][4:0] raddr_i, + output logic [NrReadPorts-1:0][DataWidth-1:0] rdata_o, // write port - input logic [NR_WRITE_PORTS-1:0][4:0] waddr_i, - input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i, - input logic [NR_WRITE_PORTS-1:0] we_i + input logic [NrWritePorts-1:0][4:0] waddr_i, + input logic [NrWritePorts-1:0][DataWidth-1:0] wdata_i, + input logic [NrWritePorts-1:0] we_i ); - localparam int unsigned NumWords = 2**ADDR_WIDTH; - localparam int unsigned LogNrWritePorts = NR_WRITE_PORTS == 1 ? 1 : $clog2(NR_WRITE_PORTS); + localparam int unsigned NumWords = 2**AddrWidth; + localparam int unsigned LogNrWritePorts = NrWritePorts == 1 ? 1 : $clog2(NrWritePorts); // The register values are stored in distinct separate RAM blocks each featuring 1 sync-write and // N async-read ports. A set of narrow flip-flops keeps track of which RAM block contains the // valid entry for each register. // Distributed RAM usually supports one write port per block. We need one block per write port. - logic [NumWords-1:0][DATA_WIDTH-1:0] mem [NR_WRITE_PORTS]; + logic [NumWords-1:0][DataWidth-1:0] mem [NrWritePorts]; - logic [NR_WRITE_PORTS-1:0][NumWords-1:0] we_dec; + logic [NrWritePorts-1:0][NumWords-1:0] we_dec; logic [NumWords-1:0][LogNrWritePorts-1:0] mem_block_sel; logic [NumWords-1:0][LogNrWritePorts-1:0] mem_block_sel_q; // write adress decoder (for block selector) always_comb begin - for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin + for (int unsigned j = 0; j < NrWritePorts; j++) begin for (int unsigned i = 0; i < NumWords; i++) begin if (waddr_i[j] == i) begin we_dec[j][i] = we_i[j]; @@ -75,7 +75,7 @@ module snitch_regfile #( always_comb begin mem_block_sel = mem_block_sel_q; for (int i = 0; i Date: Wed, 3 Jul 2024 15:28:59 +0200 Subject: [PATCH 4/6] Fix elaboration of snitch regfile --- hw/snitch/src/snitch_regfile_ff.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/snitch/src/snitch_regfile_ff.sv b/hw/snitch/src/snitch_regfile_ff.sv index f32a4b645..ab815c43f 100644 --- a/hw/snitch/src/snitch_regfile_ff.sv +++ b/hw/snitch/src/snitch_regfile_ff.sv @@ -41,11 +41,11 @@ module snitch_regfile #( // loop from 1 to NumWords-1 as R0 is nil always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral - for (int unsigned j = 0; j < NrWritePorts; j++) begin - for (int unsigned i = 0; i < NumWords; i++) begin - if (~rst_ni) begin - mem[i] <= '0; - end else begin + if (~rst_ni) begin + mem <= '0; + end else begin + for (int unsigned j = 0; j < NrWritePorts; j++) begin + for (int unsigned i = 0; i < NumWords; i++) begin if (we_dec[j][i]) begin mem[i] <= wdata_i[j]; end From 1390fd50b7b8eee9eec47642c1a94ac1ba9a3af8 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 3 Jul 2024 15:29:06 +0200 Subject: [PATCH 5/6] Remove unused include --- hw/snitch/src/snitch_l0_tlb.sv | 1 - hw/snitch_cluster/src/snitch_clkdiv2.sv | 1 - 2 files changed, 2 deletions(-) diff --git a/hw/snitch/src/snitch_l0_tlb.sv b/hw/snitch/src/snitch_l0_tlb.sv index 373cd9399..6196afc05 100644 --- a/hw/snitch/src/snitch_l0_tlb.sv +++ b/hw/snitch/src/snitch_l0_tlb.sv @@ -5,7 +5,6 @@ // Author: Florian Zaruba `include "common_cells/registers.svh" -`include "common_cells/assertions.svh" // MMU w/ L0 TLB module snitch_l0_tlb import snitch_pkg::*; #( diff --git a/hw/snitch_cluster/src/snitch_clkdiv2.sv b/hw/snitch_cluster/src/snitch_clkdiv2.sv index 429b25cf2..401b6ad23 100644 --- a/hw/snitch_cluster/src/snitch_clkdiv2.sv +++ b/hw/snitch_cluster/src/snitch_clkdiv2.sv @@ -27,7 +27,6 @@ // Author: Fabian Schuiki `include "common_cells/registers.svh" -`include "common_cells/assertions.svh" (* no_ungroup *) (* no_boundary_optimization *) From 7bf05c569205dbb929c39cece0ca15bf05b6b1b8 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Fri, 19 Jul 2024 16:24:37 +0200 Subject: [PATCH 6/6] hw: Fix wrong FF --- hw/snitch_ipu/src/snitch_int_ss.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/snitch_ipu/src/snitch_int_ss.sv b/hw/snitch_ipu/src/snitch_int_ss.sv index 337383c5f..bcd6a93d2 100644 --- a/hw/snitch_ipu/src/snitch_int_ss.sv +++ b/hw/snitch_ipu/src/snitch_int_ss.sv @@ -601,7 +601,7 @@ module snitch_int_ss import riscv_instr::*; import snitch_ipu_pkg::*; import sni ); for (genvar i = 0; i < 2; i++) begin : gen_multi_cycle_buffer - `FFL(imd_val_q[i], imd_val_q[i], imd_val_we[i], '0, clk_i, rst_i) + `FFLAR(imd_val_q[i], imd_val_q[i], imd_val_we[i], '0, clk_i, rst_i) end // ---------------