From dae7047f45218c73d584fd10e80e5a70928233f9 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Thu, 29 Aug 2024 22:35:53 +0200 Subject: [PATCH] hw: Update sources --- .../snitch_cluster_peripheral_reg_pkg.sv | 27 ++- .../snitch_cluster_peripheral_reg_top.sv | 178 +++++++++++++++++- 2 files changed, 188 insertions(+), 17 deletions(-) diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv index 3795d8013..50b789c34 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv @@ -8,6 +8,7 @@ package snitch_cluster_peripheral_reg_pkg; // Param list parameter int NumPerfCounters = 16; + parameter int NumCtrlScratch = 4; // Address widths within the block parameter int BlockAw = 9; @@ -128,9 +129,13 @@ package snitch_cluster_peripheral_reg_pkg; parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET = 9'h 168; parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET = 9'h 170; parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET = 9'h 178; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 9'h 180; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 9'h 188; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 190; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0_OFFSET = 9'h 180; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1_OFFSET = 9'h 188; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2_OFFSET = 9'h 190; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3_OFFSET = 9'h 198; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 9'h 1a0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 9'h 1a8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 1b0; // Reset values for hwext registers and their fields parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_RESVAL = 32'h 0; @@ -218,13 +223,17 @@ package snitch_cluster_peripheral_reg_pkg; SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13, SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14, SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15, + SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0, + SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1, + SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2, + SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3, SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET, SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR, SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE } snitch_cluster_peripheral_id_e; // Register width information to check illegal writes - parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [51] = '{ + parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [55] = '{ 4'b 0001, // index[ 0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0 4'b 0001, // index[ 1] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1 4'b 0001, // index[ 2] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2 @@ -273,9 +282,13 @@ package snitch_cluster_peripheral_reg_pkg; 4'b 1111, // index[45] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13 4'b 1111, // index[46] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14 4'b 1111, // index[47] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15 - 4'b 1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET - 4'b 1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR - 4'b 0001 // index[50] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE + 4'b 1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0 + 4'b 1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1 + 4'b 1111, // index[50] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2 + 4'b 1111, // index[51] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3 + 4'b 1111, // index[52] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET + 4'b 1111, // index[53] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR + 4'b 0001 // index[54] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE }; endpackage diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv index fb6cdb86d..62781fda6 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv @@ -308,6 +308,18 @@ module snitch_cluster_peripheral_reg_top #( logic [47:0] perf_cnt_15_wd; logic perf_cnt_15_we; logic perf_cnt_15_re; + logic [31:0] scratch_0_qs; + logic [31:0] scratch_0_wd; + logic scratch_0_we; + logic [31:0] scratch_1_qs; + logic [31:0] scratch_1_wd; + logic scratch_1_we; + logic [31:0] scratch_2_qs; + logic [31:0] scratch_2_wd; + logic scratch_2_we; + logic [31:0] scratch_3_qs; + logic [31:0] scratch_3_wd; + logic scratch_3_we; logic [31:0] cl_clint_set_wd; logic cl_clint_set_we; logic [31:0] cl_clint_clear_wd; @@ -1538,6 +1550,116 @@ module snitch_cluster_peripheral_reg_top #( ); + + // Subregister 0 of Multireg scratch + // R[scratch_0]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_scratch_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (scratch_0_we), + .wd (scratch_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (scratch_0_qs) + ); + + // Subregister 1 of Multireg scratch + // R[scratch_1]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_scratch_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (scratch_1_we), + .wd (scratch_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (scratch_1_qs) + ); + + // Subregister 2 of Multireg scratch + // R[scratch_2]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_scratch_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (scratch_2_we), + .wd (scratch_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (scratch_2_qs) + ); + + // Subregister 3 of Multireg scratch + // R[scratch_3]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_scratch_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (scratch_3_we), + .wd (scratch_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (scratch_3_qs) + ); + + // R[cl_clint_set]: V(True) prim_subreg_ext #( @@ -1598,7 +1720,7 @@ module snitch_cluster_peripheral_reg_top #( - logic [50:0] addr_hit; + logic [54:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_OFFSET); @@ -1649,9 +1771,13 @@ module snitch_cluster_peripheral_reg_top #( addr_hit[45] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET); addr_hit[46] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET); addr_hit[47] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET); - addr_hit[48] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET); - addr_hit[49] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET); - addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); + addr_hit[48] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0_OFFSET); + addr_hit[49] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1_OFFSET); + addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2_OFFSET); + addr_hit[51] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3_OFFSET); + addr_hit[52] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET); + addr_hit[53] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET); + addr_hit[54] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1709,7 +1835,11 @@ module snitch_cluster_peripheral_reg_top #( (addr_hit[47] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[47] & ~reg_be))) | (addr_hit[48] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[48] & ~reg_be))) | (addr_hit[49] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[49] & ~reg_be))) | - (addr_hit[50] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[50] & ~reg_be))))); + (addr_hit[50] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[50] & ~reg_be))) | + (addr_hit[51] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[51] & ~reg_be))) | + (addr_hit[52] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[52] & ~reg_be))) | + (addr_hit[53] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[53] & ~reg_be))) | + (addr_hit[54] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[54] & ~reg_be))))); end assign perf_cnt_en_0_we = addr_hit[0] & reg_we & !reg_error; @@ -1952,13 +2082,25 @@ module snitch_cluster_peripheral_reg_top #( assign perf_cnt_15_wd = reg_wdata[47:0]; assign perf_cnt_15_re = addr_hit[47] & reg_re & !reg_error; - assign cl_clint_set_we = addr_hit[48] & reg_we & !reg_error; + assign scratch_0_we = addr_hit[48] & reg_we & !reg_error; + assign scratch_0_wd = reg_wdata[31:0]; + + assign scratch_1_we = addr_hit[49] & reg_we & !reg_error; + assign scratch_1_wd = reg_wdata[31:0]; + + assign scratch_2_we = addr_hit[50] & reg_we & !reg_error; + assign scratch_2_wd = reg_wdata[31:0]; + + assign scratch_3_we = addr_hit[51] & reg_we & !reg_error; + assign scratch_3_wd = reg_wdata[31:0]; + + assign cl_clint_set_we = addr_hit[52] & reg_we & !reg_error; assign cl_clint_set_wd = reg_wdata[31:0]; - assign cl_clint_clear_we = addr_hit[49] & reg_we & !reg_error; + assign cl_clint_clear_we = addr_hit[53] & reg_we & !reg_error; assign cl_clint_clear_wd = reg_wdata[31:0]; - assign icache_prefetch_enable_we = addr_hit[50] & reg_we & !reg_error; + assign icache_prefetch_enable_we = addr_hit[54] & reg_we & !reg_error; assign icache_prefetch_enable_wd = reg_wdata[0]; // Read data return @@ -2174,14 +2316,30 @@ module snitch_cluster_peripheral_reg_top #( end addr_hit[48]: begin - reg_rdata_next[31:0] = '0; + reg_rdata_next[31:0] = scratch_0_qs; end addr_hit[49]: begin - reg_rdata_next[31:0] = '0; + reg_rdata_next[31:0] = scratch_1_qs; end addr_hit[50]: begin + reg_rdata_next[31:0] = scratch_2_qs; + end + + addr_hit[51]: begin + reg_rdata_next[31:0] = scratch_3_qs; + end + + addr_hit[52]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[53]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[54]: begin reg_rdata_next[0] = '0; end