From c6190223d80ded2cf8597b9145d1589322c51325 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 3 Jul 2024 14:59:04 +0200 Subject: [PATCH] Use CamelCase parameters in `snitch_regfile` --- hw/snitch/src/snitch.sv | 10 +++--- hw/snitch/src/snitch_regfile_ff.sv | 48 ++++++++++++------------- hw/snitch/src/snitch_regfile_fpga.sv | 48 ++++++++++++------------- hw/snitch/src/snitch_regfile_latch.sv | 50 +++++++++++++-------------- hw/snitch_cluster/src/snitch_fp_ss.sv | 10 +++--- hw/snitch_ipu/src/snitch_int_ss.sv | 10 +++--- 6 files changed, 88 insertions(+), 88 deletions(-) diff --git a/hw/snitch/src/snitch.sv b/hw/snitch/src/snitch.sv index 29fd2b2f70..59723954a3 100644 --- a/hw/snitch/src/snitch.sv +++ b/hw/snitch/src/snitch.sv @@ -2623,11 +2623,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( // pragma translate_on snitch_regfile #( - .DATA_WIDTH ( 32 ), - .NR_READ_PORTS ( 2 ), - .NR_WRITE_PORTS ( 1 ), - .ZERO_REG_ZERO ( 1 ), - .ADDR_WIDTH ( RegWidth ) + .DataWidth ( 32 ), + .NrReadPorts ( 2 ), + .NrWritePorts ( 1 ), + .ZeroRegZero ( 1 ), + .AddrWidth ( RegWidth ) ) i_snitch_regfile ( .clk_i, .rst_ni ( ~rst_i ), diff --git a/hw/snitch/src/snitch_regfile_ff.sv b/hw/snitch/src/snitch_regfile_ff.sv index 601ef991a6..f32a4b645b 100644 --- a/hw/snitch/src/snitch_regfile_ff.sv +++ b/hw/snitch/src/snitch_regfile_ff.sv @@ -6,42 +6,42 @@ // Description: Variable Register File // verilog_lint: waive module-filename module snitch_regfile #( - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned NR_READ_PORTS = 2, - parameter int unsigned NR_WRITE_PORTS = 1, - parameter bit ZERO_REG_ZERO = 0, - parameter int unsigned ADDR_WIDTH = 4 + parameter int unsigned DataWidth = 32, + parameter int unsigned NrReadPorts = 2, + parameter int unsigned NrWritePorts = 1, + parameter bit ZeroRegZero = 0, + parameter int unsigned AddrWidth = 4 ) ( // clock and reset - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // read port - input logic [NR_READ_PORTS-1:0][ADDR_WIDTH-1:0] raddr_i, - output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, + input logic [NrReadPorts-1:0][AddrWidth-1:0] raddr_i, + output logic [NrReadPorts-1:0][DataWidth-1:0] rdata_o, // write port - input logic [NR_WRITE_PORTS-1:0][ADDR_WIDTH-1:0] waddr_i, - input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i, - input logic [NR_WRITE_PORTS-1:0] we_i + input logic [NrWritePorts-1:0][AddrWidth-1:0] waddr_i, + input logic [NrWritePorts-1:0][DataWidth-1:0] wdata_i, + input logic [NrWritePorts-1:0] we_i ); - localparam int unsigned NumWords = 2**ADDR_WIDTH; + localparam int unsigned NumWords = 2**AddrWidth; - logic [NumWords-1:0][DATA_WIDTH-1:0] mem; - logic [NR_WRITE_PORTS-1:0][NumWords-1:0] we_dec; + logic [NumWords-1:0][DataWidth-1:0] mem; + logic [NrWritePorts-1:0][NumWords-1:0] we_dec; - always_comb begin : we_decoder - for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin - for (int unsigned i = 0; i < NumWords; i++) begin - if (waddr_i[j] == i) we_dec[j][i] = we_i[j]; - else we_dec[j][i] = 1'b0; - end + always_comb begin : we_decoder + for (int unsigned j = 0; j < NrWritePorts; j++) begin + for (int unsigned i = 0; i < NumWords; i++) begin + if (waddr_i[j] == i) we_dec[j][i] = we_i[j]; + else we_dec[j][i] = 1'b0; end end + end // loop from 1 to NumWords-1 as R0 is nil always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral - for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin + for (int unsigned j = 0; j < NrWritePorts; j++) begin for (int unsigned i = 0; i < NumWords; i++) begin if (~rst_ni) begin mem[i] <= '0; @@ -51,13 +51,13 @@ module snitch_regfile #( end end end - if (ZERO_REG_ZERO) begin + if (ZeroRegZero) begin mem[0] <= '0; end end end - for (genvar i = 0; i < NR_READ_PORTS; i++) begin : gen_read_port + for (genvar i = 0; i < NrReadPorts; i++) begin : gen_read_port assign rdata_o[i] = mem[raddr_i[i]]; end diff --git a/hw/snitch/src/snitch_regfile_fpga.sv b/hw/snitch/src/snitch_regfile_fpga.sv index bee0569b53..b2249d4633 100644 --- a/hw/snitch/src/snitch_regfile_fpga.sv +++ b/hw/snitch/src/snitch_regfile_fpga.sv @@ -22,42 +22,42 @@ // verilog_lint: waive module-filename module snitch_regfile #( - parameter int unsigned DATA_WIDTH = 32, - parameter int unsigned NR_READ_PORTS = 2, - parameter int unsigned NR_WRITE_PORTS = 1, - parameter bit ZERO_REG_ZERO = 0, - parameter int unsigned ADDR_WIDTH = 4 + parameter int unsigned DataWidth = 32, + parameter int unsigned NrReadPorts = 2, + parameter int unsigned NrWritePorts = 1, + parameter bit ZeroRegZero = 0, + parameter int unsigned AddrWidth = 4 )( // clock and reset - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // read port - input logic [NR_READ_PORTS-1:0][4:0] raddr_i, - output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, + input logic [NrReadPorts-1:0][4:0] raddr_i, + output logic [NrReadPorts-1:0][DataWidth-1:0] rdata_o, // write port - input logic [NR_WRITE_PORTS-1:0][4:0] waddr_i, - input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i, - input logic [NR_WRITE_PORTS-1:0] we_i + input logic [NrWritePorts-1:0][4:0] waddr_i, + input logic [NrWritePorts-1:0][DataWidth-1:0] wdata_i, + input logic [NrWritePorts-1:0] we_i ); - localparam int unsigned NumWords = 2**ADDR_WIDTH; - localparam int unsigned LogNrWritePorts = NR_WRITE_PORTS == 1 ? 1 : $clog2(NR_WRITE_PORTS); + localparam int unsigned NumWords = 2**AddrWidth; + localparam int unsigned LogNrWritePorts = NrWritePorts == 1 ? 1 : $clog2(NrWritePorts); // The register values are stored in distinct separate RAM blocks each featuring 1 sync-write and // N async-read ports. A set of narrow flip-flops keeps track of which RAM block contains the // valid entry for each register. // Distributed RAM usually supports one write port per block. We need one block per write port. - logic [NumWords-1:0][DATA_WIDTH-1:0] mem [NR_WRITE_PORTS]; + logic [NumWords-1:0][DataWidth-1:0] mem [NrWritePorts]; - logic [NR_WRITE_PORTS-1:0][NumWords-1:0] we_dec; + logic [NrWritePorts-1:0][NumWords-1:0] we_dec; logic [NumWords-1:0][LogNrWritePorts-1:0] mem_block_sel; logic [NumWords-1:0][LogNrWritePorts-1:0] mem_block_sel_q; // write adress decoder (for block selector) always_comb begin - for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin + for (int unsigned j = 0; j < NrWritePorts; j++) begin for (int unsigned i = 0; i < NumWords; i++) begin if (waddr_i[j] == i) begin we_dec[j][i] = we_i[j]; @@ -75,7 +75,7 @@ module snitch_regfile #( always_comb begin mem_block_sel = mem_block_sel_q; for (int i = 0; i