From bcca6eff5f54db2874891c09d7fbedad6e4fed7e Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Fri, 3 Nov 2023 15:03:02 +0100 Subject: [PATCH] target/cluster: Expose `cluster_base` ports --- docs/schema/snitch_cluster.schema.json | 5 +++++ hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl | 10 +++++----- util/clustergen/cluster.py | 1 - 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/docs/schema/snitch_cluster.schema.json b/docs/schema/snitch_cluster.schema.json index 6e8c1181ad..e0a66cd449 100644 --- a/docs/schema/snitch_cluster.schema.json +++ b/docs/schema/snitch_cluster.schema.json @@ -141,6 +141,11 @@ "description": "Whether to provide a debug request input and external debug features", "default": true }, + "cluster_base_expose": { + "type": "boolean", + "description": "Whether to expose base_addr and base_hart_id", + "default": false + }, "sram_cfg_expose": { "type": "boolean", "description": "Whether to expose memory cut configuration inputs for implementation", diff --git a/hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl b/hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl index 6c1df0dc1f..179fdf7825 100644 --- a/hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl +++ b/hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl @@ -222,7 +222,7 @@ module ${cfg['name']}_wrapper ( input logic [${cfg['pkg_name']}::NrCores-1:0] meip_i, input logic [${cfg['pkg_name']}::NrCores-1:0] mtip_i, input logic [${cfg['pkg_name']}::NrCores-1:0] msip_i, -% if not cfg['tie_ports']: +% if cfg['cluster_base_expose']: input logic [9:0] hart_base_id_i, input logic [${cfg['addr_width']-1}:0] cluster_base_addr_i, % endif @@ -344,12 +344,12 @@ module ${cfg['name']}_wrapper ( .meip_i, .mtip_i, .msip_i, -% if cfg['tie_ports']: - .hart_base_id_i (${to_sv_hex(cfg['cluster_base_hartid'], 10)}), - .cluster_base_addr_i (${to_sv_hex(cfg['cluster_base_addr'], cfg['addr_width'])}), -% else: +% if cfg['cluster_base_expose']: .hart_base_id_i, .cluster_base_addr_i, +% else: + .hart_base_id_i (${to_sv_hex(cfg['cluster_base_hartid'], 10)}), + .cluster_base_addr_i (${to_sv_hex(cfg['cluster_base_addr'], cfg['addr_width'])}), % endif % if cfg['timing']['iso_crossings']: .clk_d2_bypass_i, diff --git a/util/clustergen/cluster.py b/util/clustergen/cluster.py index 3b9badb648..608a9dacfd 100644 --- a/util/clustergen/cluster.py +++ b/util/clustergen/cluster.py @@ -374,7 +374,6 @@ def __init__(self, cfg): pma_cfg.add_region_length(PMA.CACHED, self.cfg['dram']['address'], self.cfg['dram']['length'], self.cfg['cluster']['addr_width']) - self.cfg['cluster']['tie_ports'] = True # Store Snitch cluster config in separate variable self.cluster = SnitchCluster(cfg["cluster"], pma_cfg)