From b9af419cb87bd0a84e1bb328463e6a40283087f2 Mon Sep 17 00:00:00 2001
From: Luca Colagrande <luca.colagrande3@gmail.com>
Date: Wed, 10 Jan 2024 13:28:41 +0100
Subject: [PATCH] target: Align Verilator timescale with Questa

---
 target/common/common.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/common/common.mk b/target/common/common.mk
index f5d746ebfa..143f9b9a81 100644
--- a/target/common/common.mk
+++ b/target/common/common.mk
@@ -77,6 +77,7 @@ VLT_FLAGS    += -Wno-UNSIGNED
 VLT_FLAGS    += -Wno-UNOPTFLAT
 VLT_FLAGS    += -Wno-fatal
 VLT_FLAGS    += --unroll-count 1024
+VLT_FLAGS    += --timescale 1ns/1ps
 VLT_CFLAGS   += -std=c++14 -pthread
 VLT_CFLAGS   +=-I ${VLT_BUILDDIR} -I $(VLT_ROOT)/include -I $(VLT_ROOT)/include/vltstd -I $(VLT_FESVR)/include -I $(TB_DIR) -I ${MKFILE_DIR}/test