From 7bdd4a2f291dbd8d0acba42f4188189446678b00 Mon Sep 17 00:00:00 2001
From: Tim Fischer <fischeti@iis.ee.ethz.ch>
Date: Thu, 8 Aug 2024 19:49:48 +0200
Subject: [PATCH] make: Include SV files from include directories

---
 target/common/common.mk | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/common/common.mk b/target/common/common.mk
index eb1180a2c..d15ffba05 100644
--- a/target/common/common.mk
+++ b/target/common/common.mk
@@ -47,10 +47,15 @@ VLT_ROOT        ?= ${VERILATOR_ROOT}
 VLT_JOBS        ?= $(shell nproc)
 VLT_NUM_THREADS ?= 1
 
+MATCH_END := '/+incdir+/ s/$$/\/*\/*/'
+MATCH_BGN := 's/+incdir+//g'
+MATCH_DEF := '/+define+/d'
+SED_SRCS  := sed -e ${MATCH_END} -e ${MATCH_BGN} -e ${MATCH_DEF}
+
 COMMON_BENDER_FLAGS += -t rtl
 
 VSIM_BENDER   += $(COMMON_BENDER_FLAGS) -t test -t simulation -t vsim
-VSIM_SOURCES   = $(shell ${BENDER} script flist ${VSIM_BENDER})
+VSIM_SOURCES   = $(shell ${BENDER} script flist-plus ${VSIM_BENDER} | ${SED_SRCS})
 VSIM_BUILDDIR ?= work-vsim
 VSIM_FLAGS    += -t 1ps
 ifeq ($(DEBUG), ON)
@@ -63,7 +68,7 @@ endif
 # VCS_BUILDDIR should to be the same as the `DEFAULT : ./work-vcs`
 # in target/snitch_cluster/synopsys_sim.setup
 VCS_BENDER   += $(COMMON_BENDER_FLAGS) -t test -t simulation -t vcs
-VCS_SOURCES   = $(shell ${BENDER} script flist ${VCS_BENDER})
+VCS_SOURCES   = $(shell ${BENDER} script flist-plus ${VCS_BENDER} | ${SED_SRCS})
 VCS_BUILDDIR := work-vcs
 
 # fesvr is being installed here
@@ -71,7 +76,7 @@ FESVR         ?= ${MKFILE_DIR}work
 FESVR_VERSION ?= 35d50bc40e59ea1d5566fbd3d9226023821b1bb6
 
 VLT_BENDER   += $(COMMON_BENDER_FLAGS) -DCOMMON_CELLS_ASSERTS_OFF
-VLT_SOURCES   = $(shell ${BENDER} script flist ${VLT_BENDER})
+VLT_SOURCES   = $(shell ${BENDER} script flist-plus ${VLT_BENDER} | ${SED_SRCS})
 VLT_BUILDDIR := $(abspath work-vlt)
 VLT_FESVR     = $(VLT_BUILDDIR)/riscv-isa-sim
 VLT_FLAGS    += --timing