From 42d430ddd7829a251c28f8560cd1ae8ea1e327b5 Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Fri, 9 Aug 2024 09:49:56 +0200 Subject: [PATCH] hw: Improve performance counters for bring-up (#155) Co-authored-by: Milos Hirsl Co-authored-by: Luca Colagrande --- .github/workflows/lint.yml | 28 +- hw/snitch_cluster/src/snitch_cluster.sv | 13 +- .../src/snitch_cluster_peripheral/Makefile | 26 - .../snitch_cluster_peripheral.sv | 291 +- .../snitch_cluster_peripheral_reg.hjson | 581 +- .../snitch_cluster_peripheral_reg_pkg.sv | 487 +- .../snitch_cluster_peripheral_reg_top.sv | 18546 ++-------------- sw/dnn/conv2d/src/main.c | 18 - sw/snRuntime/api/memory_decls.h | 2 - sw/snRuntime/src/perf_cnt.c | 16 + sw/snRuntime/src/perf_cnt.h | 136 +- sw/tests/perf_cnt.c | 160 +- target/snitch_cluster/Makefile | 23 +- target/snitch_cluster/sw/run.yaml | 1 + .../runtime/common/snitch_cluster_cfg.h.tpl | 2 - .../sw/runtime/common/snitch_cluster_memory.c | 2 - .../sw/runtime/common/snitch_cluster_memory.h | 9 +- util/lint/waiver.verible | 10 +- 18 files changed, 2302 insertions(+), 18049 deletions(-) delete mode 100644 hw/snitch_cluster/src/snitch_cluster_peripheral/Makefile create mode 100644 sw/snRuntime/src/perf_cnt.c diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index 6337ace3c2..023c20fd80 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -20,8 +20,6 @@ jobs: with: paths: | ./hw - exclude_paths: | - ./hw/future/test github_token: ${{ secrets.GITHUB_TOKEN }} fail_on_error: true reviewdog_reporter: github-check @@ -39,22 +37,34 @@ jobs: uses: pulp-platform/pulp-actions/bender-vendor-up-to-date@v2.1.0 ###################### - # Opcodes Up-to-Date # + # Sources Up-to-Date # ###################### - check-opcodes: - name: Check Opcodes Up-to-Date - runs-on: ubuntu-latest + sources-up-to-date: + name: Check Sources Up-to-Date + runs-on: ubuntu-22.04 + container: + image: ghcr.io/pulp-platform/snitch_cluster:main steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 with: submodules: true - - name: Update opcodes and diff + - name: Generate opcodes run: | ./util/generate-opcodes.sh + - name: Generate RTL sources + working-directory: target/snitch_cluster + run: | + make rtl + # For some reason, the checkout is done by a different user, + # than that running `git diff` (root, possibly due to Docker). + # So we need to set the repository as a safe directory. + - name: Git config safe.directory + run: | + git config --global --add safe.directory $GITHUB_WORKSPACE - name: Diff porcelain uses: mmontes11/diff-porcelain@v0.0.1 with: - message: Found differences, please update all opcode + message: Found differences, please update all sources ################# # Check License # diff --git a/hw/snitch_cluster/src/snitch_cluster.sv b/hw/snitch_cluster/src/snitch_cluster.sv index 30d72b9e15..9d68831f37 100644 --- a/hw/snitch_cluster/src/snitch_cluster.sv +++ b/hw/snitch_cluster/src/snitch_cluster.sv @@ -510,9 +510,9 @@ module snitch_cluster tcdm_req_t [NrTCDMPortsCores-1:0] tcdm_req; tcdm_rsp_t [NrTCDMPortsCores-1:0] tcdm_rsp; - core_events_t [NrCores-1:0] core_events; - tcdm_events_t tcdm_events; - dma_events_t dma_events; + core_events_t [NrCores-1:0] core_events; + tcdm_events_t tcdm_events; + dma_events_t [DMANumChannels-1:0] dma_events; snitch_icache_pkg::icache_events_t [NrCores-1:0] icache_events; // 4. Memory Subsystem (Core side). @@ -959,7 +959,7 @@ module snitch_cluster assign wide_axi_mst_req[SDMAMst + j] = axi_dma_req[j]; assign axi_dma_res[j] = wide_axi_mst_rsp[SDMAMst + j]; end - assign dma_events = dma_core_events[0]; // Only first channel is tracked + assign dma_events = dma_core_events; end end @@ -1237,12 +1237,12 @@ module snitch_cluster ); snitch_cluster_peripheral #( - .AddrWidth (PhysicalAddrWidth), .reg_req_t (reg_req_t), .reg_rsp_t (reg_rsp_t), .tcdm_events_t (tcdm_events_t), .dma_events_t (dma_events_t), - .NrCores (NrCores) + .NrCores (NrCores), + .DMANumChannels (DMANumChannels) ) i_snitch_cluster_peripheral ( .clk_i, .rst_ni, @@ -1250,7 +1250,6 @@ module snitch_cluster .reg_rsp_o (reg_rsp), .icache_prefetch_enable_o (icache_prefetch_enable), .cl_clint_o (cl_interrupt), - .cluster_hart_base_id_i (hart_base_id_i), .core_events_i (core_events), .tcdm_events_i (tcdm_events), .dma_events_i (dma_events), diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/Makefile b/hw/snitch_cluster/src/snitch_cluster_peripheral/Makefile deleted file mode 100644 index 436d5f578f..0000000000 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright 2021 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Noah Huetter - -REGTOOL=../../../../../util/regtool.py -PYTHON3=$(shell which python) -CLANG_FORMAT=$(shell which clang-format-12.0.1) - -SCHEMA=snitch_cluster_peripheral_reg.hjson - -PKG=snitch_cluster_peripheral_reg_pkg.sv -TOP=snitch_cluster_peripheral_reg_top.sv -CDEF=../../../../../sw/snRuntime/include/snitch_cluster_peripheral.h - -all: $(PKG) $(TOP) $(CDEF) - -$(PKG): $(SCHEMA) - $(PYTHON3) $(REGTOOL) -r -t $(dir $@) $< -$(TOP): $(SCHEMA) - $(PYTHON3) $(REGTOOL) -r -t $(dir $@) $< - -%.h: $(SCHEMA) - $(PYTHON3) $(REGTOOL) -D -o $@ $< - $(CLANG_FORMAT) -i $@ diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv index 998a1dabae..d2e5ff319c 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv @@ -10,16 +10,15 @@ module snitch_cluster_peripheral import snitch_pkg::*; import snitch_cluster_peripheral_reg_pkg::*; #( - parameter int unsigned AddrWidth = 0, + // Nr of cores in the cluster + parameter int unsigned NrCores = 0, + // Nr of DMA channels + parameter int unsigned DMANumChannels = 0, parameter int unsigned DMADataWidth = 0, parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter type tcdm_events_t = logic, - parameter type dma_events_t = logic, - // Nr of course in the cluster - parameter logic [31:0] NrCores = 0, - /// Derived parameter *Do not override* - parameter type addr_t = logic [AddrWidth-1:0] + parameter type tcdm_events_t = logic, + parameter type dma_events_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -29,16 +28,15 @@ module snitch_cluster_peripheral output logic icache_prefetch_enable_o, output logic [NrCores-1:0] cl_clint_o, - input logic [9:0] cluster_hart_base_id_i, - input core_events_t [NrCores-1:0] core_events_i, - input tcdm_events_t tcdm_events_i, - input dma_events_t dma_events_i, + input core_events_t [NrCores-1:0] core_events_i, + input tcdm_events_t tcdm_events_i, + input dma_events_t [DMANumChannels-1:0] dma_events_i, input snitch_icache_pkg::icache_events_t [NrCores-1:0] icache_events_i ); // Pipeline register to ease timing. tcdm_events_t tcdm_events_q; - dma_events_t dma_events_q; + dma_events_t [DMANumChannels-1:0] dma_events_q; snitch_icache_pkg::icache_events_t [NrCores-1:0] icache_events_q; `FF(tcdm_events_q, tcdm_events_i, '0) `FF(dma_events_q, dma_events_i, '0) @@ -60,7 +58,59 @@ module snitch_cluster_peripheral .hw2reg (hw2reg) ); - logic [NumPerfCounters-1:0][47:0] perf_counter_d, perf_counter_q; + // As defined in the `.hjson` file. Unfortunately, + // The regtool does not generate enums for SV, + // only for C. So we have to define them here. + typedef enum logic[4:0] { + Cycle = 5'd0, + TcdmAccessed = 5'd1, + TcdmCongested = 5'd2, + IssueFpu = 5'd3, + IssueFpuSeq = 5'd4, + IssueCoreToFpu = 5'd5, + RetiredInstr = 5'd6, + RetiredLoad = 5'd7, + RetiredI = 5'd8, + RetiredAcc = 5'd9, + DmaAwStall = 5'd10, + DmaArStall = 5'd11, + DmaRStall = 5'd12, + DmaWStall = 5'd13, + DmaBufWStall = 5'd14, + DmaBufRStall = 5'd15, + DmaAwDone = 5'd16, + DmaAwBw = 5'd17, + DmaArDone = 5'd18, + DmaArBw = 5'd19, + DmaRDone = 5'd20, + DmaRBw = 5'd21, + DmaWDone = 5'd22, + DmaWBw = 5'd23, + DmaBDone = 5'd24, + DmaBusy = 5'd25, + IcacheMiss = 5'd26, + IcacheHit = 5'd27, + IcachePrefetch = 5'd28, + IcacheDoubleHit = 5'd29, + IcacheStall = 5'd30, + NumMetrics = 5'd31 + } perf_metrics_e; + + // The metrics that should be tracked immediately after reset. + localparam int unsigned NumPerfMetricRstValues = 7; + localparam perf_metrics_e PerfMetricRstValues[NumPerfMetricRstValues] = '{ + Cycle, + RetiredInstr, + TcdmAccessed, + IcacheMiss, + IcacheHit, + IcachePrefetch, + IcacheStall + }; + + logic [NumPerfCounters-1:0][47:0] perf_cnt_q, perf_cnt_d; + perf_metrics_e [NumPerfCounters-1:0] perf_metrics_q, perf_metrics_d; + logic [NumPerfCounters-1:0][$clog2(NrCores)-1:0] perf_hart_sel_q, perf_hart_sel_d; logic [31:0] cl_clint_d, cl_clint_q; // Wake-up logic: Bits in cl_clint_q can be set/cleared with writes to @@ -81,160 +131,83 @@ module snitch_cluster_peripheral // Continuously assign the perf values. for (genvar i = 0; i < NumPerfCounters; i++) begin : gen_perf_assign - assign hw2reg.perf_counter[i].d = perf_counter_q[i]; + assign hw2reg.perf_cnt[i].d = perf_cnt_q[i]; + assign hw2reg.perf_cnt_sel[i].metric.d = perf_metrics_q[i]; + assign hw2reg.perf_cnt_sel[i].hart.d = perf_hart_sel_q[i]; end - // The hardware barrier is external and always reads `0`. - assign hw2reg.hw_barrier.d = 0; - always_comb begin - perf_counter_d = perf_counter_q; + perf_cnt_d = perf_cnt_q; + perf_metrics_d = perf_metrics_q; + perf_hart_sel_d = perf_hart_sel_q; for (int i = 0; i < NumPerfCounters; i++) begin automatic core_events_t sel_core_events; - sel_core_events = core_events_i[reg2hw.hart_select[i].q[$clog2(NrCores):0]]; - // Cycle - if (reg2hw.perf_counter_enable[i].cycle.q) begin - perf_counter_d[i]++; - end - // TCDM Accessed - else if (reg2hw.perf_counter_enable[i].tcdm_accessed.q) begin - perf_counter_d[i] = perf_counter_d[i] + tcdm_events_q.inc_accessed; - end - // TCDM Congested - else if (reg2hw.perf_counter_enable[i].tcdm_congested.q) begin - perf_counter_d[i] = perf_counter_d[i] + tcdm_events_q.inc_congested; - end - // Per-hart performance counter. - // Issue FPU - else if (reg2hw.perf_counter_enable[i].issue_fpu.q) begin - perf_counter_d[i] = perf_counter_d[i] + sel_core_events.issue_fpu; - end - // Issue FPU Sequencer - else if (reg2hw.perf_counter_enable[i].issue_fpu_seq.q) begin - perf_counter_d[i] = perf_counter_d[i] + sel_core_events.issue_fpu_seq; - end - // Issue Core to FPU - else if (reg2hw.perf_counter_enable[i].issue_core_to_fpu.q) begin - perf_counter_d[i] = perf_counter_d[i] + sel_core_events.issue_core_to_fpu; - end - // Retired instructions - else if (reg2hw.perf_counter_enable[i].retired_instr.q) begin - perf_counter_d[i] = perf_counter_d[i] + sel_core_events.retired_instr; - end - // Retired load instructions - else if (reg2hw.perf_counter_enable[i].retired_load.q) begin - perf_counter_d[i] = perf_counter_d[i] + sel_core_events.retired_load; - end - // Retired base instructions - else if (reg2hw.perf_counter_enable[i].retired_i.q) begin - perf_counter_d[i] = perf_counter_d[i] + sel_core_events.retired_i; - end - // Retired offloaded instructions - else if (reg2hw.perf_counter_enable[i].retired_acc.q) begin - perf_counter_d[i] = perf_counter_d[i] + sel_core_events.retired_acc; - end - // DMA AW stall - else if (reg2hw.perf_counter_enable[i].dma_aw_stall.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.aw_stall; - end - // DMA AR stall - else if (reg2hw.perf_counter_enable[i].dma_ar_stall.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.ar_stall; - end - // DMA R stall - else if (reg2hw.perf_counter_enable[i].dma_r_stall.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.r_stall; - end - // DMA W stall - else if (reg2hw.perf_counter_enable[i].dma_w_stall.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.w_stall; - end - // DMA BUF W stall - else if (reg2hw.perf_counter_enable[i].dma_buf_w_stall.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.buf_w_stall; - end - // DMA BUF R stall - else if (reg2hw.perf_counter_enable[i].dma_buf_r_stall.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.buf_r_stall; - end - // DMA AW done - else if (reg2hw.perf_counter_enable[i].dma_aw_done.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.aw_done; - end - // DMA AW BW - else if (reg2hw.perf_counter_enable[i].dma_aw_bw.q && - dma_events_q.aw_done) begin - perf_counter_d[i] = perf_counter_d[i] + - ((dma_events_q.aw_len + 1) << (dma_events_q.aw_size)); - end - // DMA AR done - else if (reg2hw.perf_counter_enable[i].dma_ar_done.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.ar_done; - end - // DMA AR BW - else if (reg2hw.perf_counter_enable[i].dma_ar_bw.q && - dma_events_q.ar_done) begin - perf_counter_d[i] = perf_counter_d[i] + - ((dma_events_q.ar_len + 1) << (dma_events_q.ar_size)); - end - // DMA R done - else if (reg2hw.perf_counter_enable[i].dma_r_done.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.r_done; - end - // DMA R BW - else if (reg2hw.perf_counter_enable[i].dma_r_bw.q && - dma_events_q.r_done) begin - perf_counter_d[i] = perf_counter_d[i] + DMADataWidth/8; - end - // DMA W done - else if (reg2hw.perf_counter_enable[i].dma_w_done.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.w_done; - end - // DMA W BW - else if (reg2hw.perf_counter_enable[i].dma_w_bw.q && - dma_events_q.w_done) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.num_bytes_written; - end - // DMA B done - else if (reg2hw.perf_counter_enable[i].dma_b_done.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.b_done; - end - // DMA busy - else if (reg2hw.perf_counter_enable[i].dma_busy.q) begin - perf_counter_d[i] = perf_counter_d[i] + dma_events_q.dma_busy; - end - // icache miss - else if (reg2hw.perf_counter_enable[i].icache_miss.q) begin - perf_counter_d[i] = perf_counter_d[i] + - icache_events_q[reg2hw.hart_select[i].q].l0_miss; - end - // icache hit - else if (reg2hw.perf_counter_enable[i].icache_hit.q) begin - perf_counter_d[i] = perf_counter_d[i] + - icache_events_q[reg2hw.hart_select[i].q].l0_hit; - end - // icache prefetch - else if (reg2hw.perf_counter_enable[i].icache_prefetch.q) begin - perf_counter_d[i] = perf_counter_d[i] + - icache_events_q[reg2hw.hart_select[i].q].l0_prefetch; - end - // icache double hit - else if (reg2hw.perf_counter_enable[i].icache_double_hit.q) begin - perf_counter_d[i] = perf_counter_d[i] + - icache_events_q[reg2hw.hart_select[i].q].l0_double_hit; - end - // icache stall - else if (reg2hw.perf_counter_enable[i].icache_stall.q) begin - perf_counter_d[i] = perf_counter_d[i] + - icache_events_q[reg2hw.hart_select[i].q].l0_stall; - end - // Reset performance counter. - if (reg2hw.perf_counter[i].qe) begin - perf_counter_d[i] = reg2hw.perf_counter[i].q; + automatic dma_events_t sel_dma_events; + automatic logic [$clog2(NrCores)-1:0] hart_select; + hart_select = perf_hart_sel_q[i][$clog2(NrCores)-1:0]; + sel_core_events = core_events_i[hart_select]; + sel_dma_events = dma_events_q[hart_select]; + unique case (perf_metrics_q[i]) + Cycle: perf_cnt_d[i] += 1; + TcdmAccessed: perf_cnt_d[i] += tcdm_events_q.inc_accessed; + TcdmCongested: perf_cnt_d[i] += tcdm_events_q.inc_congested; + IssueFpu: perf_cnt_d[i] += sel_core_events.issue_fpu; + IssueFpuSeq: perf_cnt_d[i] += sel_core_events.issue_fpu_seq; + IssueCoreToFpu: perf_cnt_d[i] += sel_core_events.issue_core_to_fpu; + RetiredInstr: perf_cnt_d[i] += sel_core_events.retired_instr; + RetiredLoad: perf_cnt_d[i] += sel_core_events.retired_load; + RetiredI: perf_cnt_d[i] += sel_core_events.retired_i; + RetiredAcc: perf_cnt_d[i] += sel_core_events.retired_acc; + DmaAwStall: perf_cnt_d[i] += sel_dma_events.aw_stall; + DmaArStall: perf_cnt_d[i] += sel_dma_events.ar_stall; + DmaRStall: perf_cnt_d[i] += sel_dma_events.r_stall; + DmaWStall: perf_cnt_d[i] += sel_dma_events.w_stall; + DmaBufWStall: perf_cnt_d[i] += sel_dma_events.buf_w_stall; + DmaBufRStall: perf_cnt_d[i] += sel_dma_events.buf_r_stall; + DmaAwDone: perf_cnt_d[i] += sel_dma_events.aw_done; + DmaAwBw: perf_cnt_d[i] += ((sel_dma_events.aw_len + 1) << (sel_dma_events.aw_size)); + DmaArDone: perf_cnt_d[i] += sel_dma_events.ar_done; + DmaArBw: perf_cnt_d[i] += ((sel_dma_events.ar_len + 1) << (sel_dma_events.ar_size)); + DmaRDone: perf_cnt_d[i] += sel_dma_events.r_done; + DmaRBw: perf_cnt_d[i] += DMADataWidth/8; + DmaWDone: perf_cnt_d[i] += sel_dma_events.w_done; + DmaWBw: perf_cnt_d[i] += sel_dma_events.num_bytes_written; + DmaBDone: perf_cnt_d[i] += sel_dma_events.b_done; + DmaBusy: perf_cnt_d[i] += sel_dma_events.dma_busy; + IcacheMiss: perf_cnt_d[i] += icache_events_q[hart_select].l0_miss; + IcacheHit: perf_cnt_d[i] += icache_events_q[hart_select].l0_hit; + IcachePrefetch: perf_cnt_d[i] += icache_events_q[hart_select].l0_prefetch; + IcacheDoubleHit: perf_cnt_d[i] += icache_events_q[hart_select].l0_double_hit; + IcacheStall: perf_cnt_d[i] += icache_events_q[hart_select].l0_stall; + default:; + endcase + // Set performance metric. + if (reg2hw.perf_cnt_sel[i].metric.qe) begin + perf_metrics_d[i] = perf_metrics_e'(reg2hw.perf_cnt_sel[i].metric.q); + end + // Set hart select. + if (reg2hw.perf_cnt_sel[i].hart.qe) begin + perf_hart_sel_d[i] = reg2hw.perf_cnt_sel[i].hart.q; end end end - `FF(perf_counter_q, perf_counter_d, '0, clk_i, rst_ni) + // Performance counter FFs. + for (genvar i = 0; i < NumPerfCounters; i++) begin : gen_perf_cnt + `FFLARNC(perf_cnt_q[i], perf_cnt_d[i], + reg2hw.perf_cnt_en[i], reg2hw.perf_cnt[i].qe, '0, clk_i, rst_ni) + end + + // Set reset values for the metrics that should be tracked immediately after reset. + for (genvar i = 0; i < NumPerfCounters; i++) begin : gen_perf_metrics_assign + if (i < NumPerfMetricRstValues) begin : gen_perf_metrics_rst_value + `FF(perf_metrics_q[i], perf_metrics_d[i], PerfMetricRstValues[i], clk_i, rst_ni) + end else begin : gen_perf_metrics_default + `FF(perf_metrics_q[i], perf_metrics_d[i], Cycle, clk_i, rst_ni) + end + end + + // Use hart `0` as default. + `FF(perf_hart_sel_q, perf_hart_sel_d, 0, clk_i, rst_ni) endmodule diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson index e3a0c485c9..8831aa0892 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson @@ -16,335 +16,284 @@ { protocol: "reg_iface", direction: "device"} ] regwidth: 64, - registers: [{ + registers: [ + { multireg: { - name: "PERF_COUNTER_ENABLE", - desc: "Enable particular performance counter and start tracking.", + name: "PERF_CNT_EN", + desc: "Enable a particular performance counter to start tracking." swaccess: "rw", hwaccess: "hro", count: "NumPerfCounters", - cname: "performance_counter_enable", + cname: "perf_cnt_en", + compact: "false", fields: [{ bits: "0:0", - resval: "0", - name: "CYCLE", - desc: ''' - Cycle counter. Counts up as long as the cluster is powered. - ''' - }, - { - bits: "1:1", - resval: "0", - name: "TCDM_ACCESSED" - desc: ''' - Increased whenever the TCDM is accessed. Each individual access is tracked, - so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM, - so it doesn't matter whether the cores or for example the SSR hardware accesses - the TCDM. _This is a cluster-global signal._ - ''' - }, - { - bits: "2:2", - resval: "0", - name: "TCDM_CONGESTED" - desc: ''' - Incremented whenever an access towards the TCDM is made but the arbitration - logic didn't grant the access (due to congestion). It's strictly less than TCDM_ACCESSED. - _This is a cluster-global signal._ - ''' - }, - { - bits: "3:3", - resval: "0", - name: "ISSUE_FPU" - desc: ''' - Operations performed in the FPU. Includes both operations initiated by the - sequencer and by the core. When the Xfrep extension is available, this counter is - equivalent to ISSUE_FPU_SEQ (see description of ISSUE_FPU_SEQ). If the Xfrep extension - is not supported, then it is equivalent to ISSUE_CORE_TO_FPU. _This is a hart-local signal._ - ''' - }, - { - bits: "4:4", - resval: "0", - name: "ISSUE_FPU_SEQ" - desc: ''' - Incremented whenever the FPU Sequencer issues an FPU instruction. - Might not be available if the hardware doesn't support FREP. - Note that all FP instructions offloaded by the core to the FPU are routed - through the sequencer (although not necessarily buffered) and thus are also counted. - The instructions issued independently by the FPU sequencer could thus be - calculated as ISSUE_FPU_SEQ_PROPER = ISSUE_FPU_SEQ - ISSUE_CORE_TO_FPU. - _This is a hart-local signal._ - ''' - }, - { - bits: "5:5", - resval: "0", - name: "ISSUE_CORE_TO_FPU" - desc: '''Incremented whenever the core issues an FPU instruction. - _This is a hart-local signal._''' - }, - { - bits: "6:6", - resval: "0", - name: "RETIRED_INSTR" - desc: ''' - Instructions retired by the core, both offloaded and not. Does not - count instructions issued independently by the FPU sequencer. - _This is a hart-local signal._ - ''' - }, - { - bits: "7:7", - resval: "0", - name: "RETIRED_LOAD" - desc: ''' - Load instructions retired by the core. _This is a hart-local signal._ - ''' - }, - { - bits: "8:8", - resval: "0", - name: "RETIRED_I" - desc: ''' - Base instructions retired by the core. _This is a hart-local signal._ - ''' - }, - { - bits: "9:9", - resval: "0", - name: "RETIRED_ACC" - desc: ''' - Offloaded instructions retired by the core. _This is a hart-local signal._ - ''' - }, - { - bits: "10:10", - resval: "0", - name: "DMA_AW_STALL" - desc: ''' - Incremented whenever aw_valid = 1 but aw_ready = 0. - _This is a DMA-local signal_ - ''' - }, - { - bits: "11:11", - resval: "0", - name: "DMA_AR_STALL" - desc: ''' - Incremented whenever ar_valid = 1 but ar_ready = 0. - _This is a DMA-local signal_ - ''' - }, - { - bits: "12:12", - resval: "0", - name: "DMA_R_STALL" - desc: ''' - Incremented whenever r_ready = 1 but r_valid = 0. - _This is a DMA-local signal_ - ''' - }, - { - bits: "13:13", - resval: "0", - name: "DMA_W_STALL" - desc: ''' - Incremented whenever w_valid = 1 but w_ready = 0. - _This is a DMA-local signal_ - ''' - }, - { - bits: "14:14", - resval: "0", - name: "DMA_BUF_W_STALL" - desc: ''' - Incremented whenever w_ready = 1 but w_valid = 0. - _This is a DMA-local signal_ - ''' - }, - { - bits: "15:15", - resval: "0", - name: "DMA_BUF_R_STALL" - desc: ''' - Incremented whenever r_valid = 1 but r_ready = 0. - _This is a DMA-local signal_ - ''' - }, - { - bits: "16:16", - resval: "0", - name: "DMA_AW_DONE" - desc: ''' - Incremented whenever AW handshake occurs. - _This is a DMA-local signal_ - ''' - }, - { - bits: "17:17", - resval: "0", - name: "DMA_AW_BW" - desc: ''' - Whenever AW handshake occurs, the counter is incremented - by the number of bytes transfered for this transaction - _This is a DMA-local signal_ - ''' - }, - { - bits: "18:18", - resval: "0", - name: "DMA_AR_DONE" - desc: ''' - Incremented whenever AR handshake occurs. - _This is a DMA-local signal_ - ''' - }, - { - bits: "19:19", - resval: "0", - name: "DMA_AR_BW" - desc: ''' - Whenever AR handshake occurs, the counter is incremented - by the number of bytes transfered for this transaction - _This is a DMA-local signal_ - ''' - }, - { - bits: "20:20", - resval: "0", - name: "DMA_R_DONE" - desc: ''' - Incremented whenever R handshake occurs. - _This is a DMA-local signal_ - ''' - }, - { - bits: "21:21", - resval: "0", - name: "DMA_R_BW" - desc: ''' - Whenever R handshake occurs, the counter is incremented - by the number of bytes transfered in this cycle - _This is a DMA-local signal_ - ''' - }, - { - bits: "22:22", - resval: "0", - name: "DMA_W_DONE" - desc: ''' - Incremented whenvever W handshake occurs. - _This is a DMA-local signal_ - ''' - }, - { - bits: "23:23", - resval: "0", - name: "DMA_W_BW" - desc: ''' - Whenever W handshake occurs, the counter is incremented - by the number of bytes transfered in this cycle - _This is a DMA-local signal_ - ''' - }, - { - bits: "24:24", - resval: "0", - name: "DMA_B_DONE" - desc: ''' - Incremented whenever B handshake occurs. - _This is a DMA-local signal_ - ''' - }, - { - bits: "25:25", - resval: "0", - name: "DMA_BUSY" - desc: ''' - Incremented whenever DMA is busy. - _This is a DMA-local signal_ - ''' - }, - { - bits: "26:26", - resval: "0", - name: "ICACHE_MISS" - desc: ''' - Incremented for instruction cache misses. - _This is a hart-local signal_ - ''' - }, - { - bits: "27:27", - resval: "0", - name: "ICACHE_HIT" - desc: ''' - Incremented for instruction cache hits. - _This is a hart-local signal_ - ''' - }, - { - bits: "28:28", - resval: "0", - name: "ICACHE_PREFETCH" - desc: ''' - Incremented for instruction cache prefetches. - _This is a hart-local signal_ - ''' - }, - { - bits: "29:29", - resval: "0", - name: "ICACHE_DOUBLE_HIT" - desc: ''' - Incremented for instruction cache double hit. - _This is a hart-local signal_ - ''' - }, - { - bits: "30:30", - resval: "0", - name: "ICACHE_STALL" - desc: ''' - Incremented for instruction cache stalls. - _This is a hart-local signal_ - ''' - }, - ] + resval: "1", + name: "ENABLE", + desc: "Enable a particular performance counter to start tracking." + }] } }, { multireg: { - name: "HART_SELECT", - desc: '''Select from which hart in the cluster, starting from `0`, - the event should be counted. For each performance counter - the cores can be selected individually. If a hart greater - than the clusters total hart size is selected the selection - will wrap and the hart corresponding to `hart_select % total_harts_in_cluster` - will be selected.''' + name: "PERF_CNT_SEL", + desc: "Select the metric that is tracked for each performance counter.", swaccess: "rw", - hwaccess: "hro", + hwaccess: "hrw", count: "NumPerfCounters", - cname: "hart_select", - compact: "false", + cname: "perf_cnt_sel", + hwext: "true", + hwqe: "true", fields: [{ - bits: "9:0", - name: "HART_SELECT", - desc: "Select source of per-hart performance counter" + bits: "15:0", + name: "HART", + desc: '''Select from which hart in the cluster, starting from `0`, + the event should be counted. For each performance counter + the cores can be selected individually. If a hart greater + than the cluster's total hart size is selected the selection + will wrap and the hart corresponding to `hart_select % total_harts_in_cluster` + will be selected.''' + }, + { + bits: "31:16", + name: "METRIC", + desc: "Select the metric that is tracked for each performance counter", + enum: [{ + value: "0", + name: "CYCLE", + desc: "Cycle counter. Counts up as long as the cluster is powered." + }, + { + value: "1", + name: "TCDM_ACCESSED", + desc: ''' + Increased whenever the TCDM is accessed. Each individual access is tracked, + so if `n` cores access the TCDM, `n` will be added. Accesses are tracked at the TCDM, + so it doesn't matter whether the cores or for example the SSR hardware accesses + the TCDM. _This is a cluster-global signal._''' + }, + { + value: "2", + name: "TCDM_CONGESTED", + desc: ''' + Incremented whenever an access towards the TCDM is made but the arbitration + logic didn't grant the access (due to congestion). It's strictly less than TCDM_ACCESSED. + _This is a cluster-global signal._''' + }, + { + value: "3", + name: "ISSUE_FPU", + desc: ''' + Operations performed in the FPU. Includes both operations initiated by the + sequencer and by the core. When the Xfrep extension is available, this counter is + equivalent to ISSUE_FPU_SEQ (see description of ISSUE_FPU_SEQ). If the Xfrep extension + is not supported, then it is equivalent to ISSUE_CORE_TO_FPU. _This is a hart-local signal._''' + }, + { + value: "4", + name: "ISSUE_FPU_SEQ", + desc: ''' + Incremented whenever the FPU Sequencer issues an FPU instruction. + Might not be available if the hardware doesn't support FREP. + Note that all FP instructions offloaded by the core to the FPU are routed + through the sequencer (although not necessarily buffered) and thus are also counted. + The instructions issued independently by the FPU sequencer could thus be + calculated as ISSUE_FPU_SEQ_PROPER = ISSUE_FPU_SEQ - ISSUE_CORE_TO_FPU. + _This is a hart-local signal._''' + }, + { + value: "5", + name: "ISSUE_CORE_TO_FPU", + desc: '''Incremented whenever the core issues an FPU instruction. + _This is a hart-local signal._''' + }, + { + value: "6", + name: "RETIRED_INSTR", + desc: ''' + Instructions retired by the core, both offloaded and not. Does not + count instructions issued independently by the FPU sequencer. + _This is a hart-local signal._''' + }, + { + value: "7", + name: "RETIRED_LOAD", + desc: '''Load instructions retired by the core. _This is a hart-local signal._''' + }, + { + value: "8", + name: "RETIRED_I", + desc: '''Base instructions retired by the core. _This is a hart-local signal._''' + }, + { + value: "9", + name: "RETIRED_ACC", + desc: '''Offloaded instructions retired by the core. _This is a hart-local signal._''' + }, + { + value: "10", + name: "DMA_AW_STALL", + desc: ''' + Incremented whenever aw_valid = 1 but aw_ready = 0. + _This is a DMA-local signal_''' + }, + { + value: "11", + name: "DMA_AR_STALL", + desc: ''' + Incremented whenever ar_valid = 1 but ar_ready = 0. + _This is a DMA-local signal_''' + }, + { + value: "12", + name: "DMA_R_STALL", + desc: ''' + Incremented whenever r_ready = 1 but r_valid = 0. + _This is a DMA-local signal_''' + }, + { + value: "13", + name: "DMA_W_STALL", + desc: ''' + Incremented whenever w_valid = 1 but w_ready = 0. + _This is a DMA-local signal_''' + }, + { + value: "14", + name: "DMA_BUF_W_STALL", + desc: ''' + Incremented whenever w_ready = 1 but w_valid = 0. + _This is a DMA-local signal_''' + }, + { + value: "15", + name: "DMA_BUF_R_STALL", + desc: ''' + Incremented whenever r_valid = 1 but r_ready = 0. + _This is a DMA-local signal_''' + }, + { + value: "16", + name: "DMA_AW_DONE", + desc: ''' + Incremented whenever AW handshake occurs. + _This is a DMA-local signal_''' + }, + { + value: "17", + name: "DMA_AW_BW", + desc: ''' + Whenever AW handshake occurs, the counter is incremented + by the number of bytes transfered for this transaction + _This is a DMA-local signal_''' + }, + { + value: "18", + name: "DMA_AR_DONE", + desc: ''' + Incremented whenever AR handshake occurs. + _This is a DMA-local signal_''' + }, + { + value: "19", + name: "DMA_AR_BW", + desc: ''' + Whenever AR handshake occurs, the counter is incremented + by the number of bytes transfered for this transaction + _This is a DMA-local signal_''' + }, + { + value: "20", + name: "DMA_R_DONE", + desc: ''' + Incremented whenever R handshake occurs. + _This is a DMA-local signal_''' + }, + { + value: "21", + name: "DMA_R_BW", + desc: ''' + Whenever R handshake occurs, the counter is incremented + by the number of bytes transfered in this cycle + _This is a DMA-local signal_''' + }, + { + value: "22", + name: "DMA_W_DONE", + desc: ''' + Incremented whenvever W handshake occurs. + _This is a DMA-local signal_''' + }, + { + value: "23", + name: "DMA_W_BW", + desc: ''' + Whenever W handshake occurs, the counter is incremented + by the number of bytes transfered in this cycle + _This is a DMA-local signal_''' + }, + { + value: "24", + name: "DMA_B_DONE", + desc: ''' + Incremented whenever B handshake occurs. + _This is a DMA-local signal_''' + }, + { + value: "25", + name: "DMA_BUSY", + desc: ''' + Incremented whenever DMA is busy. + _This is a DMA-local signal_''' + }, + { + value: "26", + name: "ICACHE_MISS", + desc: ''' + Incremented for instruction cache misses. + _This is a hart-local signal_''' + }, + { + value: "27", + name: "ICACHE_HIT", + desc: ''' + Incremented for instruction cache hits. + _This is a hart-local signal_''' + }, + { + value: "28", + name: "ICACHE_PREFETCH", + desc: ''' + Incremented for instruction cache prefetches. + _This is a hart-local signal_''' + }, + { + value: "29", + name: "ICACHE_DOUBLE_HIT", + desc: ''' + Incremented for instruction cache double hit. + _This is a hart-local signal_''' + }, + { + value: "30", + name: "ICACHE_STALL", + desc: ''' + Incremented for instruction cache stalls. + _This is a hart-local signal_''' + }, + ] }] } - } + }, { multireg: { - name: "PERF_COUNTER", - desc: '''Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending on what - performance metric you would like to track.''' + name: "PERF_CNT", + desc: '''Performance counter. Set corresponding PERF_CNT_SEL register depending on what + performance metric and hart you would like to track.''' swaccess: "rw", hwaccess: "hrw", count: "NumPerfCounters", - cname: "performance_counter", + cname: "perf_cnt", hwext: "true", hwqe: "true", fields: [{ @@ -386,20 +335,6 @@ desc: "Clear cluster-local interrupt of hart i" }] }, - { - name: "HW_BARRIER", - desc: '''Hardware barrier register. Loads to this register will block until all cores have - performed the load. At this stage we know that they reached the same point in the control flow, - i.e., the cores are synchronized.''' - swaccess: "ro", - hwaccess: "hrw", - hwext: "true", - fields: [{ - bits: "31:0", - name: "HW_BARRIER", - desc: "Hardware barrier register." - }] - }, { name: "ICACHE_PREFETCH_ENABLE", desc: '''Controls prefetching of the instruction cache.''' diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv index ff5616f7dd..3795d8013b 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv @@ -17,109 +17,24 @@ package snitch_cluster_peripheral_reg_pkg; //////////////////////////// typedef struct packed { - struct packed { - logic q; - } cycle; - struct packed { - logic q; - } tcdm_accessed; - struct packed { - logic q; - } tcdm_congested; - struct packed { - logic q; - } issue_fpu; - struct packed { - logic q; - } issue_fpu_seq; - struct packed { - logic q; - } issue_core_to_fpu; - struct packed { - logic q; - } retired_instr; - struct packed { - logic q; - } retired_load; - struct packed { - logic q; - } retired_i; - struct packed { - logic q; - } retired_acc; - struct packed { - logic q; - } dma_aw_stall; - struct packed { - logic q; - } dma_ar_stall; - struct packed { - logic q; - } dma_r_stall; - struct packed { - logic q; - } dma_w_stall; - struct packed { - logic q; - } dma_buf_w_stall; - struct packed { - logic q; - } dma_buf_r_stall; - struct packed { - logic q; - } dma_aw_done; - struct packed { - logic q; - } dma_aw_bw; - struct packed { - logic q; - } dma_ar_done; - struct packed { - logic q; - } dma_ar_bw; - struct packed { - logic q; - } dma_r_done; - struct packed { - logic q; - } dma_r_bw; - struct packed { - logic q; - } dma_w_done; - struct packed { - logic q; - } dma_w_bw; - struct packed { - logic q; - } dma_b_done; - struct packed { - logic q; - } dma_busy; - struct packed { - logic q; - } icache_miss; - struct packed { - logic q; - } icache_hit; - struct packed { - logic q; - } icache_prefetch; - struct packed { - logic q; - } icache_double_hit; - struct packed { - logic q; - } icache_stall; - } snitch_cluster_peripheral_reg2hw_perf_counter_enable_mreg_t; + logic q; + } snitch_cluster_peripheral_reg2hw_perf_cnt_en_mreg_t; typedef struct packed { - logic [9:0] q; - } snitch_cluster_peripheral_reg2hw_hart_select_mreg_t; + struct packed { + logic [15:0] q; + logic qe; + } hart; + struct packed { + logic [15:0] q; + logic qe; + } metric; + } snitch_cluster_peripheral_reg2hw_perf_cnt_sel_mreg_t; typedef struct packed { logic [47:0] q; logic qe; - } snitch_cluster_peripheral_reg2hw_perf_counter_mreg_t; + } snitch_cluster_peripheral_reg2hw_perf_cnt_mreg_t; typedef struct packed { logic [31:0] q; @@ -131,224 +46,236 @@ package snitch_cluster_peripheral_reg_pkg; logic qe; } snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t; - typedef struct packed { - logic [31:0] q; - } snitch_cluster_peripheral_reg2hw_hw_barrier_reg_t; - typedef struct packed { logic q; } snitch_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t; typedef struct packed { - logic [47:0] d; - } snitch_cluster_peripheral_hw2reg_perf_counter_mreg_t; + struct packed { + logic [15:0] d; + } hart; + struct packed { + logic [15:0] d; + } metric; + } snitch_cluster_peripheral_hw2reg_perf_cnt_sel_mreg_t; typedef struct packed { - logic [31:0] d; - } snitch_cluster_peripheral_hw2reg_hw_barrier_reg_t; + logic [47:0] d; + } snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t; // Register -> HW type typedef struct packed { - snitch_cluster_peripheral_reg2hw_perf_counter_enable_mreg_t [15:0] perf_counter_enable; // [1538:1043] - snitch_cluster_peripheral_reg2hw_hart_select_mreg_t [15:0] hart_select; // [1042:883] - snitch_cluster_peripheral_reg2hw_perf_counter_mreg_t [15:0] perf_counter; // [882:99] - snitch_cluster_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [98:66] - snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [65:33] - snitch_cluster_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [32:1] + snitch_cluster_peripheral_reg2hw_perf_cnt_en_mreg_t [15:0] perf_cnt_en; // [1410:1395] + snitch_cluster_peripheral_reg2hw_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1394:851] + snitch_cluster_peripheral_reg2hw_perf_cnt_mreg_t [15:0] perf_cnt; // [850:67] + snitch_cluster_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [66:34] + snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [33:1] snitch_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [0:0] } snitch_cluster_peripheral_reg2hw_t; // HW -> register type typedef struct packed { - snitch_cluster_peripheral_hw2reg_perf_counter_mreg_t [15:0] perf_counter; // [799:32] - snitch_cluster_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [31:0] + snitch_cluster_peripheral_hw2reg_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1279:768] + snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t [15:0] perf_cnt; // [767:0] } snitch_cluster_peripheral_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_OFFSET = 9'h 0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_OFFSET = 9'h 8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_OFFSET = 9'h 10; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_OFFSET = 9'h 18; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_OFFSET = 9'h 20; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_OFFSET = 9'h 28; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_OFFSET = 9'h 30; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_OFFSET = 9'h 38; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_OFFSET = 9'h 40; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_OFFSET = 9'h 48; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_OFFSET = 9'h 50; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_OFFSET = 9'h 58; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_OFFSET = 9'h 60; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_OFFSET = 9'h 68; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_OFFSET = 9'h 70; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_OFFSET = 9'h 78; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0_OFFSET = 9'h 80; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1_OFFSET = 9'h 88; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2_OFFSET = 9'h 90; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3_OFFSET = 9'h 98; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4_OFFSET = 9'h a0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5_OFFSET = 9'h a8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6_OFFSET = 9'h b0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7_OFFSET = 9'h b8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8_OFFSET = 9'h c0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9_OFFSET = 9'h c8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10_OFFSET = 9'h d0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11_OFFSET = 9'h d8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12_OFFSET = 9'h e0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13_OFFSET = 9'h e8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14_OFFSET = 9'h f0; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15_OFFSET = 9'h f8; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_OFFSET = 9'h 100; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_OFFSET = 9'h 108; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_OFFSET = 9'h 110; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_OFFSET = 9'h 118; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_OFFSET = 9'h 120; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_OFFSET = 9'h 128; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_OFFSET = 9'h 130; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_OFFSET = 9'h 138; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_OFFSET = 9'h 140; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_OFFSET = 9'h 148; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_OFFSET = 9'h 150; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_OFFSET = 9'h 158; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_OFFSET = 9'h 160; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_OFFSET = 9'h 168; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_OFFSET = 9'h 170; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_OFFSET = 9'h 178; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_OFFSET = 9'h 0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1_OFFSET = 9'h 8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2_OFFSET = 9'h 10; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3_OFFSET = 9'h 18; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4_OFFSET = 9'h 20; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5_OFFSET = 9'h 28; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6_OFFSET = 9'h 30; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7_OFFSET = 9'h 38; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8_OFFSET = 9'h 40; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_OFFSET = 9'h c8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_OFFSET = 9'h d0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_OFFSET = 9'h d8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_OFFSET = 9'h e0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_OFFSET = 9'h e8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_OFFSET = 9'h f0; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_OFFSET = 9'h f8; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_OFFSET = 9'h 100; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_OFFSET = 9'h 108; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_OFFSET = 9'h 110; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_OFFSET = 9'h 118; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_OFFSET = 9'h 120; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_OFFSET = 9'h 128; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_OFFSET = 9'h 130; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_OFFSET = 9'h 138; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_OFFSET = 9'h 140; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_OFFSET = 9'h 148; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_OFFSET = 9'h 150; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_OFFSET = 9'h 158; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_OFFSET = 9'h 160; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET = 9'h 168; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET = 9'h 170; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET = 9'h 178; parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 9'h 180; parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 9'h 188; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET = 9'h 190; - parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 198; + parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 190; // Reset values for hwext registers and their fields - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_RESVAL = 48'h 0; - parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_RESVAL = 48'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_RESVAL = 32'h 0; + parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_RESVAL = 32'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_RESVAL = 48'h 0; + parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_RESVAL = 48'h 0; parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_RESVAL = 32'h 0; parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_RESVAL = 32'h 0; - parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_RESVAL = 32'h 0; // Register index typedef enum int { - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14, - SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14, - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15, SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET, SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR, - SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER, SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE } snitch_cluster_peripheral_id_e; // Register width information to check illegal writes - parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [52] = '{ - 4'b 1111, // index[ 0] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0 - 4'b 1111, // index[ 1] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1 - 4'b 1111, // index[ 2] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2 - 4'b 1111, // index[ 3] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3 - 4'b 1111, // index[ 4] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4 - 4'b 1111, // index[ 5] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5 - 4'b 1111, // index[ 6] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6 - 4'b 1111, // index[ 7] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7 - 4'b 1111, // index[ 8] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8 - 4'b 1111, // index[ 9] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9 - 4'b 1111, // index[10] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10 - 4'b 1111, // index[11] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11 - 4'b 1111, // index[12] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12 - 4'b 1111, // index[13] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13 - 4'b 1111, // index[14] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14 - 4'b 1111, // index[15] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15 - 4'b 0011, // index[16] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0 - 4'b 0011, // index[17] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1 - 4'b 0011, // index[18] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2 - 4'b 0011, // index[19] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3 - 4'b 0011, // index[20] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4 - 4'b 0011, // index[21] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5 - 4'b 0011, // index[22] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6 - 4'b 0011, // index[23] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7 - 4'b 0011, // index[24] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8 - 4'b 0011, // index[25] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9 - 4'b 0011, // index[26] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10 - 4'b 0011, // index[27] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11 - 4'b 0011, // index[28] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12 - 4'b 0011, // index[29] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13 - 4'b 0011, // index[30] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14 - 4'b 0011, // index[31] SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15 - 4'b 1111, // index[32] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0 - 4'b 1111, // index[33] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1 - 4'b 1111, // index[34] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2 - 4'b 1111, // index[35] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3 - 4'b 1111, // index[36] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4 - 4'b 1111, // index[37] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5 - 4'b 1111, // index[38] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6 - 4'b 1111, // index[39] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7 - 4'b 1111, // index[40] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8 - 4'b 1111, // index[41] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9 - 4'b 1111, // index[42] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10 - 4'b 1111, // index[43] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11 - 4'b 1111, // index[44] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12 - 4'b 1111, // index[45] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13 - 4'b 1111, // index[46] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14 - 4'b 1111, // index[47] SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15 + parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [51] = '{ + 4'b 0001, // index[ 0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0 + 4'b 0001, // index[ 1] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1 + 4'b 0001, // index[ 2] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2 + 4'b 0001, // index[ 3] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3 + 4'b 0001, // index[ 4] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4 + 4'b 0001, // index[ 5] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5 + 4'b 0001, // index[ 6] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6 + 4'b 0001, // index[ 7] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7 + 4'b 0001, // index[ 8] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8 + 4'b 0001, // index[ 9] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9 + 4'b 0001, // index[10] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10 + 4'b 0001, // index[11] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11 + 4'b 0001, // index[12] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12 + 4'b 0001, // index[13] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13 + 4'b 0001, // index[14] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14 + 4'b 0001, // index[15] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15 + 4'b 1111, // index[16] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0 + 4'b 1111, // index[17] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1 + 4'b 1111, // index[18] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2 + 4'b 1111, // index[19] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3 + 4'b 1111, // index[20] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4 + 4'b 1111, // index[21] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5 + 4'b 1111, // index[22] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6 + 4'b 1111, // index[23] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7 + 4'b 1111, // index[24] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8 + 4'b 1111, // index[25] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9 + 4'b 1111, // index[26] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10 + 4'b 1111, // index[27] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11 + 4'b 1111, // index[28] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12 + 4'b 1111, // index[29] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13 + 4'b 1111, // index[30] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14 + 4'b 1111, // index[31] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15 + 4'b 1111, // index[32] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0 + 4'b 1111, // index[33] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1 + 4'b 1111, // index[34] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2 + 4'b 1111, // index[35] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3 + 4'b 1111, // index[36] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4 + 4'b 1111, // index[37] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5 + 4'b 1111, // index[38] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6 + 4'b 1111, // index[39] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7 + 4'b 1111, // index[40] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8 + 4'b 1111, // index[41] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9 + 4'b 1111, // index[42] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10 + 4'b 1111, // index[43] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11 + 4'b 1111, // index[44] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12 + 4'b 1111, // index[45] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13 + 4'b 1111, // index[46] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14 + 4'b 1111, // index[47] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15 4'b 1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET 4'b 1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR - 4'b 1111, // index[50] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER - 4'b 0001 // index[51] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE + 4'b 0001 // index[50] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE }; endpackage diff --git a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv index ab8298e781..fb6cdb86d4 100644 --- a/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv +++ b/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv @@ -8,12 +8,12 @@ `include "common_cells/assertions.svh" module snitch_cluster_peripheral_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 9 + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 9 ) ( - input clk_i, - input rst_ni, + input logic clk_i, + input logic rst_ni, input reg_req_t reg_req_i, output reg_rsp_t reg_rsp_o, // To HW @@ -33,7 +33,7 @@ module snitch_cluster_peripheral_reg_top #( // register signals logic reg_we; logic reg_re; - logic [AW-1:0] reg_addr; + logic [BlockAw-1:0] reg_addr; logic [DW-1:0] reg_wdata; logic [DBW-1:0] reg_be; logic [DW-1:0] reg_rdata; @@ -54,7 +54,7 @@ module snitch_cluster_peripheral_reg_top #( assign reg_we = reg_intf_req.valid & reg_intf_req.write; assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; - assign reg_addr = reg_intf_req.addr; + assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; assign reg_wdata = reg_intf_req.wdata; assign reg_be = reg_intf_req.wstrb; assign reg_intf_rsp.rdata = reg_rdata; @@ -68,1632 +68,269 @@ module snitch_cluster_peripheral_reg_top #( // Define SW related signals // Format: __{wd|we|qs} // or _{wd|we|qs} if field == 1 or 0 - logic perf_counter_enable_0_cycle_0_qs; - logic perf_counter_enable_0_cycle_0_wd; - logic perf_counter_enable_0_cycle_0_we; - logic perf_counter_enable_0_tcdm_accessed_0_qs; - logic perf_counter_enable_0_tcdm_accessed_0_wd; - logic perf_counter_enable_0_tcdm_accessed_0_we; - logic perf_counter_enable_0_tcdm_congested_0_qs; - logic perf_counter_enable_0_tcdm_congested_0_wd; - logic perf_counter_enable_0_tcdm_congested_0_we; - logic perf_counter_enable_0_issue_fpu_0_qs; - logic perf_counter_enable_0_issue_fpu_0_wd; - logic perf_counter_enable_0_issue_fpu_0_we; - logic perf_counter_enable_0_issue_fpu_seq_0_qs; - logic perf_counter_enable_0_issue_fpu_seq_0_wd; - logic perf_counter_enable_0_issue_fpu_seq_0_we; - logic perf_counter_enable_0_issue_core_to_fpu_0_qs; - logic perf_counter_enable_0_issue_core_to_fpu_0_wd; - logic perf_counter_enable_0_issue_core_to_fpu_0_we; - logic perf_counter_enable_0_retired_instr_0_qs; - logic perf_counter_enable_0_retired_instr_0_wd; - logic perf_counter_enable_0_retired_instr_0_we; - logic perf_counter_enable_0_retired_load_0_qs; - logic perf_counter_enable_0_retired_load_0_wd; - logic perf_counter_enable_0_retired_load_0_we; - logic perf_counter_enable_0_retired_i_0_qs; - logic perf_counter_enable_0_retired_i_0_wd; - logic perf_counter_enable_0_retired_i_0_we; - logic perf_counter_enable_0_retired_acc_0_qs; - logic perf_counter_enable_0_retired_acc_0_wd; - logic perf_counter_enable_0_retired_acc_0_we; - logic perf_counter_enable_0_dma_aw_stall_0_qs; - logic perf_counter_enable_0_dma_aw_stall_0_wd; - logic perf_counter_enable_0_dma_aw_stall_0_we; - logic perf_counter_enable_0_dma_ar_stall_0_qs; - logic perf_counter_enable_0_dma_ar_stall_0_wd; - logic perf_counter_enable_0_dma_ar_stall_0_we; - logic perf_counter_enable_0_dma_r_stall_0_qs; - logic perf_counter_enable_0_dma_r_stall_0_wd; - logic perf_counter_enable_0_dma_r_stall_0_we; - logic perf_counter_enable_0_dma_w_stall_0_qs; - logic perf_counter_enable_0_dma_w_stall_0_wd; - logic perf_counter_enable_0_dma_w_stall_0_we; - logic perf_counter_enable_0_dma_buf_w_stall_0_qs; - logic perf_counter_enable_0_dma_buf_w_stall_0_wd; - logic perf_counter_enable_0_dma_buf_w_stall_0_we; - logic perf_counter_enable_0_dma_buf_r_stall_0_qs; - logic perf_counter_enable_0_dma_buf_r_stall_0_wd; - logic perf_counter_enable_0_dma_buf_r_stall_0_we; - logic perf_counter_enable_0_dma_aw_done_0_qs; - logic perf_counter_enable_0_dma_aw_done_0_wd; - logic perf_counter_enable_0_dma_aw_done_0_we; - logic perf_counter_enable_0_dma_aw_bw_0_qs; - logic perf_counter_enable_0_dma_aw_bw_0_wd; - logic perf_counter_enable_0_dma_aw_bw_0_we; - logic perf_counter_enable_0_dma_ar_done_0_qs; - logic perf_counter_enable_0_dma_ar_done_0_wd; - logic perf_counter_enable_0_dma_ar_done_0_we; - logic perf_counter_enable_0_dma_ar_bw_0_qs; - logic perf_counter_enable_0_dma_ar_bw_0_wd; - logic perf_counter_enable_0_dma_ar_bw_0_we; - logic perf_counter_enable_0_dma_r_done_0_qs; - logic perf_counter_enable_0_dma_r_done_0_wd; - logic perf_counter_enable_0_dma_r_done_0_we; - logic perf_counter_enable_0_dma_r_bw_0_qs; - logic perf_counter_enable_0_dma_r_bw_0_wd; - logic perf_counter_enable_0_dma_r_bw_0_we; - logic perf_counter_enable_0_dma_w_done_0_qs; - logic perf_counter_enable_0_dma_w_done_0_wd; - logic perf_counter_enable_0_dma_w_done_0_we; - logic perf_counter_enable_0_dma_w_bw_0_qs; - logic perf_counter_enable_0_dma_w_bw_0_wd; - logic perf_counter_enable_0_dma_w_bw_0_we; - logic perf_counter_enable_0_dma_b_done_0_qs; - logic perf_counter_enable_0_dma_b_done_0_wd; - logic perf_counter_enable_0_dma_b_done_0_we; - logic perf_counter_enable_0_dma_busy_0_qs; - logic perf_counter_enable_0_dma_busy_0_wd; - logic perf_counter_enable_0_dma_busy_0_we; - logic perf_counter_enable_0_icache_miss_0_qs; - logic perf_counter_enable_0_icache_miss_0_wd; - logic perf_counter_enable_0_icache_miss_0_we; - logic perf_counter_enable_0_icache_hit_0_qs; - logic perf_counter_enable_0_icache_hit_0_wd; - logic perf_counter_enable_0_icache_hit_0_we; - logic perf_counter_enable_0_icache_prefetch_0_qs; - logic perf_counter_enable_0_icache_prefetch_0_wd; - logic perf_counter_enable_0_icache_prefetch_0_we; - logic perf_counter_enable_0_icache_double_hit_0_qs; - logic perf_counter_enable_0_icache_double_hit_0_wd; - logic perf_counter_enable_0_icache_double_hit_0_we; - logic perf_counter_enable_0_icache_stall_0_qs; - logic perf_counter_enable_0_icache_stall_0_wd; - logic perf_counter_enable_0_icache_stall_0_we; - logic perf_counter_enable_1_cycle_1_qs; - logic perf_counter_enable_1_cycle_1_wd; - logic perf_counter_enable_1_cycle_1_we; - logic perf_counter_enable_1_tcdm_accessed_1_qs; - logic perf_counter_enable_1_tcdm_accessed_1_wd; - logic perf_counter_enable_1_tcdm_accessed_1_we; - logic perf_counter_enable_1_tcdm_congested_1_qs; - logic perf_counter_enable_1_tcdm_congested_1_wd; - logic perf_counter_enable_1_tcdm_congested_1_we; - logic perf_counter_enable_1_issue_fpu_1_qs; - logic perf_counter_enable_1_issue_fpu_1_wd; - logic perf_counter_enable_1_issue_fpu_1_we; - logic perf_counter_enable_1_issue_fpu_seq_1_qs; - logic perf_counter_enable_1_issue_fpu_seq_1_wd; - logic perf_counter_enable_1_issue_fpu_seq_1_we; - logic perf_counter_enable_1_issue_core_to_fpu_1_qs; - logic perf_counter_enable_1_issue_core_to_fpu_1_wd; - logic perf_counter_enable_1_issue_core_to_fpu_1_we; - logic perf_counter_enable_1_retired_instr_1_qs; - logic perf_counter_enable_1_retired_instr_1_wd; - logic perf_counter_enable_1_retired_instr_1_we; - logic perf_counter_enable_1_retired_load_1_qs; - logic perf_counter_enable_1_retired_load_1_wd; - logic perf_counter_enable_1_retired_load_1_we; - logic perf_counter_enable_1_retired_i_1_qs; - logic perf_counter_enable_1_retired_i_1_wd; - logic perf_counter_enable_1_retired_i_1_we; - logic perf_counter_enable_1_retired_acc_1_qs; - logic perf_counter_enable_1_retired_acc_1_wd; - logic perf_counter_enable_1_retired_acc_1_we; - logic perf_counter_enable_1_dma_aw_stall_1_qs; - logic perf_counter_enable_1_dma_aw_stall_1_wd; - logic perf_counter_enable_1_dma_aw_stall_1_we; - logic perf_counter_enable_1_dma_ar_stall_1_qs; - logic perf_counter_enable_1_dma_ar_stall_1_wd; - logic perf_counter_enable_1_dma_ar_stall_1_we; - logic perf_counter_enable_1_dma_r_stall_1_qs; - logic perf_counter_enable_1_dma_r_stall_1_wd; - logic perf_counter_enable_1_dma_r_stall_1_we; - logic perf_counter_enable_1_dma_w_stall_1_qs; - logic perf_counter_enable_1_dma_w_stall_1_wd; - logic perf_counter_enable_1_dma_w_stall_1_we; - logic perf_counter_enable_1_dma_buf_w_stall_1_qs; - logic perf_counter_enable_1_dma_buf_w_stall_1_wd; - logic perf_counter_enable_1_dma_buf_w_stall_1_we; - logic perf_counter_enable_1_dma_buf_r_stall_1_qs; - logic perf_counter_enable_1_dma_buf_r_stall_1_wd; - logic perf_counter_enable_1_dma_buf_r_stall_1_we; - logic perf_counter_enable_1_dma_aw_done_1_qs; - logic perf_counter_enable_1_dma_aw_done_1_wd; - logic perf_counter_enable_1_dma_aw_done_1_we; - logic perf_counter_enable_1_dma_aw_bw_1_qs; - logic perf_counter_enable_1_dma_aw_bw_1_wd; - logic perf_counter_enable_1_dma_aw_bw_1_we; - logic perf_counter_enable_1_dma_ar_done_1_qs; - logic perf_counter_enable_1_dma_ar_done_1_wd; - logic perf_counter_enable_1_dma_ar_done_1_we; - logic perf_counter_enable_1_dma_ar_bw_1_qs; - logic perf_counter_enable_1_dma_ar_bw_1_wd; - logic perf_counter_enable_1_dma_ar_bw_1_we; - logic perf_counter_enable_1_dma_r_done_1_qs; - logic perf_counter_enable_1_dma_r_done_1_wd; - logic perf_counter_enable_1_dma_r_done_1_we; - logic perf_counter_enable_1_dma_r_bw_1_qs; - logic perf_counter_enable_1_dma_r_bw_1_wd; - logic perf_counter_enable_1_dma_r_bw_1_we; - logic perf_counter_enable_1_dma_w_done_1_qs; - logic perf_counter_enable_1_dma_w_done_1_wd; - logic perf_counter_enable_1_dma_w_done_1_we; - logic perf_counter_enable_1_dma_w_bw_1_qs; - logic perf_counter_enable_1_dma_w_bw_1_wd; - logic perf_counter_enable_1_dma_w_bw_1_we; - logic perf_counter_enable_1_dma_b_done_1_qs; - logic perf_counter_enable_1_dma_b_done_1_wd; - logic perf_counter_enable_1_dma_b_done_1_we; - logic perf_counter_enable_1_dma_busy_1_qs; - logic perf_counter_enable_1_dma_busy_1_wd; - logic perf_counter_enable_1_dma_busy_1_we; - logic perf_counter_enable_1_icache_miss_1_qs; - logic perf_counter_enable_1_icache_miss_1_wd; - logic perf_counter_enable_1_icache_miss_1_we; - logic perf_counter_enable_1_icache_hit_1_qs; - logic perf_counter_enable_1_icache_hit_1_wd; - logic perf_counter_enable_1_icache_hit_1_we; - logic perf_counter_enable_1_icache_prefetch_1_qs; - logic perf_counter_enable_1_icache_prefetch_1_wd; - logic perf_counter_enable_1_icache_prefetch_1_we; - logic perf_counter_enable_1_icache_double_hit_1_qs; - logic perf_counter_enable_1_icache_double_hit_1_wd; - logic perf_counter_enable_1_icache_double_hit_1_we; - logic perf_counter_enable_1_icache_stall_1_qs; - logic perf_counter_enable_1_icache_stall_1_wd; - logic perf_counter_enable_1_icache_stall_1_we; - logic perf_counter_enable_2_cycle_2_qs; - logic perf_counter_enable_2_cycle_2_wd; - logic perf_counter_enable_2_cycle_2_we; - logic perf_counter_enable_2_tcdm_accessed_2_qs; - logic perf_counter_enable_2_tcdm_accessed_2_wd; - logic perf_counter_enable_2_tcdm_accessed_2_we; - logic perf_counter_enable_2_tcdm_congested_2_qs; - logic perf_counter_enable_2_tcdm_congested_2_wd; - logic perf_counter_enable_2_tcdm_congested_2_we; - logic perf_counter_enable_2_issue_fpu_2_qs; - logic perf_counter_enable_2_issue_fpu_2_wd; - logic perf_counter_enable_2_issue_fpu_2_we; - logic perf_counter_enable_2_issue_fpu_seq_2_qs; - logic perf_counter_enable_2_issue_fpu_seq_2_wd; - logic perf_counter_enable_2_issue_fpu_seq_2_we; - logic perf_counter_enable_2_issue_core_to_fpu_2_qs; - logic perf_counter_enable_2_issue_core_to_fpu_2_wd; - logic perf_counter_enable_2_issue_core_to_fpu_2_we; - logic perf_counter_enable_2_retired_instr_2_qs; - logic perf_counter_enable_2_retired_instr_2_wd; - logic perf_counter_enable_2_retired_instr_2_we; - logic perf_counter_enable_2_retired_load_2_qs; - logic perf_counter_enable_2_retired_load_2_wd; - logic perf_counter_enable_2_retired_load_2_we; - logic perf_counter_enable_2_retired_i_2_qs; - logic perf_counter_enable_2_retired_i_2_wd; - logic perf_counter_enable_2_retired_i_2_we; - logic perf_counter_enable_2_retired_acc_2_qs; - logic perf_counter_enable_2_retired_acc_2_wd; - logic perf_counter_enable_2_retired_acc_2_we; - logic perf_counter_enable_2_dma_aw_stall_2_qs; - logic perf_counter_enable_2_dma_aw_stall_2_wd; - logic perf_counter_enable_2_dma_aw_stall_2_we; - logic perf_counter_enable_2_dma_ar_stall_2_qs; - logic perf_counter_enable_2_dma_ar_stall_2_wd; - logic perf_counter_enable_2_dma_ar_stall_2_we; - logic perf_counter_enable_2_dma_r_stall_2_qs; - logic perf_counter_enable_2_dma_r_stall_2_wd; - logic perf_counter_enable_2_dma_r_stall_2_we; - logic perf_counter_enable_2_dma_w_stall_2_qs; - logic perf_counter_enable_2_dma_w_stall_2_wd; - logic perf_counter_enable_2_dma_w_stall_2_we; - logic perf_counter_enable_2_dma_buf_w_stall_2_qs; - logic perf_counter_enable_2_dma_buf_w_stall_2_wd; - logic perf_counter_enable_2_dma_buf_w_stall_2_we; - logic perf_counter_enable_2_dma_buf_r_stall_2_qs; - logic perf_counter_enable_2_dma_buf_r_stall_2_wd; - logic perf_counter_enable_2_dma_buf_r_stall_2_we; - logic perf_counter_enable_2_dma_aw_done_2_qs; - logic perf_counter_enable_2_dma_aw_done_2_wd; - logic perf_counter_enable_2_dma_aw_done_2_we; - logic perf_counter_enable_2_dma_aw_bw_2_qs; - logic perf_counter_enable_2_dma_aw_bw_2_wd; - logic perf_counter_enable_2_dma_aw_bw_2_we; - logic perf_counter_enable_2_dma_ar_done_2_qs; - logic perf_counter_enable_2_dma_ar_done_2_wd; - logic perf_counter_enable_2_dma_ar_done_2_we; - logic perf_counter_enable_2_dma_ar_bw_2_qs; - logic perf_counter_enable_2_dma_ar_bw_2_wd; - logic perf_counter_enable_2_dma_ar_bw_2_we; - logic perf_counter_enable_2_dma_r_done_2_qs; - logic perf_counter_enable_2_dma_r_done_2_wd; - logic perf_counter_enable_2_dma_r_done_2_we; - logic perf_counter_enable_2_dma_r_bw_2_qs; - logic perf_counter_enable_2_dma_r_bw_2_wd; - logic perf_counter_enable_2_dma_r_bw_2_we; - logic perf_counter_enable_2_dma_w_done_2_qs; - logic perf_counter_enable_2_dma_w_done_2_wd; - logic perf_counter_enable_2_dma_w_done_2_we; - logic perf_counter_enable_2_dma_w_bw_2_qs; - logic perf_counter_enable_2_dma_w_bw_2_wd; - logic perf_counter_enable_2_dma_w_bw_2_we; - logic perf_counter_enable_2_dma_b_done_2_qs; - logic perf_counter_enable_2_dma_b_done_2_wd; - logic perf_counter_enable_2_dma_b_done_2_we; - logic perf_counter_enable_2_dma_busy_2_qs; - logic perf_counter_enable_2_dma_busy_2_wd; - logic perf_counter_enable_2_dma_busy_2_we; - logic perf_counter_enable_2_icache_miss_2_qs; - logic perf_counter_enable_2_icache_miss_2_wd; - logic perf_counter_enable_2_icache_miss_2_we; - logic perf_counter_enable_2_icache_hit_2_qs; - logic perf_counter_enable_2_icache_hit_2_wd; - logic perf_counter_enable_2_icache_hit_2_we; - logic perf_counter_enable_2_icache_prefetch_2_qs; - logic perf_counter_enable_2_icache_prefetch_2_wd; - logic perf_counter_enable_2_icache_prefetch_2_we; - logic perf_counter_enable_2_icache_double_hit_2_qs; - logic perf_counter_enable_2_icache_double_hit_2_wd; - logic perf_counter_enable_2_icache_double_hit_2_we; - logic perf_counter_enable_2_icache_stall_2_qs; - logic perf_counter_enable_2_icache_stall_2_wd; - logic perf_counter_enable_2_icache_stall_2_we; - logic perf_counter_enable_3_cycle_3_qs; - logic perf_counter_enable_3_cycle_3_wd; - logic perf_counter_enable_3_cycle_3_we; - logic perf_counter_enable_3_tcdm_accessed_3_qs; - logic perf_counter_enable_3_tcdm_accessed_3_wd; - logic perf_counter_enable_3_tcdm_accessed_3_we; - logic perf_counter_enable_3_tcdm_congested_3_qs; - logic perf_counter_enable_3_tcdm_congested_3_wd; - logic perf_counter_enable_3_tcdm_congested_3_we; - logic perf_counter_enable_3_issue_fpu_3_qs; - logic perf_counter_enable_3_issue_fpu_3_wd; - logic perf_counter_enable_3_issue_fpu_3_we; - logic perf_counter_enable_3_issue_fpu_seq_3_qs; - logic perf_counter_enable_3_issue_fpu_seq_3_wd; - logic perf_counter_enable_3_issue_fpu_seq_3_we; - logic perf_counter_enable_3_issue_core_to_fpu_3_qs; - logic perf_counter_enable_3_issue_core_to_fpu_3_wd; - logic perf_counter_enable_3_issue_core_to_fpu_3_we; - logic perf_counter_enable_3_retired_instr_3_qs; - logic perf_counter_enable_3_retired_instr_3_wd; - logic perf_counter_enable_3_retired_instr_3_we; - logic perf_counter_enable_3_retired_load_3_qs; - logic perf_counter_enable_3_retired_load_3_wd; - logic perf_counter_enable_3_retired_load_3_we; - logic perf_counter_enable_3_retired_i_3_qs; - logic perf_counter_enable_3_retired_i_3_wd; - logic perf_counter_enable_3_retired_i_3_we; - logic perf_counter_enable_3_retired_acc_3_qs; - logic perf_counter_enable_3_retired_acc_3_wd; - logic perf_counter_enable_3_retired_acc_3_we; - logic perf_counter_enable_3_dma_aw_stall_3_qs; - logic perf_counter_enable_3_dma_aw_stall_3_wd; - logic perf_counter_enable_3_dma_aw_stall_3_we; - logic perf_counter_enable_3_dma_ar_stall_3_qs; - logic perf_counter_enable_3_dma_ar_stall_3_wd; - logic perf_counter_enable_3_dma_ar_stall_3_we; - logic perf_counter_enable_3_dma_r_stall_3_qs; - logic perf_counter_enable_3_dma_r_stall_3_wd; - logic perf_counter_enable_3_dma_r_stall_3_we; - logic perf_counter_enable_3_dma_w_stall_3_qs; - logic perf_counter_enable_3_dma_w_stall_3_wd; - logic perf_counter_enable_3_dma_w_stall_3_we; - logic perf_counter_enable_3_dma_buf_w_stall_3_qs; - logic perf_counter_enable_3_dma_buf_w_stall_3_wd; - logic perf_counter_enable_3_dma_buf_w_stall_3_we; - logic perf_counter_enable_3_dma_buf_r_stall_3_qs; - logic perf_counter_enable_3_dma_buf_r_stall_3_wd; - logic perf_counter_enable_3_dma_buf_r_stall_3_we; - logic perf_counter_enable_3_dma_aw_done_3_qs; - logic perf_counter_enable_3_dma_aw_done_3_wd; - logic perf_counter_enable_3_dma_aw_done_3_we; - logic perf_counter_enable_3_dma_aw_bw_3_qs; - logic perf_counter_enable_3_dma_aw_bw_3_wd; - logic perf_counter_enable_3_dma_aw_bw_3_we; - logic perf_counter_enable_3_dma_ar_done_3_qs; - logic perf_counter_enable_3_dma_ar_done_3_wd; - logic perf_counter_enable_3_dma_ar_done_3_we; - logic perf_counter_enable_3_dma_ar_bw_3_qs; - logic perf_counter_enable_3_dma_ar_bw_3_wd; - logic perf_counter_enable_3_dma_ar_bw_3_we; - logic perf_counter_enable_3_dma_r_done_3_qs; - logic perf_counter_enable_3_dma_r_done_3_wd; - logic perf_counter_enable_3_dma_r_done_3_we; - logic perf_counter_enable_3_dma_r_bw_3_qs; - logic perf_counter_enable_3_dma_r_bw_3_wd; - logic perf_counter_enable_3_dma_r_bw_3_we; - logic perf_counter_enable_3_dma_w_done_3_qs; - logic perf_counter_enable_3_dma_w_done_3_wd; - logic perf_counter_enable_3_dma_w_done_3_we; - logic perf_counter_enable_3_dma_w_bw_3_qs; - logic perf_counter_enable_3_dma_w_bw_3_wd; - logic perf_counter_enable_3_dma_w_bw_3_we; - logic perf_counter_enable_3_dma_b_done_3_qs; - logic perf_counter_enable_3_dma_b_done_3_wd; - logic perf_counter_enable_3_dma_b_done_3_we; - logic perf_counter_enable_3_dma_busy_3_qs; - logic perf_counter_enable_3_dma_busy_3_wd; - logic perf_counter_enable_3_dma_busy_3_we; - logic perf_counter_enable_3_icache_miss_3_qs; - logic perf_counter_enable_3_icache_miss_3_wd; - logic perf_counter_enable_3_icache_miss_3_we; - logic perf_counter_enable_3_icache_hit_3_qs; - logic perf_counter_enable_3_icache_hit_3_wd; - logic perf_counter_enable_3_icache_hit_3_we; - logic perf_counter_enable_3_icache_prefetch_3_qs; - logic perf_counter_enable_3_icache_prefetch_3_wd; - logic perf_counter_enable_3_icache_prefetch_3_we; - logic perf_counter_enable_3_icache_double_hit_3_qs; - logic perf_counter_enable_3_icache_double_hit_3_wd; - logic perf_counter_enable_3_icache_double_hit_3_we; - logic perf_counter_enable_3_icache_stall_3_qs; - logic perf_counter_enable_3_icache_stall_3_wd; - logic perf_counter_enable_3_icache_stall_3_we; - logic perf_counter_enable_4_cycle_4_qs; - logic perf_counter_enable_4_cycle_4_wd; - logic perf_counter_enable_4_cycle_4_we; - logic perf_counter_enable_4_tcdm_accessed_4_qs; - logic perf_counter_enable_4_tcdm_accessed_4_wd; - logic perf_counter_enable_4_tcdm_accessed_4_we; - logic perf_counter_enable_4_tcdm_congested_4_qs; - logic perf_counter_enable_4_tcdm_congested_4_wd; - logic perf_counter_enable_4_tcdm_congested_4_we; - logic perf_counter_enable_4_issue_fpu_4_qs; - logic perf_counter_enable_4_issue_fpu_4_wd; - logic perf_counter_enable_4_issue_fpu_4_we; - logic perf_counter_enable_4_issue_fpu_seq_4_qs; - logic perf_counter_enable_4_issue_fpu_seq_4_wd; - logic perf_counter_enable_4_issue_fpu_seq_4_we; - logic perf_counter_enable_4_issue_core_to_fpu_4_qs; - logic perf_counter_enable_4_issue_core_to_fpu_4_wd; - logic perf_counter_enable_4_issue_core_to_fpu_4_we; - logic perf_counter_enable_4_retired_instr_4_qs; - logic perf_counter_enable_4_retired_instr_4_wd; - logic perf_counter_enable_4_retired_instr_4_we; - logic perf_counter_enable_4_retired_load_4_qs; - logic perf_counter_enable_4_retired_load_4_wd; - logic perf_counter_enable_4_retired_load_4_we; - logic perf_counter_enable_4_retired_i_4_qs; - logic perf_counter_enable_4_retired_i_4_wd; - logic perf_counter_enable_4_retired_i_4_we; - logic perf_counter_enable_4_retired_acc_4_qs; - logic perf_counter_enable_4_retired_acc_4_wd; - logic perf_counter_enable_4_retired_acc_4_we; - logic perf_counter_enable_4_dma_aw_stall_4_qs; - logic perf_counter_enable_4_dma_aw_stall_4_wd; - logic perf_counter_enable_4_dma_aw_stall_4_we; - logic perf_counter_enable_4_dma_ar_stall_4_qs; - logic perf_counter_enable_4_dma_ar_stall_4_wd; - logic perf_counter_enable_4_dma_ar_stall_4_we; - logic perf_counter_enable_4_dma_r_stall_4_qs; - logic perf_counter_enable_4_dma_r_stall_4_wd; - logic perf_counter_enable_4_dma_r_stall_4_we; - logic perf_counter_enable_4_dma_w_stall_4_qs; - logic perf_counter_enable_4_dma_w_stall_4_wd; - logic perf_counter_enable_4_dma_w_stall_4_we; - logic perf_counter_enable_4_dma_buf_w_stall_4_qs; - logic perf_counter_enable_4_dma_buf_w_stall_4_wd; - logic perf_counter_enable_4_dma_buf_w_stall_4_we; - logic perf_counter_enable_4_dma_buf_r_stall_4_qs; - logic perf_counter_enable_4_dma_buf_r_stall_4_wd; - logic perf_counter_enable_4_dma_buf_r_stall_4_we; - logic perf_counter_enable_4_dma_aw_done_4_qs; - logic perf_counter_enable_4_dma_aw_done_4_wd; - logic perf_counter_enable_4_dma_aw_done_4_we; - logic perf_counter_enable_4_dma_aw_bw_4_qs; - logic perf_counter_enable_4_dma_aw_bw_4_wd; - logic perf_counter_enable_4_dma_aw_bw_4_we; - logic perf_counter_enable_4_dma_ar_done_4_qs; - logic perf_counter_enable_4_dma_ar_done_4_wd; - logic perf_counter_enable_4_dma_ar_done_4_we; - logic perf_counter_enable_4_dma_ar_bw_4_qs; - logic perf_counter_enable_4_dma_ar_bw_4_wd; - logic perf_counter_enable_4_dma_ar_bw_4_we; - logic perf_counter_enable_4_dma_r_done_4_qs; - logic perf_counter_enable_4_dma_r_done_4_wd; - logic perf_counter_enable_4_dma_r_done_4_we; - logic perf_counter_enable_4_dma_r_bw_4_qs; - logic perf_counter_enable_4_dma_r_bw_4_wd; - logic perf_counter_enable_4_dma_r_bw_4_we; - logic perf_counter_enable_4_dma_w_done_4_qs; - logic perf_counter_enable_4_dma_w_done_4_wd; - logic perf_counter_enable_4_dma_w_done_4_we; - logic perf_counter_enable_4_dma_w_bw_4_qs; - logic perf_counter_enable_4_dma_w_bw_4_wd; - logic perf_counter_enable_4_dma_w_bw_4_we; - logic perf_counter_enable_4_dma_b_done_4_qs; - logic perf_counter_enable_4_dma_b_done_4_wd; - logic perf_counter_enable_4_dma_b_done_4_we; - logic perf_counter_enable_4_dma_busy_4_qs; - logic perf_counter_enable_4_dma_busy_4_wd; - logic perf_counter_enable_4_dma_busy_4_we; - logic perf_counter_enable_4_icache_miss_4_qs; - logic perf_counter_enable_4_icache_miss_4_wd; - logic perf_counter_enable_4_icache_miss_4_we; - logic perf_counter_enable_4_icache_hit_4_qs; - logic perf_counter_enable_4_icache_hit_4_wd; - logic perf_counter_enable_4_icache_hit_4_we; - logic perf_counter_enable_4_icache_prefetch_4_qs; - logic perf_counter_enable_4_icache_prefetch_4_wd; - logic perf_counter_enable_4_icache_prefetch_4_we; - logic perf_counter_enable_4_icache_double_hit_4_qs; - logic perf_counter_enable_4_icache_double_hit_4_wd; - logic perf_counter_enable_4_icache_double_hit_4_we; - logic perf_counter_enable_4_icache_stall_4_qs; - logic perf_counter_enable_4_icache_stall_4_wd; - logic perf_counter_enable_4_icache_stall_4_we; - logic perf_counter_enable_5_cycle_5_qs; - logic perf_counter_enable_5_cycle_5_wd; - logic perf_counter_enable_5_cycle_5_we; - logic perf_counter_enable_5_tcdm_accessed_5_qs; - logic perf_counter_enable_5_tcdm_accessed_5_wd; - logic perf_counter_enable_5_tcdm_accessed_5_we; - logic perf_counter_enable_5_tcdm_congested_5_qs; - logic perf_counter_enable_5_tcdm_congested_5_wd; - logic perf_counter_enable_5_tcdm_congested_5_we; - logic perf_counter_enable_5_issue_fpu_5_qs; - logic perf_counter_enable_5_issue_fpu_5_wd; - logic perf_counter_enable_5_issue_fpu_5_we; - logic perf_counter_enable_5_issue_fpu_seq_5_qs; - logic perf_counter_enable_5_issue_fpu_seq_5_wd; - logic perf_counter_enable_5_issue_fpu_seq_5_we; - logic perf_counter_enable_5_issue_core_to_fpu_5_qs; - logic perf_counter_enable_5_issue_core_to_fpu_5_wd; - logic perf_counter_enable_5_issue_core_to_fpu_5_we; - logic perf_counter_enable_5_retired_instr_5_qs; - logic perf_counter_enable_5_retired_instr_5_wd; - logic perf_counter_enable_5_retired_instr_5_we; - logic perf_counter_enable_5_retired_load_5_qs; - logic perf_counter_enable_5_retired_load_5_wd; - logic perf_counter_enable_5_retired_load_5_we; - logic perf_counter_enable_5_retired_i_5_qs; - logic perf_counter_enable_5_retired_i_5_wd; - logic perf_counter_enable_5_retired_i_5_we; - logic perf_counter_enable_5_retired_acc_5_qs; - logic perf_counter_enable_5_retired_acc_5_wd; - logic perf_counter_enable_5_retired_acc_5_we; - logic perf_counter_enable_5_dma_aw_stall_5_qs; - logic perf_counter_enable_5_dma_aw_stall_5_wd; - logic perf_counter_enable_5_dma_aw_stall_5_we; - logic perf_counter_enable_5_dma_ar_stall_5_qs; - logic perf_counter_enable_5_dma_ar_stall_5_wd; - logic perf_counter_enable_5_dma_ar_stall_5_we; - logic perf_counter_enable_5_dma_r_stall_5_qs; - logic perf_counter_enable_5_dma_r_stall_5_wd; - logic perf_counter_enable_5_dma_r_stall_5_we; - logic perf_counter_enable_5_dma_w_stall_5_qs; - logic perf_counter_enable_5_dma_w_stall_5_wd; - logic perf_counter_enable_5_dma_w_stall_5_we; - logic perf_counter_enable_5_dma_buf_w_stall_5_qs; - logic perf_counter_enable_5_dma_buf_w_stall_5_wd; - logic perf_counter_enable_5_dma_buf_w_stall_5_we; - logic perf_counter_enable_5_dma_buf_r_stall_5_qs; - logic perf_counter_enable_5_dma_buf_r_stall_5_wd; - logic perf_counter_enable_5_dma_buf_r_stall_5_we; - logic perf_counter_enable_5_dma_aw_done_5_qs; - logic perf_counter_enable_5_dma_aw_done_5_wd; - logic perf_counter_enable_5_dma_aw_done_5_we; - logic perf_counter_enable_5_dma_aw_bw_5_qs; - logic perf_counter_enable_5_dma_aw_bw_5_wd; - logic perf_counter_enable_5_dma_aw_bw_5_we; - logic perf_counter_enable_5_dma_ar_done_5_qs; - logic perf_counter_enable_5_dma_ar_done_5_wd; - logic perf_counter_enable_5_dma_ar_done_5_we; - logic perf_counter_enable_5_dma_ar_bw_5_qs; - logic perf_counter_enable_5_dma_ar_bw_5_wd; - logic perf_counter_enable_5_dma_ar_bw_5_we; - logic perf_counter_enable_5_dma_r_done_5_qs; - logic perf_counter_enable_5_dma_r_done_5_wd; - logic perf_counter_enable_5_dma_r_done_5_we; - logic perf_counter_enable_5_dma_r_bw_5_qs; - logic perf_counter_enable_5_dma_r_bw_5_wd; - logic perf_counter_enable_5_dma_r_bw_5_we; - logic perf_counter_enable_5_dma_w_done_5_qs; - logic perf_counter_enable_5_dma_w_done_5_wd; - logic perf_counter_enable_5_dma_w_done_5_we; - logic perf_counter_enable_5_dma_w_bw_5_qs; - logic perf_counter_enable_5_dma_w_bw_5_wd; - logic perf_counter_enable_5_dma_w_bw_5_we; - logic perf_counter_enable_5_dma_b_done_5_qs; - logic perf_counter_enable_5_dma_b_done_5_wd; - logic perf_counter_enable_5_dma_b_done_5_we; - logic perf_counter_enable_5_dma_busy_5_qs; - logic perf_counter_enable_5_dma_busy_5_wd; - logic perf_counter_enable_5_dma_busy_5_we; - logic perf_counter_enable_5_icache_miss_5_qs; - logic perf_counter_enable_5_icache_miss_5_wd; - logic perf_counter_enable_5_icache_miss_5_we; - logic perf_counter_enable_5_icache_hit_5_qs; - logic perf_counter_enable_5_icache_hit_5_wd; - logic perf_counter_enable_5_icache_hit_5_we; - logic perf_counter_enable_5_icache_prefetch_5_qs; - logic perf_counter_enable_5_icache_prefetch_5_wd; - logic perf_counter_enable_5_icache_prefetch_5_we; - logic perf_counter_enable_5_icache_double_hit_5_qs; - logic perf_counter_enable_5_icache_double_hit_5_wd; - logic perf_counter_enable_5_icache_double_hit_5_we; - logic perf_counter_enable_5_icache_stall_5_qs; - logic perf_counter_enable_5_icache_stall_5_wd; - logic perf_counter_enable_5_icache_stall_5_we; - logic perf_counter_enable_6_cycle_6_qs; - logic perf_counter_enable_6_cycle_6_wd; - logic perf_counter_enable_6_cycle_6_we; - logic perf_counter_enable_6_tcdm_accessed_6_qs; - logic perf_counter_enable_6_tcdm_accessed_6_wd; - logic perf_counter_enable_6_tcdm_accessed_6_we; - logic perf_counter_enable_6_tcdm_congested_6_qs; - logic perf_counter_enable_6_tcdm_congested_6_wd; - logic perf_counter_enable_6_tcdm_congested_6_we; - logic perf_counter_enable_6_issue_fpu_6_qs; - logic perf_counter_enable_6_issue_fpu_6_wd; - logic perf_counter_enable_6_issue_fpu_6_we; - logic perf_counter_enable_6_issue_fpu_seq_6_qs; - logic perf_counter_enable_6_issue_fpu_seq_6_wd; - logic perf_counter_enable_6_issue_fpu_seq_6_we; - logic perf_counter_enable_6_issue_core_to_fpu_6_qs; - logic perf_counter_enable_6_issue_core_to_fpu_6_wd; - logic perf_counter_enable_6_issue_core_to_fpu_6_we; - logic perf_counter_enable_6_retired_instr_6_qs; - logic perf_counter_enable_6_retired_instr_6_wd; - logic perf_counter_enable_6_retired_instr_6_we; - logic perf_counter_enable_6_retired_load_6_qs; - logic perf_counter_enable_6_retired_load_6_wd; - logic perf_counter_enable_6_retired_load_6_we; - logic perf_counter_enable_6_retired_i_6_qs; - logic perf_counter_enable_6_retired_i_6_wd; - logic perf_counter_enable_6_retired_i_6_we; - logic perf_counter_enable_6_retired_acc_6_qs; - logic perf_counter_enable_6_retired_acc_6_wd; - logic perf_counter_enable_6_retired_acc_6_we; - logic perf_counter_enable_6_dma_aw_stall_6_qs; - logic perf_counter_enable_6_dma_aw_stall_6_wd; - logic perf_counter_enable_6_dma_aw_stall_6_we; - logic perf_counter_enable_6_dma_ar_stall_6_qs; - logic perf_counter_enable_6_dma_ar_stall_6_wd; - logic perf_counter_enable_6_dma_ar_stall_6_we; - logic perf_counter_enable_6_dma_r_stall_6_qs; - logic perf_counter_enable_6_dma_r_stall_6_wd; - logic perf_counter_enable_6_dma_r_stall_6_we; - logic perf_counter_enable_6_dma_w_stall_6_qs; - logic perf_counter_enable_6_dma_w_stall_6_wd; - logic perf_counter_enable_6_dma_w_stall_6_we; - logic perf_counter_enable_6_dma_buf_w_stall_6_qs; - logic perf_counter_enable_6_dma_buf_w_stall_6_wd; - logic perf_counter_enable_6_dma_buf_w_stall_6_we; - logic perf_counter_enable_6_dma_buf_r_stall_6_qs; - logic perf_counter_enable_6_dma_buf_r_stall_6_wd; - logic perf_counter_enable_6_dma_buf_r_stall_6_we; - logic perf_counter_enable_6_dma_aw_done_6_qs; - logic perf_counter_enable_6_dma_aw_done_6_wd; - logic perf_counter_enable_6_dma_aw_done_6_we; - logic perf_counter_enable_6_dma_aw_bw_6_qs; - logic perf_counter_enable_6_dma_aw_bw_6_wd; - logic perf_counter_enable_6_dma_aw_bw_6_we; - logic perf_counter_enable_6_dma_ar_done_6_qs; - logic perf_counter_enable_6_dma_ar_done_6_wd; - logic perf_counter_enable_6_dma_ar_done_6_we; - logic perf_counter_enable_6_dma_ar_bw_6_qs; - logic perf_counter_enable_6_dma_ar_bw_6_wd; - logic perf_counter_enable_6_dma_ar_bw_6_we; - logic perf_counter_enable_6_dma_r_done_6_qs; - logic perf_counter_enable_6_dma_r_done_6_wd; - logic perf_counter_enable_6_dma_r_done_6_we; - logic perf_counter_enable_6_dma_r_bw_6_qs; - logic perf_counter_enable_6_dma_r_bw_6_wd; - logic perf_counter_enable_6_dma_r_bw_6_we; - logic perf_counter_enable_6_dma_w_done_6_qs; - logic perf_counter_enable_6_dma_w_done_6_wd; - logic perf_counter_enable_6_dma_w_done_6_we; - logic perf_counter_enable_6_dma_w_bw_6_qs; - logic perf_counter_enable_6_dma_w_bw_6_wd; - logic perf_counter_enable_6_dma_w_bw_6_we; - logic perf_counter_enable_6_dma_b_done_6_qs; - logic perf_counter_enable_6_dma_b_done_6_wd; - logic perf_counter_enable_6_dma_b_done_6_we; - logic perf_counter_enable_6_dma_busy_6_qs; - logic perf_counter_enable_6_dma_busy_6_wd; - logic perf_counter_enable_6_dma_busy_6_we; - logic perf_counter_enable_6_icache_miss_6_qs; - logic perf_counter_enable_6_icache_miss_6_wd; - logic perf_counter_enable_6_icache_miss_6_we; - logic perf_counter_enable_6_icache_hit_6_qs; - logic perf_counter_enable_6_icache_hit_6_wd; - logic perf_counter_enable_6_icache_hit_6_we; - logic perf_counter_enable_6_icache_prefetch_6_qs; - logic perf_counter_enable_6_icache_prefetch_6_wd; - logic perf_counter_enable_6_icache_prefetch_6_we; - logic perf_counter_enable_6_icache_double_hit_6_qs; - logic perf_counter_enable_6_icache_double_hit_6_wd; - logic perf_counter_enable_6_icache_double_hit_6_we; - logic perf_counter_enable_6_icache_stall_6_qs; - logic perf_counter_enable_6_icache_stall_6_wd; - logic perf_counter_enable_6_icache_stall_6_we; - logic perf_counter_enable_7_cycle_7_qs; - logic perf_counter_enable_7_cycle_7_wd; - logic perf_counter_enable_7_cycle_7_we; - logic perf_counter_enable_7_tcdm_accessed_7_qs; - logic perf_counter_enable_7_tcdm_accessed_7_wd; - logic perf_counter_enable_7_tcdm_accessed_7_we; - logic perf_counter_enable_7_tcdm_congested_7_qs; - logic perf_counter_enable_7_tcdm_congested_7_wd; - logic perf_counter_enable_7_tcdm_congested_7_we; - logic perf_counter_enable_7_issue_fpu_7_qs; - logic perf_counter_enable_7_issue_fpu_7_wd; - logic perf_counter_enable_7_issue_fpu_7_we; - logic perf_counter_enable_7_issue_fpu_seq_7_qs; - logic perf_counter_enable_7_issue_fpu_seq_7_wd; - logic perf_counter_enable_7_issue_fpu_seq_7_we; - logic perf_counter_enable_7_issue_core_to_fpu_7_qs; - logic perf_counter_enable_7_issue_core_to_fpu_7_wd; - logic perf_counter_enable_7_issue_core_to_fpu_7_we; - logic perf_counter_enable_7_retired_instr_7_qs; - logic perf_counter_enable_7_retired_instr_7_wd; - logic perf_counter_enable_7_retired_instr_7_we; - logic perf_counter_enable_7_retired_load_7_qs; - logic perf_counter_enable_7_retired_load_7_wd; - logic perf_counter_enable_7_retired_load_7_we; - logic perf_counter_enable_7_retired_i_7_qs; - logic perf_counter_enable_7_retired_i_7_wd; - logic perf_counter_enable_7_retired_i_7_we; - logic perf_counter_enable_7_retired_acc_7_qs; - logic perf_counter_enable_7_retired_acc_7_wd; - logic perf_counter_enable_7_retired_acc_7_we; - logic perf_counter_enable_7_dma_aw_stall_7_qs; - logic perf_counter_enable_7_dma_aw_stall_7_wd; - logic perf_counter_enable_7_dma_aw_stall_7_we; - logic perf_counter_enable_7_dma_ar_stall_7_qs; - logic perf_counter_enable_7_dma_ar_stall_7_wd; - logic perf_counter_enable_7_dma_ar_stall_7_we; - logic perf_counter_enable_7_dma_r_stall_7_qs; - logic perf_counter_enable_7_dma_r_stall_7_wd; - logic perf_counter_enable_7_dma_r_stall_7_we; - logic perf_counter_enable_7_dma_w_stall_7_qs; - logic perf_counter_enable_7_dma_w_stall_7_wd; - logic perf_counter_enable_7_dma_w_stall_7_we; - logic perf_counter_enable_7_dma_buf_w_stall_7_qs; - logic perf_counter_enable_7_dma_buf_w_stall_7_wd; - logic perf_counter_enable_7_dma_buf_w_stall_7_we; - logic perf_counter_enable_7_dma_buf_r_stall_7_qs; - logic perf_counter_enable_7_dma_buf_r_stall_7_wd; - logic perf_counter_enable_7_dma_buf_r_stall_7_we; - logic perf_counter_enable_7_dma_aw_done_7_qs; - logic perf_counter_enable_7_dma_aw_done_7_wd; - logic perf_counter_enable_7_dma_aw_done_7_we; - logic perf_counter_enable_7_dma_aw_bw_7_qs; - logic perf_counter_enable_7_dma_aw_bw_7_wd; - logic perf_counter_enable_7_dma_aw_bw_7_we; - logic perf_counter_enable_7_dma_ar_done_7_qs; - logic perf_counter_enable_7_dma_ar_done_7_wd; - logic perf_counter_enable_7_dma_ar_done_7_we; - logic perf_counter_enable_7_dma_ar_bw_7_qs; - logic perf_counter_enable_7_dma_ar_bw_7_wd; - logic perf_counter_enable_7_dma_ar_bw_7_we; - logic perf_counter_enable_7_dma_r_done_7_qs; - logic perf_counter_enable_7_dma_r_done_7_wd; - logic perf_counter_enable_7_dma_r_done_7_we; - logic perf_counter_enable_7_dma_r_bw_7_qs; - logic perf_counter_enable_7_dma_r_bw_7_wd; - logic perf_counter_enable_7_dma_r_bw_7_we; - logic perf_counter_enable_7_dma_w_done_7_qs; - logic perf_counter_enable_7_dma_w_done_7_wd; - logic perf_counter_enable_7_dma_w_done_7_we; - logic perf_counter_enable_7_dma_w_bw_7_qs; - logic perf_counter_enable_7_dma_w_bw_7_wd; - logic perf_counter_enable_7_dma_w_bw_7_we; - logic perf_counter_enable_7_dma_b_done_7_qs; - logic perf_counter_enable_7_dma_b_done_7_wd; - logic perf_counter_enable_7_dma_b_done_7_we; - logic perf_counter_enable_7_dma_busy_7_qs; - logic perf_counter_enable_7_dma_busy_7_wd; - logic perf_counter_enable_7_dma_busy_7_we; - logic perf_counter_enable_7_icache_miss_7_qs; - logic perf_counter_enable_7_icache_miss_7_wd; - logic perf_counter_enable_7_icache_miss_7_we; - logic perf_counter_enable_7_icache_hit_7_qs; - logic perf_counter_enable_7_icache_hit_7_wd; - logic perf_counter_enable_7_icache_hit_7_we; - logic perf_counter_enable_7_icache_prefetch_7_qs; - logic perf_counter_enable_7_icache_prefetch_7_wd; - logic perf_counter_enable_7_icache_prefetch_7_we; - logic perf_counter_enable_7_icache_double_hit_7_qs; - logic perf_counter_enable_7_icache_double_hit_7_wd; - logic perf_counter_enable_7_icache_double_hit_7_we; - logic perf_counter_enable_7_icache_stall_7_qs; - logic perf_counter_enable_7_icache_stall_7_wd; - logic perf_counter_enable_7_icache_stall_7_we; - logic perf_counter_enable_8_cycle_8_qs; - logic perf_counter_enable_8_cycle_8_wd; - logic perf_counter_enable_8_cycle_8_we; - logic perf_counter_enable_8_tcdm_accessed_8_qs; - logic perf_counter_enable_8_tcdm_accessed_8_wd; - logic perf_counter_enable_8_tcdm_accessed_8_we; - logic perf_counter_enable_8_tcdm_congested_8_qs; - logic perf_counter_enable_8_tcdm_congested_8_wd; - logic perf_counter_enable_8_tcdm_congested_8_we; - logic perf_counter_enable_8_issue_fpu_8_qs; - logic perf_counter_enable_8_issue_fpu_8_wd; - logic perf_counter_enable_8_issue_fpu_8_we; - logic perf_counter_enable_8_issue_fpu_seq_8_qs; - logic perf_counter_enable_8_issue_fpu_seq_8_wd; - logic perf_counter_enable_8_issue_fpu_seq_8_we; - logic perf_counter_enable_8_issue_core_to_fpu_8_qs; - logic perf_counter_enable_8_issue_core_to_fpu_8_wd; - logic perf_counter_enable_8_issue_core_to_fpu_8_we; - logic perf_counter_enable_8_retired_instr_8_qs; - logic perf_counter_enable_8_retired_instr_8_wd; - logic perf_counter_enable_8_retired_instr_8_we; - logic perf_counter_enable_8_retired_load_8_qs; - logic perf_counter_enable_8_retired_load_8_wd; - logic perf_counter_enable_8_retired_load_8_we; - logic perf_counter_enable_8_retired_i_8_qs; - logic perf_counter_enable_8_retired_i_8_wd; - logic perf_counter_enable_8_retired_i_8_we; - logic perf_counter_enable_8_retired_acc_8_qs; - logic perf_counter_enable_8_retired_acc_8_wd; - logic perf_counter_enable_8_retired_acc_8_we; - logic perf_counter_enable_8_dma_aw_stall_8_qs; - logic perf_counter_enable_8_dma_aw_stall_8_wd; - logic perf_counter_enable_8_dma_aw_stall_8_we; - logic perf_counter_enable_8_dma_ar_stall_8_qs; - logic perf_counter_enable_8_dma_ar_stall_8_wd; - logic perf_counter_enable_8_dma_ar_stall_8_we; - logic perf_counter_enable_8_dma_r_stall_8_qs; - logic perf_counter_enable_8_dma_r_stall_8_wd; - logic perf_counter_enable_8_dma_r_stall_8_we; - logic perf_counter_enable_8_dma_w_stall_8_qs; - logic perf_counter_enable_8_dma_w_stall_8_wd; - logic perf_counter_enable_8_dma_w_stall_8_we; - logic perf_counter_enable_8_dma_buf_w_stall_8_qs; - logic perf_counter_enable_8_dma_buf_w_stall_8_wd; - logic perf_counter_enable_8_dma_buf_w_stall_8_we; - logic perf_counter_enable_8_dma_buf_r_stall_8_qs; - logic perf_counter_enable_8_dma_buf_r_stall_8_wd; - logic perf_counter_enable_8_dma_buf_r_stall_8_we; - logic perf_counter_enable_8_dma_aw_done_8_qs; - logic perf_counter_enable_8_dma_aw_done_8_wd; - logic perf_counter_enable_8_dma_aw_done_8_we; - logic perf_counter_enable_8_dma_aw_bw_8_qs; - logic perf_counter_enable_8_dma_aw_bw_8_wd; - logic perf_counter_enable_8_dma_aw_bw_8_we; - logic perf_counter_enable_8_dma_ar_done_8_qs; - logic perf_counter_enable_8_dma_ar_done_8_wd; - logic perf_counter_enable_8_dma_ar_done_8_we; - logic perf_counter_enable_8_dma_ar_bw_8_qs; - logic perf_counter_enable_8_dma_ar_bw_8_wd; - logic perf_counter_enable_8_dma_ar_bw_8_we; - logic perf_counter_enable_8_dma_r_done_8_qs; - logic perf_counter_enable_8_dma_r_done_8_wd; - logic perf_counter_enable_8_dma_r_done_8_we; - logic perf_counter_enable_8_dma_r_bw_8_qs; - logic perf_counter_enable_8_dma_r_bw_8_wd; - logic perf_counter_enable_8_dma_r_bw_8_we; - logic perf_counter_enable_8_dma_w_done_8_qs; - logic perf_counter_enable_8_dma_w_done_8_wd; - logic perf_counter_enable_8_dma_w_done_8_we; - logic perf_counter_enable_8_dma_w_bw_8_qs; - logic perf_counter_enable_8_dma_w_bw_8_wd; - logic perf_counter_enable_8_dma_w_bw_8_we; - logic perf_counter_enable_8_dma_b_done_8_qs; - logic perf_counter_enable_8_dma_b_done_8_wd; - logic perf_counter_enable_8_dma_b_done_8_we; - logic perf_counter_enable_8_dma_busy_8_qs; - logic perf_counter_enable_8_dma_busy_8_wd; - logic perf_counter_enable_8_dma_busy_8_we; - logic perf_counter_enable_8_icache_miss_8_qs; - logic perf_counter_enable_8_icache_miss_8_wd; - logic perf_counter_enable_8_icache_miss_8_we; - logic perf_counter_enable_8_icache_hit_8_qs; - logic perf_counter_enable_8_icache_hit_8_wd; - logic perf_counter_enable_8_icache_hit_8_we; - logic perf_counter_enable_8_icache_prefetch_8_qs; - logic perf_counter_enable_8_icache_prefetch_8_wd; - logic perf_counter_enable_8_icache_prefetch_8_we; - logic perf_counter_enable_8_icache_double_hit_8_qs; - logic perf_counter_enable_8_icache_double_hit_8_wd; - logic perf_counter_enable_8_icache_double_hit_8_we; - logic perf_counter_enable_8_icache_stall_8_qs; - logic perf_counter_enable_8_icache_stall_8_wd; - logic perf_counter_enable_8_icache_stall_8_we; - logic perf_counter_enable_9_cycle_9_qs; - logic perf_counter_enable_9_cycle_9_wd; - logic perf_counter_enable_9_cycle_9_we; - logic perf_counter_enable_9_tcdm_accessed_9_qs; - logic perf_counter_enable_9_tcdm_accessed_9_wd; - logic perf_counter_enable_9_tcdm_accessed_9_we; - logic perf_counter_enable_9_tcdm_congested_9_qs; - logic perf_counter_enable_9_tcdm_congested_9_wd; - logic perf_counter_enable_9_tcdm_congested_9_we; - logic perf_counter_enable_9_issue_fpu_9_qs; - logic perf_counter_enable_9_issue_fpu_9_wd; - logic perf_counter_enable_9_issue_fpu_9_we; - logic perf_counter_enable_9_issue_fpu_seq_9_qs; - logic perf_counter_enable_9_issue_fpu_seq_9_wd; - logic perf_counter_enable_9_issue_fpu_seq_9_we; - logic perf_counter_enable_9_issue_core_to_fpu_9_qs; - logic perf_counter_enable_9_issue_core_to_fpu_9_wd; - logic perf_counter_enable_9_issue_core_to_fpu_9_we; - logic perf_counter_enable_9_retired_instr_9_qs; - logic perf_counter_enable_9_retired_instr_9_wd; - logic perf_counter_enable_9_retired_instr_9_we; - logic perf_counter_enable_9_retired_load_9_qs; - logic perf_counter_enable_9_retired_load_9_wd; - logic perf_counter_enable_9_retired_load_9_we; - logic perf_counter_enable_9_retired_i_9_qs; - logic perf_counter_enable_9_retired_i_9_wd; - logic perf_counter_enable_9_retired_i_9_we; - logic perf_counter_enable_9_retired_acc_9_qs; - logic perf_counter_enable_9_retired_acc_9_wd; - logic perf_counter_enable_9_retired_acc_9_we; - logic perf_counter_enable_9_dma_aw_stall_9_qs; - logic perf_counter_enable_9_dma_aw_stall_9_wd; - logic perf_counter_enable_9_dma_aw_stall_9_we; - logic perf_counter_enable_9_dma_ar_stall_9_qs; - logic perf_counter_enable_9_dma_ar_stall_9_wd; - logic perf_counter_enable_9_dma_ar_stall_9_we; - logic perf_counter_enable_9_dma_r_stall_9_qs; - logic perf_counter_enable_9_dma_r_stall_9_wd; - logic perf_counter_enable_9_dma_r_stall_9_we; - logic perf_counter_enable_9_dma_w_stall_9_qs; - logic perf_counter_enable_9_dma_w_stall_9_wd; - logic perf_counter_enable_9_dma_w_stall_9_we; - logic perf_counter_enable_9_dma_buf_w_stall_9_qs; - logic perf_counter_enable_9_dma_buf_w_stall_9_wd; - logic perf_counter_enable_9_dma_buf_w_stall_9_we; - logic perf_counter_enable_9_dma_buf_r_stall_9_qs; - logic perf_counter_enable_9_dma_buf_r_stall_9_wd; - logic perf_counter_enable_9_dma_buf_r_stall_9_we; - logic perf_counter_enable_9_dma_aw_done_9_qs; - logic perf_counter_enable_9_dma_aw_done_9_wd; - logic perf_counter_enable_9_dma_aw_done_9_we; - logic perf_counter_enable_9_dma_aw_bw_9_qs; - logic perf_counter_enable_9_dma_aw_bw_9_wd; - logic perf_counter_enable_9_dma_aw_bw_9_we; - logic perf_counter_enable_9_dma_ar_done_9_qs; - logic perf_counter_enable_9_dma_ar_done_9_wd; - logic perf_counter_enable_9_dma_ar_done_9_we; - logic perf_counter_enable_9_dma_ar_bw_9_qs; - logic perf_counter_enable_9_dma_ar_bw_9_wd; - logic perf_counter_enable_9_dma_ar_bw_9_we; - logic perf_counter_enable_9_dma_r_done_9_qs; - logic perf_counter_enable_9_dma_r_done_9_wd; - logic perf_counter_enable_9_dma_r_done_9_we; - logic perf_counter_enable_9_dma_r_bw_9_qs; - logic perf_counter_enable_9_dma_r_bw_9_wd; - logic perf_counter_enable_9_dma_r_bw_9_we; - logic perf_counter_enable_9_dma_w_done_9_qs; - logic perf_counter_enable_9_dma_w_done_9_wd; - logic perf_counter_enable_9_dma_w_done_9_we; - logic perf_counter_enable_9_dma_w_bw_9_qs; - logic perf_counter_enable_9_dma_w_bw_9_wd; - logic perf_counter_enable_9_dma_w_bw_9_we; - logic perf_counter_enable_9_dma_b_done_9_qs; - logic perf_counter_enable_9_dma_b_done_9_wd; - logic perf_counter_enable_9_dma_b_done_9_we; - logic perf_counter_enable_9_dma_busy_9_qs; - logic perf_counter_enable_9_dma_busy_9_wd; - logic perf_counter_enable_9_dma_busy_9_we; - logic perf_counter_enable_9_icache_miss_9_qs; - logic perf_counter_enable_9_icache_miss_9_wd; - logic perf_counter_enable_9_icache_miss_9_we; - logic perf_counter_enable_9_icache_hit_9_qs; - logic perf_counter_enable_9_icache_hit_9_wd; - logic perf_counter_enable_9_icache_hit_9_we; - logic perf_counter_enable_9_icache_prefetch_9_qs; - logic perf_counter_enable_9_icache_prefetch_9_wd; - logic perf_counter_enable_9_icache_prefetch_9_we; - logic perf_counter_enable_9_icache_double_hit_9_qs; - logic perf_counter_enable_9_icache_double_hit_9_wd; - logic perf_counter_enable_9_icache_double_hit_9_we; - logic perf_counter_enable_9_icache_stall_9_qs; - logic perf_counter_enable_9_icache_stall_9_wd; - logic perf_counter_enable_9_icache_stall_9_we; - logic perf_counter_enable_10_cycle_10_qs; - logic perf_counter_enable_10_cycle_10_wd; - logic perf_counter_enable_10_cycle_10_we; - logic perf_counter_enable_10_tcdm_accessed_10_qs; - logic perf_counter_enable_10_tcdm_accessed_10_wd; - logic perf_counter_enable_10_tcdm_accessed_10_we; - logic perf_counter_enable_10_tcdm_congested_10_qs; - logic perf_counter_enable_10_tcdm_congested_10_wd; - logic perf_counter_enable_10_tcdm_congested_10_we; - logic perf_counter_enable_10_issue_fpu_10_qs; - logic perf_counter_enable_10_issue_fpu_10_wd; - logic perf_counter_enable_10_issue_fpu_10_we; - logic perf_counter_enable_10_issue_fpu_seq_10_qs; - logic perf_counter_enable_10_issue_fpu_seq_10_wd; - logic perf_counter_enable_10_issue_fpu_seq_10_we; - logic perf_counter_enable_10_issue_core_to_fpu_10_qs; - logic perf_counter_enable_10_issue_core_to_fpu_10_wd; - logic perf_counter_enable_10_issue_core_to_fpu_10_we; - logic perf_counter_enable_10_retired_instr_10_qs; - logic perf_counter_enable_10_retired_instr_10_wd; - logic perf_counter_enable_10_retired_instr_10_we; - logic perf_counter_enable_10_retired_load_10_qs; - logic perf_counter_enable_10_retired_load_10_wd; - logic perf_counter_enable_10_retired_load_10_we; - logic perf_counter_enable_10_retired_i_10_qs; - logic perf_counter_enable_10_retired_i_10_wd; - logic perf_counter_enable_10_retired_i_10_we; - logic perf_counter_enable_10_retired_acc_10_qs; - logic perf_counter_enable_10_retired_acc_10_wd; - logic perf_counter_enable_10_retired_acc_10_we; - logic perf_counter_enable_10_dma_aw_stall_10_qs; - logic perf_counter_enable_10_dma_aw_stall_10_wd; - logic perf_counter_enable_10_dma_aw_stall_10_we; - logic perf_counter_enable_10_dma_ar_stall_10_qs; - logic perf_counter_enable_10_dma_ar_stall_10_wd; - logic perf_counter_enable_10_dma_ar_stall_10_we; - logic perf_counter_enable_10_dma_r_stall_10_qs; - logic perf_counter_enable_10_dma_r_stall_10_wd; - logic perf_counter_enable_10_dma_r_stall_10_we; - logic perf_counter_enable_10_dma_w_stall_10_qs; - logic perf_counter_enable_10_dma_w_stall_10_wd; - logic perf_counter_enable_10_dma_w_stall_10_we; - logic perf_counter_enable_10_dma_buf_w_stall_10_qs; - logic perf_counter_enable_10_dma_buf_w_stall_10_wd; - logic perf_counter_enable_10_dma_buf_w_stall_10_we; - logic perf_counter_enable_10_dma_buf_r_stall_10_qs; - logic perf_counter_enable_10_dma_buf_r_stall_10_wd; - logic perf_counter_enable_10_dma_buf_r_stall_10_we; - logic perf_counter_enable_10_dma_aw_done_10_qs; - logic perf_counter_enable_10_dma_aw_done_10_wd; - logic perf_counter_enable_10_dma_aw_done_10_we; - logic perf_counter_enable_10_dma_aw_bw_10_qs; - logic perf_counter_enable_10_dma_aw_bw_10_wd; - logic perf_counter_enable_10_dma_aw_bw_10_we; - logic perf_counter_enable_10_dma_ar_done_10_qs; - logic perf_counter_enable_10_dma_ar_done_10_wd; - logic perf_counter_enable_10_dma_ar_done_10_we; - logic perf_counter_enable_10_dma_ar_bw_10_qs; - logic perf_counter_enable_10_dma_ar_bw_10_wd; - logic perf_counter_enable_10_dma_ar_bw_10_we; - logic perf_counter_enable_10_dma_r_done_10_qs; - logic perf_counter_enable_10_dma_r_done_10_wd; - logic perf_counter_enable_10_dma_r_done_10_we; - logic perf_counter_enable_10_dma_r_bw_10_qs; - logic perf_counter_enable_10_dma_r_bw_10_wd; - logic perf_counter_enable_10_dma_r_bw_10_we; - logic perf_counter_enable_10_dma_w_done_10_qs; - logic perf_counter_enable_10_dma_w_done_10_wd; - logic perf_counter_enable_10_dma_w_done_10_we; - logic perf_counter_enable_10_dma_w_bw_10_qs; - logic perf_counter_enable_10_dma_w_bw_10_wd; - logic perf_counter_enable_10_dma_w_bw_10_we; - logic perf_counter_enable_10_dma_b_done_10_qs; - logic perf_counter_enable_10_dma_b_done_10_wd; - logic perf_counter_enable_10_dma_b_done_10_we; - logic perf_counter_enable_10_dma_busy_10_qs; - logic perf_counter_enable_10_dma_busy_10_wd; - logic perf_counter_enable_10_dma_busy_10_we; - logic perf_counter_enable_10_icache_miss_10_qs; - logic perf_counter_enable_10_icache_miss_10_wd; - logic perf_counter_enable_10_icache_miss_10_we; - logic perf_counter_enable_10_icache_hit_10_qs; - logic perf_counter_enable_10_icache_hit_10_wd; - logic perf_counter_enable_10_icache_hit_10_we; - logic perf_counter_enable_10_icache_prefetch_10_qs; - logic perf_counter_enable_10_icache_prefetch_10_wd; - logic perf_counter_enable_10_icache_prefetch_10_we; - logic perf_counter_enable_10_icache_double_hit_10_qs; - logic perf_counter_enable_10_icache_double_hit_10_wd; - logic perf_counter_enable_10_icache_double_hit_10_we; - logic perf_counter_enable_10_icache_stall_10_qs; - logic perf_counter_enable_10_icache_stall_10_wd; - logic perf_counter_enable_10_icache_stall_10_we; - logic perf_counter_enable_11_cycle_11_qs; - logic perf_counter_enable_11_cycle_11_wd; - logic perf_counter_enable_11_cycle_11_we; - logic perf_counter_enable_11_tcdm_accessed_11_qs; - logic perf_counter_enable_11_tcdm_accessed_11_wd; - logic perf_counter_enable_11_tcdm_accessed_11_we; - logic perf_counter_enable_11_tcdm_congested_11_qs; - logic perf_counter_enable_11_tcdm_congested_11_wd; - logic perf_counter_enable_11_tcdm_congested_11_we; - logic perf_counter_enable_11_issue_fpu_11_qs; - logic perf_counter_enable_11_issue_fpu_11_wd; - logic perf_counter_enable_11_issue_fpu_11_we; - logic perf_counter_enable_11_issue_fpu_seq_11_qs; - logic perf_counter_enable_11_issue_fpu_seq_11_wd; - logic perf_counter_enable_11_issue_fpu_seq_11_we; - logic perf_counter_enable_11_issue_core_to_fpu_11_qs; - logic perf_counter_enable_11_issue_core_to_fpu_11_wd; - logic perf_counter_enable_11_issue_core_to_fpu_11_we; - logic perf_counter_enable_11_retired_instr_11_qs; - logic perf_counter_enable_11_retired_instr_11_wd; - logic perf_counter_enable_11_retired_instr_11_we; - logic perf_counter_enable_11_retired_load_11_qs; - logic perf_counter_enable_11_retired_load_11_wd; - logic perf_counter_enable_11_retired_load_11_we; - logic perf_counter_enable_11_retired_i_11_qs; - logic perf_counter_enable_11_retired_i_11_wd; - logic perf_counter_enable_11_retired_i_11_we; - logic perf_counter_enable_11_retired_acc_11_qs; - logic perf_counter_enable_11_retired_acc_11_wd; - logic perf_counter_enable_11_retired_acc_11_we; - logic perf_counter_enable_11_dma_aw_stall_11_qs; - logic perf_counter_enable_11_dma_aw_stall_11_wd; - logic perf_counter_enable_11_dma_aw_stall_11_we; - logic perf_counter_enable_11_dma_ar_stall_11_qs; - logic perf_counter_enable_11_dma_ar_stall_11_wd; - logic perf_counter_enable_11_dma_ar_stall_11_we; - logic perf_counter_enable_11_dma_r_stall_11_qs; - logic perf_counter_enable_11_dma_r_stall_11_wd; - logic perf_counter_enable_11_dma_r_stall_11_we; - logic perf_counter_enable_11_dma_w_stall_11_qs; - logic perf_counter_enable_11_dma_w_stall_11_wd; - logic perf_counter_enable_11_dma_w_stall_11_we; - logic perf_counter_enable_11_dma_buf_w_stall_11_qs; - logic perf_counter_enable_11_dma_buf_w_stall_11_wd; - logic perf_counter_enable_11_dma_buf_w_stall_11_we; - logic perf_counter_enable_11_dma_buf_r_stall_11_qs; - logic perf_counter_enable_11_dma_buf_r_stall_11_wd; - logic perf_counter_enable_11_dma_buf_r_stall_11_we; - logic perf_counter_enable_11_dma_aw_done_11_qs; - logic perf_counter_enable_11_dma_aw_done_11_wd; - logic perf_counter_enable_11_dma_aw_done_11_we; - logic perf_counter_enable_11_dma_aw_bw_11_qs; - logic perf_counter_enable_11_dma_aw_bw_11_wd; - logic perf_counter_enable_11_dma_aw_bw_11_we; - logic perf_counter_enable_11_dma_ar_done_11_qs; - logic perf_counter_enable_11_dma_ar_done_11_wd; - logic perf_counter_enable_11_dma_ar_done_11_we; - logic perf_counter_enable_11_dma_ar_bw_11_qs; - logic perf_counter_enable_11_dma_ar_bw_11_wd; - logic perf_counter_enable_11_dma_ar_bw_11_we; - logic perf_counter_enable_11_dma_r_done_11_qs; - logic perf_counter_enable_11_dma_r_done_11_wd; - logic perf_counter_enable_11_dma_r_done_11_we; - logic perf_counter_enable_11_dma_r_bw_11_qs; - logic perf_counter_enable_11_dma_r_bw_11_wd; - logic perf_counter_enable_11_dma_r_bw_11_we; - logic perf_counter_enable_11_dma_w_done_11_qs; - logic perf_counter_enable_11_dma_w_done_11_wd; - logic perf_counter_enable_11_dma_w_done_11_we; - logic perf_counter_enable_11_dma_w_bw_11_qs; - logic perf_counter_enable_11_dma_w_bw_11_wd; - logic perf_counter_enable_11_dma_w_bw_11_we; - logic perf_counter_enable_11_dma_b_done_11_qs; - logic perf_counter_enable_11_dma_b_done_11_wd; - logic perf_counter_enable_11_dma_b_done_11_we; - logic perf_counter_enable_11_dma_busy_11_qs; - logic perf_counter_enable_11_dma_busy_11_wd; - logic perf_counter_enable_11_dma_busy_11_we; - logic perf_counter_enable_11_icache_miss_11_qs; - logic perf_counter_enable_11_icache_miss_11_wd; - logic perf_counter_enable_11_icache_miss_11_we; - logic perf_counter_enable_11_icache_hit_11_qs; - logic perf_counter_enable_11_icache_hit_11_wd; - logic perf_counter_enable_11_icache_hit_11_we; - logic perf_counter_enable_11_icache_prefetch_11_qs; - logic perf_counter_enable_11_icache_prefetch_11_wd; - logic perf_counter_enable_11_icache_prefetch_11_we; - logic perf_counter_enable_11_icache_double_hit_11_qs; - logic perf_counter_enable_11_icache_double_hit_11_wd; - logic perf_counter_enable_11_icache_double_hit_11_we; - logic perf_counter_enable_11_icache_stall_11_qs; - logic perf_counter_enable_11_icache_stall_11_wd; - logic perf_counter_enable_11_icache_stall_11_we; - logic perf_counter_enable_12_cycle_12_qs; - logic perf_counter_enable_12_cycle_12_wd; - logic perf_counter_enable_12_cycle_12_we; - logic perf_counter_enable_12_tcdm_accessed_12_qs; - logic perf_counter_enable_12_tcdm_accessed_12_wd; - logic perf_counter_enable_12_tcdm_accessed_12_we; - logic perf_counter_enable_12_tcdm_congested_12_qs; - logic perf_counter_enable_12_tcdm_congested_12_wd; - logic perf_counter_enable_12_tcdm_congested_12_we; - logic perf_counter_enable_12_issue_fpu_12_qs; - logic perf_counter_enable_12_issue_fpu_12_wd; - logic perf_counter_enable_12_issue_fpu_12_we; - logic perf_counter_enable_12_issue_fpu_seq_12_qs; - logic perf_counter_enable_12_issue_fpu_seq_12_wd; - logic perf_counter_enable_12_issue_fpu_seq_12_we; - logic perf_counter_enable_12_issue_core_to_fpu_12_qs; - logic perf_counter_enable_12_issue_core_to_fpu_12_wd; - logic perf_counter_enable_12_issue_core_to_fpu_12_we; - logic perf_counter_enable_12_retired_instr_12_qs; - logic perf_counter_enable_12_retired_instr_12_wd; - logic perf_counter_enable_12_retired_instr_12_we; - logic perf_counter_enable_12_retired_load_12_qs; - logic perf_counter_enable_12_retired_load_12_wd; - logic perf_counter_enable_12_retired_load_12_we; - logic perf_counter_enable_12_retired_i_12_qs; - logic perf_counter_enable_12_retired_i_12_wd; - logic perf_counter_enable_12_retired_i_12_we; - logic perf_counter_enable_12_retired_acc_12_qs; - logic perf_counter_enable_12_retired_acc_12_wd; - logic perf_counter_enable_12_retired_acc_12_we; - logic perf_counter_enable_12_dma_aw_stall_12_qs; - logic perf_counter_enable_12_dma_aw_stall_12_wd; - logic perf_counter_enable_12_dma_aw_stall_12_we; - logic perf_counter_enable_12_dma_ar_stall_12_qs; - logic perf_counter_enable_12_dma_ar_stall_12_wd; - logic perf_counter_enable_12_dma_ar_stall_12_we; - logic perf_counter_enable_12_dma_r_stall_12_qs; - logic perf_counter_enable_12_dma_r_stall_12_wd; - logic perf_counter_enable_12_dma_r_stall_12_we; - logic perf_counter_enable_12_dma_w_stall_12_qs; - logic perf_counter_enable_12_dma_w_stall_12_wd; - logic perf_counter_enable_12_dma_w_stall_12_we; - logic perf_counter_enable_12_dma_buf_w_stall_12_qs; - logic perf_counter_enable_12_dma_buf_w_stall_12_wd; - logic perf_counter_enable_12_dma_buf_w_stall_12_we; - logic perf_counter_enable_12_dma_buf_r_stall_12_qs; - logic perf_counter_enable_12_dma_buf_r_stall_12_wd; - logic perf_counter_enable_12_dma_buf_r_stall_12_we; - logic perf_counter_enable_12_dma_aw_done_12_qs; - logic perf_counter_enable_12_dma_aw_done_12_wd; - logic perf_counter_enable_12_dma_aw_done_12_we; - logic perf_counter_enable_12_dma_aw_bw_12_qs; - logic perf_counter_enable_12_dma_aw_bw_12_wd; - logic perf_counter_enable_12_dma_aw_bw_12_we; - logic perf_counter_enable_12_dma_ar_done_12_qs; - logic perf_counter_enable_12_dma_ar_done_12_wd; - logic perf_counter_enable_12_dma_ar_done_12_we; - logic perf_counter_enable_12_dma_ar_bw_12_qs; - logic perf_counter_enable_12_dma_ar_bw_12_wd; - logic perf_counter_enable_12_dma_ar_bw_12_we; - logic perf_counter_enable_12_dma_r_done_12_qs; - logic perf_counter_enable_12_dma_r_done_12_wd; - logic perf_counter_enable_12_dma_r_done_12_we; - logic perf_counter_enable_12_dma_r_bw_12_qs; - logic perf_counter_enable_12_dma_r_bw_12_wd; - logic perf_counter_enable_12_dma_r_bw_12_we; - logic perf_counter_enable_12_dma_w_done_12_qs; - logic perf_counter_enable_12_dma_w_done_12_wd; - logic perf_counter_enable_12_dma_w_done_12_we; - logic perf_counter_enable_12_dma_w_bw_12_qs; - logic perf_counter_enable_12_dma_w_bw_12_wd; - logic perf_counter_enable_12_dma_w_bw_12_we; - logic perf_counter_enable_12_dma_b_done_12_qs; - logic perf_counter_enable_12_dma_b_done_12_wd; - logic perf_counter_enable_12_dma_b_done_12_we; - logic perf_counter_enable_12_dma_busy_12_qs; - logic perf_counter_enable_12_dma_busy_12_wd; - logic perf_counter_enable_12_dma_busy_12_we; - logic perf_counter_enable_12_icache_miss_12_qs; - logic perf_counter_enable_12_icache_miss_12_wd; - logic perf_counter_enable_12_icache_miss_12_we; - logic perf_counter_enable_12_icache_hit_12_qs; - logic perf_counter_enable_12_icache_hit_12_wd; - logic perf_counter_enable_12_icache_hit_12_we; - logic perf_counter_enable_12_icache_prefetch_12_qs; - logic perf_counter_enable_12_icache_prefetch_12_wd; - logic perf_counter_enable_12_icache_prefetch_12_we; - logic perf_counter_enable_12_icache_double_hit_12_qs; - logic perf_counter_enable_12_icache_double_hit_12_wd; - logic perf_counter_enable_12_icache_double_hit_12_we; - logic perf_counter_enable_12_icache_stall_12_qs; - logic perf_counter_enable_12_icache_stall_12_wd; - logic perf_counter_enable_12_icache_stall_12_we; - logic perf_counter_enable_13_cycle_13_qs; - logic perf_counter_enable_13_cycle_13_wd; - logic perf_counter_enable_13_cycle_13_we; - logic perf_counter_enable_13_tcdm_accessed_13_qs; - logic perf_counter_enable_13_tcdm_accessed_13_wd; - logic perf_counter_enable_13_tcdm_accessed_13_we; - logic perf_counter_enable_13_tcdm_congested_13_qs; - logic perf_counter_enable_13_tcdm_congested_13_wd; - logic perf_counter_enable_13_tcdm_congested_13_we; - logic perf_counter_enable_13_issue_fpu_13_qs; - logic perf_counter_enable_13_issue_fpu_13_wd; - logic perf_counter_enable_13_issue_fpu_13_we; - logic perf_counter_enable_13_issue_fpu_seq_13_qs; - logic perf_counter_enable_13_issue_fpu_seq_13_wd; - logic perf_counter_enable_13_issue_fpu_seq_13_we; - logic perf_counter_enable_13_issue_core_to_fpu_13_qs; - logic perf_counter_enable_13_issue_core_to_fpu_13_wd; - logic perf_counter_enable_13_issue_core_to_fpu_13_we; - logic perf_counter_enable_13_retired_instr_13_qs; - logic perf_counter_enable_13_retired_instr_13_wd; - logic perf_counter_enable_13_retired_instr_13_we; - logic perf_counter_enable_13_retired_load_13_qs; - logic perf_counter_enable_13_retired_load_13_wd; - logic perf_counter_enable_13_retired_load_13_we; - logic perf_counter_enable_13_retired_i_13_qs; - logic perf_counter_enable_13_retired_i_13_wd; - logic perf_counter_enable_13_retired_i_13_we; - logic perf_counter_enable_13_retired_acc_13_qs; - logic perf_counter_enable_13_retired_acc_13_wd; - logic perf_counter_enable_13_retired_acc_13_we; - logic perf_counter_enable_13_dma_aw_stall_13_qs; - logic perf_counter_enable_13_dma_aw_stall_13_wd; - logic perf_counter_enable_13_dma_aw_stall_13_we; - logic perf_counter_enable_13_dma_ar_stall_13_qs; - logic perf_counter_enable_13_dma_ar_stall_13_wd; - logic perf_counter_enable_13_dma_ar_stall_13_we; - logic perf_counter_enable_13_dma_r_stall_13_qs; - logic perf_counter_enable_13_dma_r_stall_13_wd; - logic perf_counter_enable_13_dma_r_stall_13_we; - logic perf_counter_enable_13_dma_w_stall_13_qs; - logic perf_counter_enable_13_dma_w_stall_13_wd; - logic perf_counter_enable_13_dma_w_stall_13_we; - logic perf_counter_enable_13_dma_buf_w_stall_13_qs; - logic perf_counter_enable_13_dma_buf_w_stall_13_wd; - logic perf_counter_enable_13_dma_buf_w_stall_13_we; - logic perf_counter_enable_13_dma_buf_r_stall_13_qs; - logic perf_counter_enable_13_dma_buf_r_stall_13_wd; - logic perf_counter_enable_13_dma_buf_r_stall_13_we; - logic perf_counter_enable_13_dma_aw_done_13_qs; - logic perf_counter_enable_13_dma_aw_done_13_wd; - logic perf_counter_enable_13_dma_aw_done_13_we; - logic perf_counter_enable_13_dma_aw_bw_13_qs; - logic perf_counter_enable_13_dma_aw_bw_13_wd; - logic perf_counter_enable_13_dma_aw_bw_13_we; - logic perf_counter_enable_13_dma_ar_done_13_qs; - logic perf_counter_enable_13_dma_ar_done_13_wd; - logic perf_counter_enable_13_dma_ar_done_13_we; - logic perf_counter_enable_13_dma_ar_bw_13_qs; - logic perf_counter_enable_13_dma_ar_bw_13_wd; - logic perf_counter_enable_13_dma_ar_bw_13_we; - logic perf_counter_enable_13_dma_r_done_13_qs; - logic perf_counter_enable_13_dma_r_done_13_wd; - logic perf_counter_enable_13_dma_r_done_13_we; - logic perf_counter_enable_13_dma_r_bw_13_qs; - logic perf_counter_enable_13_dma_r_bw_13_wd; - logic perf_counter_enable_13_dma_r_bw_13_we; - logic perf_counter_enable_13_dma_w_done_13_qs; - logic perf_counter_enable_13_dma_w_done_13_wd; - logic perf_counter_enable_13_dma_w_done_13_we; - logic perf_counter_enable_13_dma_w_bw_13_qs; - logic perf_counter_enable_13_dma_w_bw_13_wd; - logic perf_counter_enable_13_dma_w_bw_13_we; - logic perf_counter_enable_13_dma_b_done_13_qs; - logic perf_counter_enable_13_dma_b_done_13_wd; - logic perf_counter_enable_13_dma_b_done_13_we; - logic perf_counter_enable_13_dma_busy_13_qs; - logic perf_counter_enable_13_dma_busy_13_wd; - logic perf_counter_enable_13_dma_busy_13_we; - logic perf_counter_enable_13_icache_miss_13_qs; - logic perf_counter_enable_13_icache_miss_13_wd; - logic perf_counter_enable_13_icache_miss_13_we; - logic perf_counter_enable_13_icache_hit_13_qs; - logic perf_counter_enable_13_icache_hit_13_wd; - logic perf_counter_enable_13_icache_hit_13_we; - logic perf_counter_enable_13_icache_prefetch_13_qs; - logic perf_counter_enable_13_icache_prefetch_13_wd; - logic perf_counter_enable_13_icache_prefetch_13_we; - logic perf_counter_enable_13_icache_double_hit_13_qs; - logic perf_counter_enable_13_icache_double_hit_13_wd; - logic perf_counter_enable_13_icache_double_hit_13_we; - logic perf_counter_enable_13_icache_stall_13_qs; - logic perf_counter_enable_13_icache_stall_13_wd; - logic perf_counter_enable_13_icache_stall_13_we; - logic perf_counter_enable_14_cycle_14_qs; - logic perf_counter_enable_14_cycle_14_wd; - logic perf_counter_enable_14_cycle_14_we; - logic perf_counter_enable_14_tcdm_accessed_14_qs; - logic perf_counter_enable_14_tcdm_accessed_14_wd; - logic perf_counter_enable_14_tcdm_accessed_14_we; - logic perf_counter_enable_14_tcdm_congested_14_qs; - logic perf_counter_enable_14_tcdm_congested_14_wd; - logic perf_counter_enable_14_tcdm_congested_14_we; - logic perf_counter_enable_14_issue_fpu_14_qs; - logic perf_counter_enable_14_issue_fpu_14_wd; - logic perf_counter_enable_14_issue_fpu_14_we; - logic perf_counter_enable_14_issue_fpu_seq_14_qs; - logic perf_counter_enable_14_issue_fpu_seq_14_wd; - logic perf_counter_enable_14_issue_fpu_seq_14_we; - logic perf_counter_enable_14_issue_core_to_fpu_14_qs; - logic perf_counter_enable_14_issue_core_to_fpu_14_wd; - logic perf_counter_enable_14_issue_core_to_fpu_14_we; - logic perf_counter_enable_14_retired_instr_14_qs; - logic perf_counter_enable_14_retired_instr_14_wd; - logic perf_counter_enable_14_retired_instr_14_we; - logic perf_counter_enable_14_retired_load_14_qs; - logic perf_counter_enable_14_retired_load_14_wd; - logic perf_counter_enable_14_retired_load_14_we; - logic perf_counter_enable_14_retired_i_14_qs; - logic perf_counter_enable_14_retired_i_14_wd; - logic perf_counter_enable_14_retired_i_14_we; - logic perf_counter_enable_14_retired_acc_14_qs; - logic perf_counter_enable_14_retired_acc_14_wd; - logic perf_counter_enable_14_retired_acc_14_we; - logic perf_counter_enable_14_dma_aw_stall_14_qs; - logic perf_counter_enable_14_dma_aw_stall_14_wd; - logic perf_counter_enable_14_dma_aw_stall_14_we; - logic perf_counter_enable_14_dma_ar_stall_14_qs; - logic perf_counter_enable_14_dma_ar_stall_14_wd; - logic perf_counter_enable_14_dma_ar_stall_14_we; - logic perf_counter_enable_14_dma_r_stall_14_qs; - logic perf_counter_enable_14_dma_r_stall_14_wd; - logic perf_counter_enable_14_dma_r_stall_14_we; - logic perf_counter_enable_14_dma_w_stall_14_qs; - logic perf_counter_enable_14_dma_w_stall_14_wd; - logic perf_counter_enable_14_dma_w_stall_14_we; - logic perf_counter_enable_14_dma_buf_w_stall_14_qs; - logic perf_counter_enable_14_dma_buf_w_stall_14_wd; - logic perf_counter_enable_14_dma_buf_w_stall_14_we; - logic perf_counter_enable_14_dma_buf_r_stall_14_qs; - logic perf_counter_enable_14_dma_buf_r_stall_14_wd; - logic perf_counter_enable_14_dma_buf_r_stall_14_we; - logic perf_counter_enable_14_dma_aw_done_14_qs; - logic perf_counter_enable_14_dma_aw_done_14_wd; - logic perf_counter_enable_14_dma_aw_done_14_we; - logic perf_counter_enable_14_dma_aw_bw_14_qs; - logic perf_counter_enable_14_dma_aw_bw_14_wd; - logic perf_counter_enable_14_dma_aw_bw_14_we; - logic perf_counter_enable_14_dma_ar_done_14_qs; - logic perf_counter_enable_14_dma_ar_done_14_wd; - logic perf_counter_enable_14_dma_ar_done_14_we; - logic perf_counter_enable_14_dma_ar_bw_14_qs; - logic perf_counter_enable_14_dma_ar_bw_14_wd; - logic perf_counter_enable_14_dma_ar_bw_14_we; - logic perf_counter_enable_14_dma_r_done_14_qs; - logic perf_counter_enable_14_dma_r_done_14_wd; - logic perf_counter_enable_14_dma_r_done_14_we; - logic perf_counter_enable_14_dma_r_bw_14_qs; - logic perf_counter_enable_14_dma_r_bw_14_wd; - logic perf_counter_enable_14_dma_r_bw_14_we; - logic perf_counter_enable_14_dma_w_done_14_qs; - logic perf_counter_enable_14_dma_w_done_14_wd; - logic perf_counter_enable_14_dma_w_done_14_we; - logic perf_counter_enable_14_dma_w_bw_14_qs; - logic perf_counter_enable_14_dma_w_bw_14_wd; - logic perf_counter_enable_14_dma_w_bw_14_we; - logic perf_counter_enable_14_dma_b_done_14_qs; - logic perf_counter_enable_14_dma_b_done_14_wd; - logic perf_counter_enable_14_dma_b_done_14_we; - logic perf_counter_enable_14_dma_busy_14_qs; - logic perf_counter_enable_14_dma_busy_14_wd; - logic perf_counter_enable_14_dma_busy_14_we; - logic perf_counter_enable_14_icache_miss_14_qs; - logic perf_counter_enable_14_icache_miss_14_wd; - logic perf_counter_enable_14_icache_miss_14_we; - logic perf_counter_enable_14_icache_hit_14_qs; - logic perf_counter_enable_14_icache_hit_14_wd; - logic perf_counter_enable_14_icache_hit_14_we; - logic perf_counter_enable_14_icache_prefetch_14_qs; - logic perf_counter_enable_14_icache_prefetch_14_wd; - logic perf_counter_enable_14_icache_prefetch_14_we; - logic perf_counter_enable_14_icache_double_hit_14_qs; - logic perf_counter_enable_14_icache_double_hit_14_wd; - logic perf_counter_enable_14_icache_double_hit_14_we; - logic perf_counter_enable_14_icache_stall_14_qs; - logic perf_counter_enable_14_icache_stall_14_wd; - logic perf_counter_enable_14_icache_stall_14_we; - logic perf_counter_enable_15_cycle_15_qs; - logic perf_counter_enable_15_cycle_15_wd; - logic perf_counter_enable_15_cycle_15_we; - logic perf_counter_enable_15_tcdm_accessed_15_qs; - logic perf_counter_enable_15_tcdm_accessed_15_wd; - logic perf_counter_enable_15_tcdm_accessed_15_we; - logic perf_counter_enable_15_tcdm_congested_15_qs; - logic perf_counter_enable_15_tcdm_congested_15_wd; - logic perf_counter_enable_15_tcdm_congested_15_we; - logic perf_counter_enable_15_issue_fpu_15_qs; - logic perf_counter_enable_15_issue_fpu_15_wd; - logic perf_counter_enable_15_issue_fpu_15_we; - logic perf_counter_enable_15_issue_fpu_seq_15_qs; - logic perf_counter_enable_15_issue_fpu_seq_15_wd; - logic perf_counter_enable_15_issue_fpu_seq_15_we; - logic perf_counter_enable_15_issue_core_to_fpu_15_qs; - logic perf_counter_enable_15_issue_core_to_fpu_15_wd; - logic perf_counter_enable_15_issue_core_to_fpu_15_we; - logic perf_counter_enable_15_retired_instr_15_qs; - logic perf_counter_enable_15_retired_instr_15_wd; - logic perf_counter_enable_15_retired_instr_15_we; - logic perf_counter_enable_15_retired_load_15_qs; - logic perf_counter_enable_15_retired_load_15_wd; - logic perf_counter_enable_15_retired_load_15_we; - logic perf_counter_enable_15_retired_i_15_qs; - logic perf_counter_enable_15_retired_i_15_wd; - logic perf_counter_enable_15_retired_i_15_we; - logic perf_counter_enable_15_retired_acc_15_qs; - logic perf_counter_enable_15_retired_acc_15_wd; - logic perf_counter_enable_15_retired_acc_15_we; - logic perf_counter_enable_15_dma_aw_stall_15_qs; - logic perf_counter_enable_15_dma_aw_stall_15_wd; - logic perf_counter_enable_15_dma_aw_stall_15_we; - logic perf_counter_enable_15_dma_ar_stall_15_qs; - logic perf_counter_enable_15_dma_ar_stall_15_wd; - logic perf_counter_enable_15_dma_ar_stall_15_we; - logic perf_counter_enable_15_dma_r_stall_15_qs; - logic perf_counter_enable_15_dma_r_stall_15_wd; - logic perf_counter_enable_15_dma_r_stall_15_we; - logic perf_counter_enable_15_dma_w_stall_15_qs; - logic perf_counter_enable_15_dma_w_stall_15_wd; - logic perf_counter_enable_15_dma_w_stall_15_we; - logic perf_counter_enable_15_dma_buf_w_stall_15_qs; - logic perf_counter_enable_15_dma_buf_w_stall_15_wd; - logic perf_counter_enable_15_dma_buf_w_stall_15_we; - logic perf_counter_enable_15_dma_buf_r_stall_15_qs; - logic perf_counter_enable_15_dma_buf_r_stall_15_wd; - logic perf_counter_enable_15_dma_buf_r_stall_15_we; - logic perf_counter_enable_15_dma_aw_done_15_qs; - logic perf_counter_enable_15_dma_aw_done_15_wd; - logic perf_counter_enable_15_dma_aw_done_15_we; - logic perf_counter_enable_15_dma_aw_bw_15_qs; - logic perf_counter_enable_15_dma_aw_bw_15_wd; - logic perf_counter_enable_15_dma_aw_bw_15_we; - logic perf_counter_enable_15_dma_ar_done_15_qs; - logic perf_counter_enable_15_dma_ar_done_15_wd; - logic perf_counter_enable_15_dma_ar_done_15_we; - logic perf_counter_enable_15_dma_ar_bw_15_qs; - logic perf_counter_enable_15_dma_ar_bw_15_wd; - logic perf_counter_enable_15_dma_ar_bw_15_we; - logic perf_counter_enable_15_dma_r_done_15_qs; - logic perf_counter_enable_15_dma_r_done_15_wd; - logic perf_counter_enable_15_dma_r_done_15_we; - logic perf_counter_enable_15_dma_r_bw_15_qs; - logic perf_counter_enable_15_dma_r_bw_15_wd; - logic perf_counter_enable_15_dma_r_bw_15_we; - logic perf_counter_enable_15_dma_w_done_15_qs; - logic perf_counter_enable_15_dma_w_done_15_wd; - logic perf_counter_enable_15_dma_w_done_15_we; - logic perf_counter_enable_15_dma_w_bw_15_qs; - logic perf_counter_enable_15_dma_w_bw_15_wd; - logic perf_counter_enable_15_dma_w_bw_15_we; - logic perf_counter_enable_15_dma_b_done_15_qs; - logic perf_counter_enable_15_dma_b_done_15_wd; - logic perf_counter_enable_15_dma_b_done_15_we; - logic perf_counter_enable_15_dma_busy_15_qs; - logic perf_counter_enable_15_dma_busy_15_wd; - logic perf_counter_enable_15_dma_busy_15_we; - logic perf_counter_enable_15_icache_miss_15_qs; - logic perf_counter_enable_15_icache_miss_15_wd; - logic perf_counter_enable_15_icache_miss_15_we; - logic perf_counter_enable_15_icache_hit_15_qs; - logic perf_counter_enable_15_icache_hit_15_wd; - logic perf_counter_enable_15_icache_hit_15_we; - logic perf_counter_enable_15_icache_prefetch_15_qs; - logic perf_counter_enable_15_icache_prefetch_15_wd; - logic perf_counter_enable_15_icache_prefetch_15_we; - logic perf_counter_enable_15_icache_double_hit_15_qs; - logic perf_counter_enable_15_icache_double_hit_15_wd; - logic perf_counter_enable_15_icache_double_hit_15_we; - logic perf_counter_enable_15_icache_stall_15_qs; - logic perf_counter_enable_15_icache_stall_15_wd; - logic perf_counter_enable_15_icache_stall_15_we; - logic [9:0] hart_select_0_qs; - logic [9:0] hart_select_0_wd; - logic hart_select_0_we; - logic [9:0] hart_select_1_qs; - logic [9:0] hart_select_1_wd; - logic hart_select_1_we; - logic [9:0] hart_select_2_qs; - logic [9:0] hart_select_2_wd; - logic hart_select_2_we; - logic [9:0] hart_select_3_qs; - logic [9:0] hart_select_3_wd; - logic hart_select_3_we; - logic [9:0] hart_select_4_qs; - logic [9:0] hart_select_4_wd; - logic hart_select_4_we; - logic [9:0] hart_select_5_qs; - logic [9:0] hart_select_5_wd; - logic hart_select_5_we; - logic [9:0] hart_select_6_qs; - logic [9:0] hart_select_6_wd; - logic hart_select_6_we; - logic [9:0] hart_select_7_qs; - logic [9:0] hart_select_7_wd; - logic hart_select_7_we; - logic [9:0] hart_select_8_qs; - logic [9:0] hart_select_8_wd; - logic hart_select_8_we; - logic [9:0] hart_select_9_qs; - logic [9:0] hart_select_9_wd; - logic hart_select_9_we; - logic [9:0] hart_select_10_qs; - logic [9:0] hart_select_10_wd; - logic hart_select_10_we; - logic [9:0] hart_select_11_qs; - logic [9:0] hart_select_11_wd; - logic hart_select_11_we; - logic [9:0] hart_select_12_qs; - logic [9:0] hart_select_12_wd; - logic hart_select_12_we; - logic [9:0] hart_select_13_qs; - logic [9:0] hart_select_13_wd; - logic hart_select_13_we; - logic [9:0] hart_select_14_qs; - logic [9:0] hart_select_14_wd; - logic hart_select_14_we; - logic [9:0] hart_select_15_qs; - logic [9:0] hart_select_15_wd; - logic hart_select_15_we; - logic [47:0] perf_counter_0_qs; - logic [47:0] perf_counter_0_wd; - logic perf_counter_0_we; - logic perf_counter_0_re; - logic [47:0] perf_counter_1_qs; - logic [47:0] perf_counter_1_wd; - logic perf_counter_1_we; - logic perf_counter_1_re; - logic [47:0] perf_counter_2_qs; - logic [47:0] perf_counter_2_wd; - logic perf_counter_2_we; - logic perf_counter_2_re; - logic [47:0] perf_counter_3_qs; - logic [47:0] perf_counter_3_wd; - logic perf_counter_3_we; - logic perf_counter_3_re; - logic [47:0] perf_counter_4_qs; - logic [47:0] perf_counter_4_wd; - logic perf_counter_4_we; - logic perf_counter_4_re; - logic [47:0] perf_counter_5_qs; - logic [47:0] perf_counter_5_wd; - logic perf_counter_5_we; - logic perf_counter_5_re; - logic [47:0] perf_counter_6_qs; - logic [47:0] perf_counter_6_wd; - logic perf_counter_6_we; - logic perf_counter_6_re; - logic [47:0] perf_counter_7_qs; - logic [47:0] perf_counter_7_wd; - logic perf_counter_7_we; - logic perf_counter_7_re; - logic [47:0] perf_counter_8_qs; - logic [47:0] perf_counter_8_wd; - logic perf_counter_8_we; - logic perf_counter_8_re; - logic [47:0] perf_counter_9_qs; - logic [47:0] perf_counter_9_wd; - logic perf_counter_9_we; - logic perf_counter_9_re; - logic [47:0] perf_counter_10_qs; - logic [47:0] perf_counter_10_wd; - logic perf_counter_10_we; - logic perf_counter_10_re; - logic [47:0] perf_counter_11_qs; - logic [47:0] perf_counter_11_wd; - logic perf_counter_11_we; - logic perf_counter_11_re; - logic [47:0] perf_counter_12_qs; - logic [47:0] perf_counter_12_wd; - logic perf_counter_12_we; - logic perf_counter_12_re; - logic [47:0] perf_counter_13_qs; - logic [47:0] perf_counter_13_wd; - logic perf_counter_13_we; - logic perf_counter_13_re; - logic [47:0] perf_counter_14_qs; - logic [47:0] perf_counter_14_wd; - logic perf_counter_14_we; - logic perf_counter_14_re; - logic [47:0] perf_counter_15_qs; - logic [47:0] perf_counter_15_wd; - logic perf_counter_15_we; - logic perf_counter_15_re; + logic perf_cnt_en_0_qs; + logic perf_cnt_en_0_wd; + logic perf_cnt_en_0_we; + logic perf_cnt_en_1_qs; + logic perf_cnt_en_1_wd; + logic perf_cnt_en_1_we; + logic perf_cnt_en_2_qs; + logic perf_cnt_en_2_wd; + logic perf_cnt_en_2_we; + logic perf_cnt_en_3_qs; + logic perf_cnt_en_3_wd; + logic perf_cnt_en_3_we; + logic perf_cnt_en_4_qs; + logic perf_cnt_en_4_wd; + logic perf_cnt_en_4_we; + logic perf_cnt_en_5_qs; + logic perf_cnt_en_5_wd; + logic perf_cnt_en_5_we; + logic perf_cnt_en_6_qs; + logic perf_cnt_en_6_wd; + logic perf_cnt_en_6_we; + logic perf_cnt_en_7_qs; + logic perf_cnt_en_7_wd; + logic perf_cnt_en_7_we; + logic perf_cnt_en_8_qs; + logic perf_cnt_en_8_wd; + logic perf_cnt_en_8_we; + logic perf_cnt_en_9_qs; + logic perf_cnt_en_9_wd; + logic perf_cnt_en_9_we; + logic perf_cnt_en_10_qs; + logic perf_cnt_en_10_wd; + logic perf_cnt_en_10_we; + logic perf_cnt_en_11_qs; + logic perf_cnt_en_11_wd; + logic perf_cnt_en_11_we; + logic perf_cnt_en_12_qs; + logic perf_cnt_en_12_wd; + logic perf_cnt_en_12_we; + logic perf_cnt_en_13_qs; + logic perf_cnt_en_13_wd; + logic perf_cnt_en_13_we; + logic perf_cnt_en_14_qs; + logic perf_cnt_en_14_wd; + logic perf_cnt_en_14_we; + logic perf_cnt_en_15_qs; + logic perf_cnt_en_15_wd; + logic perf_cnt_en_15_we; + logic [15:0] perf_cnt_sel_0_hart_0_qs; + logic [15:0] perf_cnt_sel_0_hart_0_wd; + logic perf_cnt_sel_0_hart_0_we; + logic perf_cnt_sel_0_hart_0_re; + logic [15:0] perf_cnt_sel_0_metric_0_qs; + logic [15:0] perf_cnt_sel_0_metric_0_wd; + logic perf_cnt_sel_0_metric_0_we; + logic perf_cnt_sel_0_metric_0_re; + logic [15:0] perf_cnt_sel_1_hart_1_qs; + logic [15:0] perf_cnt_sel_1_hart_1_wd; + logic perf_cnt_sel_1_hart_1_we; + logic perf_cnt_sel_1_hart_1_re; + logic [15:0] perf_cnt_sel_1_metric_1_qs; + logic [15:0] perf_cnt_sel_1_metric_1_wd; + logic perf_cnt_sel_1_metric_1_we; + logic perf_cnt_sel_1_metric_1_re; + logic [15:0] perf_cnt_sel_2_hart_2_qs; + logic [15:0] perf_cnt_sel_2_hart_2_wd; + logic perf_cnt_sel_2_hart_2_we; + logic perf_cnt_sel_2_hart_2_re; + logic [15:0] perf_cnt_sel_2_metric_2_qs; + logic [15:0] perf_cnt_sel_2_metric_2_wd; + logic perf_cnt_sel_2_metric_2_we; + logic perf_cnt_sel_2_metric_2_re; + logic [15:0] perf_cnt_sel_3_hart_3_qs; + logic [15:0] perf_cnt_sel_3_hart_3_wd; + logic perf_cnt_sel_3_hart_3_we; + logic perf_cnt_sel_3_hart_3_re; + logic [15:0] perf_cnt_sel_3_metric_3_qs; + logic [15:0] perf_cnt_sel_3_metric_3_wd; + logic perf_cnt_sel_3_metric_3_we; + logic perf_cnt_sel_3_metric_3_re; + logic [15:0] perf_cnt_sel_4_hart_4_qs; + logic [15:0] perf_cnt_sel_4_hart_4_wd; + logic perf_cnt_sel_4_hart_4_we; + logic perf_cnt_sel_4_hart_4_re; + logic [15:0] perf_cnt_sel_4_metric_4_qs; + logic [15:0] perf_cnt_sel_4_metric_4_wd; + logic perf_cnt_sel_4_metric_4_we; + logic perf_cnt_sel_4_metric_4_re; + logic [15:0] perf_cnt_sel_5_hart_5_qs; + logic [15:0] perf_cnt_sel_5_hart_5_wd; + logic perf_cnt_sel_5_hart_5_we; + logic perf_cnt_sel_5_hart_5_re; + logic [15:0] perf_cnt_sel_5_metric_5_qs; + logic [15:0] perf_cnt_sel_5_metric_5_wd; + logic perf_cnt_sel_5_metric_5_we; + logic perf_cnt_sel_5_metric_5_re; + logic [15:0] perf_cnt_sel_6_hart_6_qs; + logic [15:0] perf_cnt_sel_6_hart_6_wd; + logic perf_cnt_sel_6_hart_6_we; + logic perf_cnt_sel_6_hart_6_re; + logic [15:0] perf_cnt_sel_6_metric_6_qs; + logic [15:0] perf_cnt_sel_6_metric_6_wd; + logic perf_cnt_sel_6_metric_6_we; + logic perf_cnt_sel_6_metric_6_re; + logic [15:0] perf_cnt_sel_7_hart_7_qs; + logic [15:0] perf_cnt_sel_7_hart_7_wd; + logic perf_cnt_sel_7_hart_7_we; + logic perf_cnt_sel_7_hart_7_re; + logic [15:0] perf_cnt_sel_7_metric_7_qs; + logic [15:0] perf_cnt_sel_7_metric_7_wd; + logic perf_cnt_sel_7_metric_7_we; + logic perf_cnt_sel_7_metric_7_re; + logic [15:0] perf_cnt_sel_8_hart_8_qs; + logic [15:0] perf_cnt_sel_8_hart_8_wd; + logic perf_cnt_sel_8_hart_8_we; + logic perf_cnt_sel_8_hart_8_re; + logic [15:0] perf_cnt_sel_8_metric_8_qs; + logic [15:0] perf_cnt_sel_8_metric_8_wd; + logic perf_cnt_sel_8_metric_8_we; + logic perf_cnt_sel_8_metric_8_re; + logic [15:0] perf_cnt_sel_9_hart_9_qs; + logic [15:0] perf_cnt_sel_9_hart_9_wd; + logic perf_cnt_sel_9_hart_9_we; + logic perf_cnt_sel_9_hart_9_re; + logic [15:0] perf_cnt_sel_9_metric_9_qs; + logic [15:0] perf_cnt_sel_9_metric_9_wd; + logic perf_cnt_sel_9_metric_9_we; + logic perf_cnt_sel_9_metric_9_re; + logic [15:0] perf_cnt_sel_10_hart_10_qs; + logic [15:0] perf_cnt_sel_10_hart_10_wd; + logic perf_cnt_sel_10_hart_10_we; + logic perf_cnt_sel_10_hart_10_re; + logic [15:0] perf_cnt_sel_10_metric_10_qs; + logic [15:0] perf_cnt_sel_10_metric_10_wd; + logic perf_cnt_sel_10_metric_10_we; + logic perf_cnt_sel_10_metric_10_re; + logic [15:0] perf_cnt_sel_11_hart_11_qs; + logic [15:0] perf_cnt_sel_11_hart_11_wd; + logic perf_cnt_sel_11_hart_11_we; + logic perf_cnt_sel_11_hart_11_re; + logic [15:0] perf_cnt_sel_11_metric_11_qs; + logic [15:0] perf_cnt_sel_11_metric_11_wd; + logic perf_cnt_sel_11_metric_11_we; + logic perf_cnt_sel_11_metric_11_re; + logic [15:0] perf_cnt_sel_12_hart_12_qs; + logic [15:0] perf_cnt_sel_12_hart_12_wd; + logic perf_cnt_sel_12_hart_12_we; + logic perf_cnt_sel_12_hart_12_re; + logic [15:0] perf_cnt_sel_12_metric_12_qs; + logic [15:0] perf_cnt_sel_12_metric_12_wd; + logic perf_cnt_sel_12_metric_12_we; + logic perf_cnt_sel_12_metric_12_re; + logic [15:0] perf_cnt_sel_13_hart_13_qs; + logic [15:0] perf_cnt_sel_13_hart_13_wd; + logic perf_cnt_sel_13_hart_13_we; + logic perf_cnt_sel_13_hart_13_re; + logic [15:0] perf_cnt_sel_13_metric_13_qs; + logic [15:0] perf_cnt_sel_13_metric_13_wd; + logic perf_cnt_sel_13_metric_13_we; + logic perf_cnt_sel_13_metric_13_re; + logic [15:0] perf_cnt_sel_14_hart_14_qs; + logic [15:0] perf_cnt_sel_14_hart_14_wd; + logic perf_cnt_sel_14_hart_14_we; + logic perf_cnt_sel_14_hart_14_re; + logic [15:0] perf_cnt_sel_14_metric_14_qs; + logic [15:0] perf_cnt_sel_14_metric_14_wd; + logic perf_cnt_sel_14_metric_14_we; + logic perf_cnt_sel_14_metric_14_re; + logic [15:0] perf_cnt_sel_15_hart_15_qs; + logic [15:0] perf_cnt_sel_15_hart_15_wd; + logic perf_cnt_sel_15_hart_15_we; + logic perf_cnt_sel_15_hart_15_re; + logic [15:0] perf_cnt_sel_15_metric_15_qs; + logic [15:0] perf_cnt_sel_15_metric_15_wd; + logic perf_cnt_sel_15_metric_15_we; + logic perf_cnt_sel_15_metric_15_re; + logic [47:0] perf_cnt_0_qs; + logic [47:0] perf_cnt_0_wd; + logic perf_cnt_0_we; + logic perf_cnt_0_re; + logic [47:0] perf_cnt_1_qs; + logic [47:0] perf_cnt_1_wd; + logic perf_cnt_1_we; + logic perf_cnt_1_re; + logic [47:0] perf_cnt_2_qs; + logic [47:0] perf_cnt_2_wd; + logic perf_cnt_2_we; + logic perf_cnt_2_re; + logic [47:0] perf_cnt_3_qs; + logic [47:0] perf_cnt_3_wd; + logic perf_cnt_3_we; + logic perf_cnt_3_re; + logic [47:0] perf_cnt_4_qs; + logic [47:0] perf_cnt_4_wd; + logic perf_cnt_4_we; + logic perf_cnt_4_re; + logic [47:0] perf_cnt_5_qs; + logic [47:0] perf_cnt_5_wd; + logic perf_cnt_5_we; + logic perf_cnt_5_re; + logic [47:0] perf_cnt_6_qs; + logic [47:0] perf_cnt_6_wd; + logic perf_cnt_6_we; + logic perf_cnt_6_re; + logic [47:0] perf_cnt_7_qs; + logic [47:0] perf_cnt_7_wd; + logic perf_cnt_7_we; + logic perf_cnt_7_re; + logic [47:0] perf_cnt_8_qs; + logic [47:0] perf_cnt_8_wd; + logic perf_cnt_8_we; + logic perf_cnt_8_re; + logic [47:0] perf_cnt_9_qs; + logic [47:0] perf_cnt_9_wd; + logic perf_cnt_9_we; + logic perf_cnt_9_re; + logic [47:0] perf_cnt_10_qs; + logic [47:0] perf_cnt_10_wd; + logic perf_cnt_10_we; + logic perf_cnt_10_re; + logic [47:0] perf_cnt_11_qs; + logic [47:0] perf_cnt_11_wd; + logic perf_cnt_11_we; + logic perf_cnt_11_re; + logic [47:0] perf_cnt_12_qs; + logic [47:0] perf_cnt_12_wd; + logic perf_cnt_12_we; + logic perf_cnt_12_re; + logic [47:0] perf_cnt_13_qs; + logic [47:0] perf_cnt_13_wd; + logic perf_cnt_13_we; + logic perf_cnt_13_re; + logic [47:0] perf_cnt_14_qs; + logic [47:0] perf_cnt_14_wd; + logic perf_cnt_14_we; + logic perf_cnt_14_re; + logic [47:0] perf_cnt_15_qs; + logic [47:0] perf_cnt_15_wd; + logic perf_cnt_15_we; + logic perf_cnt_15_re; logic [31:0] cl_clint_set_wd; logic cl_clint_set_we; logic [31:0] cl_clint_clear_wd; logic cl_clint_clear_we; - logic [31:0] hw_barrier_qs; - logic hw_barrier_re; logic icache_prefetch_enable_wd; logic icache_prefetch_enable_we; // Register instances - // Subregister 0 of Multireg perf_counter_enable - // R[perf_counter_enable_0]: V(False) + // Subregister 0 of Multireg perf_cnt_en + // R[perf_cnt_en_0]: V(False) - // F[cycle_0]: 0:0 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_cycle_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_cycle_0_we), - .wd (perf_counter_enable_0_cycle_0_wd), + .we (perf_cnt_en_0_we), + .wd (perf_cnt_en_0_wd), // from internal hardware .de (1'b0), @@ -1701,25 +338,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].cycle.q ), + .q (reg2hw.perf_cnt_en[0].q ), // to register interface (read) - .qs (perf_counter_enable_0_cycle_0_qs) + .qs (perf_cnt_en_0_qs) ); + // Subregister 1 of Multireg perf_cnt_en + // R[perf_cnt_en_1]: V(False) - // F[tcdm_accessed_0]: 1:1 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_tcdm_accessed_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_1 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_tcdm_accessed_0_we), - .wd (perf_counter_enable_0_tcdm_accessed_0_wd), + .we (perf_cnt_en_1_we), + .wd (perf_cnt_en_1_wd), // from internal hardware .de (1'b0), @@ -1727,25 +365,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].tcdm_accessed.q ), + .q (reg2hw.perf_cnt_en[1].q ), // to register interface (read) - .qs (perf_counter_enable_0_tcdm_accessed_0_qs) + .qs (perf_cnt_en_1_qs) ); + // Subregister 2 of Multireg perf_cnt_en + // R[perf_cnt_en_2]: V(False) - // F[tcdm_congested_0]: 2:2 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_tcdm_congested_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_2 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_tcdm_congested_0_we), - .wd (perf_counter_enable_0_tcdm_congested_0_wd), + .we (perf_cnt_en_2_we), + .wd (perf_cnt_en_2_wd), // from internal hardware .de (1'b0), @@ -1753,25 +392,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].tcdm_congested.q ), + .q (reg2hw.perf_cnt_en[2].q ), // to register interface (read) - .qs (perf_counter_enable_0_tcdm_congested_0_qs) + .qs (perf_cnt_en_2_qs) ); + // Subregister 3 of Multireg perf_cnt_en + // R[perf_cnt_en_3]: V(False) - // F[issue_fpu_0]: 3:3 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_issue_fpu_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_3 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_issue_fpu_0_we), - .wd (perf_counter_enable_0_issue_fpu_0_wd), + .we (perf_cnt_en_3_we), + .wd (perf_cnt_en_3_wd), // from internal hardware .de (1'b0), @@ -1779,25 +419,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].issue_fpu.q ), + .q (reg2hw.perf_cnt_en[3].q ), // to register interface (read) - .qs (perf_counter_enable_0_issue_fpu_0_qs) + .qs (perf_cnt_en_3_qs) ); + // Subregister 4 of Multireg perf_cnt_en + // R[perf_cnt_en_4]: V(False) - // F[issue_fpu_seq_0]: 4:4 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_issue_fpu_seq_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_4 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_issue_fpu_seq_0_we), - .wd (perf_counter_enable_0_issue_fpu_seq_0_wd), + .we (perf_cnt_en_4_we), + .wd (perf_cnt_en_4_wd), // from internal hardware .de (1'b0), @@ -1805,25 +446,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].issue_fpu_seq.q ), + .q (reg2hw.perf_cnt_en[4].q ), // to register interface (read) - .qs (perf_counter_enable_0_issue_fpu_seq_0_qs) + .qs (perf_cnt_en_4_qs) ); + // Subregister 5 of Multireg perf_cnt_en + // R[perf_cnt_en_5]: V(False) - // F[issue_core_to_fpu_0]: 5:5 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_issue_core_to_fpu_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_5 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_issue_core_to_fpu_0_we), - .wd (perf_counter_enable_0_issue_core_to_fpu_0_wd), + .we (perf_cnt_en_5_we), + .wd (perf_cnt_en_5_wd), // from internal hardware .de (1'b0), @@ -1831,25 +473,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].issue_core_to_fpu.q ), + .q (reg2hw.perf_cnt_en[5].q ), // to register interface (read) - .qs (perf_counter_enable_0_issue_core_to_fpu_0_qs) + .qs (perf_cnt_en_5_qs) ); + // Subregister 6 of Multireg perf_cnt_en + // R[perf_cnt_en_6]: V(False) - // F[retired_instr_0]: 6:6 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_retired_instr_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_6 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_retired_instr_0_we), - .wd (perf_counter_enable_0_retired_instr_0_wd), + .we (perf_cnt_en_6_we), + .wd (perf_cnt_en_6_wd), // from internal hardware .de (1'b0), @@ -1857,25 +500,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].retired_instr.q ), + .q (reg2hw.perf_cnt_en[6].q ), // to register interface (read) - .qs (perf_counter_enable_0_retired_instr_0_qs) + .qs (perf_cnt_en_6_qs) ); + // Subregister 7 of Multireg perf_cnt_en + // R[perf_cnt_en_7]: V(False) - // F[retired_load_0]: 7:7 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_retired_load_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_7 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_retired_load_0_we), - .wd (perf_counter_enable_0_retired_load_0_wd), + .we (perf_cnt_en_7_we), + .wd (perf_cnt_en_7_wd), // from internal hardware .de (1'b0), @@ -1883,25 +527,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].retired_load.q ), + .q (reg2hw.perf_cnt_en[7].q ), // to register interface (read) - .qs (perf_counter_enable_0_retired_load_0_qs) + .qs (perf_cnt_en_7_qs) ); + // Subregister 8 of Multireg perf_cnt_en + // R[perf_cnt_en_8]: V(False) - // F[retired_i_0]: 8:8 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_retired_i_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_8 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_retired_i_0_we), - .wd (perf_counter_enable_0_retired_i_0_wd), + .we (perf_cnt_en_8_we), + .wd (perf_cnt_en_8_wd), // from internal hardware .de (1'b0), @@ -1909,25 +554,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].retired_i.q ), + .q (reg2hw.perf_cnt_en[8].q ), // to register interface (read) - .qs (perf_counter_enable_0_retired_i_0_qs) + .qs (perf_cnt_en_8_qs) ); + // Subregister 9 of Multireg perf_cnt_en + // R[perf_cnt_en_9]: V(False) - // F[retired_acc_0]: 9:9 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_retired_acc_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_9 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_retired_acc_0_we), - .wd (perf_counter_enable_0_retired_acc_0_wd), + .we (perf_cnt_en_9_we), + .wd (perf_cnt_en_9_wd), // from internal hardware .de (1'b0), @@ -1935,25 +581,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].retired_acc.q ), + .q (reg2hw.perf_cnt_en[9].q ), // to register interface (read) - .qs (perf_counter_enable_0_retired_acc_0_qs) + .qs (perf_cnt_en_9_qs) ); + // Subregister 10 of Multireg perf_cnt_en + // R[perf_cnt_en_10]: V(False) - // F[dma_aw_stall_0]: 10:10 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_aw_stall_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_10 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_dma_aw_stall_0_we), - .wd (perf_counter_enable_0_dma_aw_stall_0_wd), + .we (perf_cnt_en_10_we), + .wd (perf_cnt_en_10_wd), // from internal hardware .de (1'b0), @@ -1961,25 +608,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].dma_aw_stall.q ), + .q (reg2hw.perf_cnt_en[10].q ), // to register interface (read) - .qs (perf_counter_enable_0_dma_aw_stall_0_qs) + .qs (perf_cnt_en_10_qs) ); + // Subregister 11 of Multireg perf_cnt_en + // R[perf_cnt_en_11]: V(False) - // F[dma_ar_stall_0]: 11:11 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_ar_stall_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_11 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_dma_ar_stall_0_we), - .wd (perf_counter_enable_0_dma_ar_stall_0_wd), + .we (perf_cnt_en_11_we), + .wd (perf_cnt_en_11_wd), // from internal hardware .de (1'b0), @@ -1987,25 +635,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].dma_ar_stall.q ), + .q (reg2hw.perf_cnt_en[11].q ), // to register interface (read) - .qs (perf_counter_enable_0_dma_ar_stall_0_qs) + .qs (perf_cnt_en_11_qs) ); + // Subregister 12 of Multireg perf_cnt_en + // R[perf_cnt_en_12]: V(False) - // F[dma_r_stall_0]: 12:12 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_r_stall_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_12 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_dma_r_stall_0_we), - .wd (perf_counter_enable_0_dma_r_stall_0_wd), + .we (perf_cnt_en_12_we), + .wd (perf_cnt_en_12_wd), // from internal hardware .de (1'b0), @@ -2013,25 +662,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].dma_r_stall.q ), + .q (reg2hw.perf_cnt_en[12].q ), // to register interface (read) - .qs (perf_counter_enable_0_dma_r_stall_0_qs) + .qs (perf_cnt_en_12_qs) ); + // Subregister 13 of Multireg perf_cnt_en + // R[perf_cnt_en_13]: V(False) - // F[dma_w_stall_0]: 13:13 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_w_stall_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_13 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_dma_w_stall_0_we), - .wd (perf_counter_enable_0_dma_w_stall_0_wd), + .we (perf_cnt_en_13_we), + .wd (perf_cnt_en_13_wd), // from internal hardware .de (1'b0), @@ -2039,25 +689,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].dma_w_stall.q ), + .q (reg2hw.perf_cnt_en[13].q ), // to register interface (read) - .qs (perf_counter_enable_0_dma_w_stall_0_qs) + .qs (perf_cnt_en_13_qs) ); + // Subregister 14 of Multireg perf_cnt_en + // R[perf_cnt_en_14]: V(False) - // F[dma_buf_w_stall_0]: 14:14 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_buf_w_stall_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_14 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_dma_buf_w_stall_0_we), - .wd (perf_counter_enable_0_dma_buf_w_stall_0_wd), + .we (perf_cnt_en_14_we), + .wd (perf_cnt_en_14_wd), // from internal hardware .de (1'b0), @@ -2065,25 +716,26 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].dma_buf_w_stall.q ), + .q (reg2hw.perf_cnt_en[14].q ), // to register interface (read) - .qs (perf_counter_enable_0_dma_buf_w_stall_0_qs) + .qs (perf_cnt_en_14_qs) ); + // Subregister 15 of Multireg perf_cnt_en + // R[perf_cnt_en_15]: V(False) - // F[dma_buf_r_stall_0]: 15:15 prim_subreg #( .DW (1), .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_buf_r_stall_0 ( + .RESVAL (1'h1) + ) u_perf_cnt_en_15 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (perf_counter_enable_0_dma_buf_r_stall_0_we), - .wd (perf_counter_enable_0_dma_buf_r_stall_0_wd), + .we (perf_cnt_en_15_we), + .wd (perf_cnt_en_15_wd), // from internal hardware .de (1'b0), @@ -2091,15022 +743,1214 @@ module snitch_cluster_peripheral_reg_top #( // to internal hardware .qe (), - .q (reg2hw.perf_counter_enable[0].dma_buf_r_stall.q ), + .q (reg2hw.perf_cnt_en[15].q ), // to register interface (read) - .qs (perf_counter_enable_0_dma_buf_r_stall_0_qs) + .qs (perf_cnt_en_15_qs) ); - // F[dma_aw_done_0]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_aw_done_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - // from register interface - .we (perf_counter_enable_0_dma_aw_done_0_we), - .wd (perf_counter_enable_0_dma_aw_done_0_wd), + // Subregister 0 of Multireg perf_cnt_sel + // R[perf_cnt_sel_0]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_0]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_0_hart_0 ( + .re (perf_cnt_sel_0_hart_0_re), + .we (perf_cnt_sel_0_hart_0_we), + .wd (perf_cnt_sel_0_hart_0_wd), + .d (hw2reg.perf_cnt_sel[0].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[0].hart.qe), + .q (reg2hw.perf_cnt_sel[0].hart.q ), + .qs (perf_cnt_sel_0_hart_0_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_aw_done.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_aw_done_0_qs) + // F[metric_0]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_0_metric_0 ( + .re (perf_cnt_sel_0_metric_0_re), + .we (perf_cnt_sel_0_metric_0_we), + .wd (perf_cnt_sel_0_metric_0_wd), + .d (hw2reg.perf_cnt_sel[0].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[0].metric.qe), + .q (reg2hw.perf_cnt_sel[0].metric.q ), + .qs (perf_cnt_sel_0_metric_0_qs) ); - // F[dma_aw_bw_0]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_aw_bw_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_aw_bw_0_we), - .wd (perf_counter_enable_0_dma_aw_bw_0_wd), + // Subregister 1 of Multireg perf_cnt_sel + // R[perf_cnt_sel_1]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_1]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_1_hart_1 ( + .re (perf_cnt_sel_1_hart_1_re), + .we (perf_cnt_sel_1_hart_1_we), + .wd (perf_cnt_sel_1_hart_1_wd), + .d (hw2reg.perf_cnt_sel[1].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[1].hart.qe), + .q (reg2hw.perf_cnt_sel[1].hart.q ), + .qs (perf_cnt_sel_1_hart_1_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_aw_bw.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_aw_bw_0_qs) + // F[metric_1]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_1_metric_1 ( + .re (perf_cnt_sel_1_metric_1_re), + .we (perf_cnt_sel_1_metric_1_we), + .wd (perf_cnt_sel_1_metric_1_wd), + .d (hw2reg.perf_cnt_sel[1].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[1].metric.qe), + .q (reg2hw.perf_cnt_sel[1].metric.q ), + .qs (perf_cnt_sel_1_metric_1_qs) ); - // F[dma_ar_done_0]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_ar_done_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_ar_done_0_we), - .wd (perf_counter_enable_0_dma_ar_done_0_wd), + // Subregister 2 of Multireg perf_cnt_sel + // R[perf_cnt_sel_2]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_2]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_2_hart_2 ( + .re (perf_cnt_sel_2_hart_2_re), + .we (perf_cnt_sel_2_hart_2_we), + .wd (perf_cnt_sel_2_hart_2_wd), + .d (hw2reg.perf_cnt_sel[2].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[2].hart.qe), + .q (reg2hw.perf_cnt_sel[2].hart.q ), + .qs (perf_cnt_sel_2_hart_2_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_ar_done.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_ar_done_0_qs) + // F[metric_2]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_2_metric_2 ( + .re (perf_cnt_sel_2_metric_2_re), + .we (perf_cnt_sel_2_metric_2_we), + .wd (perf_cnt_sel_2_metric_2_wd), + .d (hw2reg.perf_cnt_sel[2].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[2].metric.qe), + .q (reg2hw.perf_cnt_sel[2].metric.q ), + .qs (perf_cnt_sel_2_metric_2_qs) ); - // F[dma_ar_bw_0]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_ar_bw_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_ar_bw_0_we), - .wd (perf_counter_enable_0_dma_ar_bw_0_wd), + // Subregister 3 of Multireg perf_cnt_sel + // R[perf_cnt_sel_3]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_3]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_3_hart_3 ( + .re (perf_cnt_sel_3_hart_3_re), + .we (perf_cnt_sel_3_hart_3_we), + .wd (perf_cnt_sel_3_hart_3_wd), + .d (hw2reg.perf_cnt_sel[3].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[3].hart.qe), + .q (reg2hw.perf_cnt_sel[3].hart.q ), + .qs (perf_cnt_sel_3_hart_3_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_ar_bw.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_ar_bw_0_qs) + // F[metric_3]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_3_metric_3 ( + .re (perf_cnt_sel_3_metric_3_re), + .we (perf_cnt_sel_3_metric_3_we), + .wd (perf_cnt_sel_3_metric_3_wd), + .d (hw2reg.perf_cnt_sel[3].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[3].metric.qe), + .q (reg2hw.perf_cnt_sel[3].metric.q ), + .qs (perf_cnt_sel_3_metric_3_qs) ); - // F[dma_r_done_0]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_r_done_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_r_done_0_we), - .wd (perf_counter_enable_0_dma_r_done_0_wd), + // Subregister 4 of Multireg perf_cnt_sel + // R[perf_cnt_sel_4]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_4]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_4_hart_4 ( + .re (perf_cnt_sel_4_hart_4_re), + .we (perf_cnt_sel_4_hart_4_we), + .wd (perf_cnt_sel_4_hart_4_wd), + .d (hw2reg.perf_cnt_sel[4].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[4].hart.qe), + .q (reg2hw.perf_cnt_sel[4].hart.q ), + .qs (perf_cnt_sel_4_hart_4_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_r_done.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_r_done_0_qs) + // F[metric_4]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_4_metric_4 ( + .re (perf_cnt_sel_4_metric_4_re), + .we (perf_cnt_sel_4_metric_4_we), + .wd (perf_cnt_sel_4_metric_4_wd), + .d (hw2reg.perf_cnt_sel[4].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[4].metric.qe), + .q (reg2hw.perf_cnt_sel[4].metric.q ), + .qs (perf_cnt_sel_4_metric_4_qs) ); - // F[dma_r_bw_0]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_r_bw_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_r_bw_0_we), - .wd (perf_counter_enable_0_dma_r_bw_0_wd), + // Subregister 5 of Multireg perf_cnt_sel + // R[perf_cnt_sel_5]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_5]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_5_hart_5 ( + .re (perf_cnt_sel_5_hart_5_re), + .we (perf_cnt_sel_5_hart_5_we), + .wd (perf_cnt_sel_5_hart_5_wd), + .d (hw2reg.perf_cnt_sel[5].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[5].hart.qe), + .q (reg2hw.perf_cnt_sel[5].hart.q ), + .qs (perf_cnt_sel_5_hart_5_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_r_bw.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_r_bw_0_qs) + // F[metric_5]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_5_metric_5 ( + .re (perf_cnt_sel_5_metric_5_re), + .we (perf_cnt_sel_5_metric_5_we), + .wd (perf_cnt_sel_5_metric_5_wd), + .d (hw2reg.perf_cnt_sel[5].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[5].metric.qe), + .q (reg2hw.perf_cnt_sel[5].metric.q ), + .qs (perf_cnt_sel_5_metric_5_qs) ); - // F[dma_w_done_0]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_w_done_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_w_done_0_we), - .wd (perf_counter_enable_0_dma_w_done_0_wd), + // Subregister 6 of Multireg perf_cnt_sel + // R[perf_cnt_sel_6]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_6]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_6_hart_6 ( + .re (perf_cnt_sel_6_hart_6_re), + .we (perf_cnt_sel_6_hart_6_we), + .wd (perf_cnt_sel_6_hart_6_wd), + .d (hw2reg.perf_cnt_sel[6].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[6].hart.qe), + .q (reg2hw.perf_cnt_sel[6].hart.q ), + .qs (perf_cnt_sel_6_hart_6_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_w_done.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_w_done_0_qs) + // F[metric_6]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_6_metric_6 ( + .re (perf_cnt_sel_6_metric_6_re), + .we (perf_cnt_sel_6_metric_6_we), + .wd (perf_cnt_sel_6_metric_6_wd), + .d (hw2reg.perf_cnt_sel[6].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[6].metric.qe), + .q (reg2hw.perf_cnt_sel[6].metric.q ), + .qs (perf_cnt_sel_6_metric_6_qs) ); - // F[dma_w_bw_0]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_w_bw_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_w_bw_0_we), - .wd (perf_counter_enable_0_dma_w_bw_0_wd), + // Subregister 7 of Multireg perf_cnt_sel + // R[perf_cnt_sel_7]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_7]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_7_hart_7 ( + .re (perf_cnt_sel_7_hart_7_re), + .we (perf_cnt_sel_7_hart_7_we), + .wd (perf_cnt_sel_7_hart_7_wd), + .d (hw2reg.perf_cnt_sel[7].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[7].hart.qe), + .q (reg2hw.perf_cnt_sel[7].hart.q ), + .qs (perf_cnt_sel_7_hart_7_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_w_bw.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_w_bw_0_qs) + // F[metric_7]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_7_metric_7 ( + .re (perf_cnt_sel_7_metric_7_re), + .we (perf_cnt_sel_7_metric_7_we), + .wd (perf_cnt_sel_7_metric_7_wd), + .d (hw2reg.perf_cnt_sel[7].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[7].metric.qe), + .q (reg2hw.perf_cnt_sel[7].metric.q ), + .qs (perf_cnt_sel_7_metric_7_qs) ); - // F[dma_b_done_0]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_b_done_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_b_done_0_we), - .wd (perf_counter_enable_0_dma_b_done_0_wd), + // Subregister 8 of Multireg perf_cnt_sel + // R[perf_cnt_sel_8]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_8]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_8_hart_8 ( + .re (perf_cnt_sel_8_hart_8_re), + .we (perf_cnt_sel_8_hart_8_we), + .wd (perf_cnt_sel_8_hart_8_wd), + .d (hw2reg.perf_cnt_sel[8].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[8].hart.qe), + .q (reg2hw.perf_cnt_sel[8].hart.q ), + .qs (perf_cnt_sel_8_hart_8_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_b_done.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_b_done_0_qs) + // F[metric_8]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_8_metric_8 ( + .re (perf_cnt_sel_8_metric_8_re), + .we (perf_cnt_sel_8_metric_8_we), + .wd (perf_cnt_sel_8_metric_8_wd), + .d (hw2reg.perf_cnt_sel[8].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[8].metric.qe), + .q (reg2hw.perf_cnt_sel[8].metric.q ), + .qs (perf_cnt_sel_8_metric_8_qs) ); - // F[dma_busy_0]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_dma_busy_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_dma_busy_0_we), - .wd (perf_counter_enable_0_dma_busy_0_wd), + // Subregister 9 of Multireg perf_cnt_sel + // R[perf_cnt_sel_9]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_9]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_9_hart_9 ( + .re (perf_cnt_sel_9_hart_9_re), + .we (perf_cnt_sel_9_hart_9_we), + .wd (perf_cnt_sel_9_hart_9_wd), + .d (hw2reg.perf_cnt_sel[9].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[9].hart.qe), + .q (reg2hw.perf_cnt_sel[9].hart.q ), + .qs (perf_cnt_sel_9_hart_9_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].dma_busy.q ), - // to register interface (read) - .qs (perf_counter_enable_0_dma_busy_0_qs) + // F[metric_9]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_9_metric_9 ( + .re (perf_cnt_sel_9_metric_9_re), + .we (perf_cnt_sel_9_metric_9_we), + .wd (perf_cnt_sel_9_metric_9_wd), + .d (hw2reg.perf_cnt_sel[9].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[9].metric.qe), + .q (reg2hw.perf_cnt_sel[9].metric.q ), + .qs (perf_cnt_sel_9_metric_9_qs) ); - // F[icache_miss_0]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_icache_miss_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_icache_miss_0_we), - .wd (perf_counter_enable_0_icache_miss_0_wd), + // Subregister 10 of Multireg perf_cnt_sel + // R[perf_cnt_sel_10]: V(True) - // from internal hardware - .de (1'b0), - .d ('0 ), + // F[hart_10]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_10_hart_10 ( + .re (perf_cnt_sel_10_hart_10_re), + .we (perf_cnt_sel_10_hart_10_we), + .wd (perf_cnt_sel_10_hart_10_wd), + .d (hw2reg.perf_cnt_sel[10].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[10].hart.qe), + .q (reg2hw.perf_cnt_sel[10].hart.q ), + .qs (perf_cnt_sel_10_hart_10_qs) + ); - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].icache_miss.q ), - // to register interface (read) - .qs (perf_counter_enable_0_icache_miss_0_qs) + // F[metric_10]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_10_metric_10 ( + .re (perf_cnt_sel_10_metric_10_re), + .we (perf_cnt_sel_10_metric_10_we), + .wd (perf_cnt_sel_10_metric_10_wd), + .d (hw2reg.perf_cnt_sel[10].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[10].metric.qe), + .q (reg2hw.perf_cnt_sel[10].metric.q ), + .qs (perf_cnt_sel_10_metric_10_qs) ); - // F[icache_hit_0]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_icache_hit_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + // Subregister 11 of Multireg perf_cnt_sel + // R[perf_cnt_sel_11]: V(True) - // from register interface - .we (perf_counter_enable_0_icache_hit_0_we), - .wd (perf_counter_enable_0_icache_hit_0_wd), + // F[hart_11]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_11_hart_11 ( + .re (perf_cnt_sel_11_hart_11_re), + .we (perf_cnt_sel_11_hart_11_we), + .wd (perf_cnt_sel_11_hart_11_wd), + .d (hw2reg.perf_cnt_sel[11].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[11].hart.qe), + .q (reg2hw.perf_cnt_sel[11].hart.q ), + .qs (perf_cnt_sel_11_hart_11_qs) + ); - // from internal hardware - .de (1'b0), - .d ('0 ), - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].icache_hit.q ), + // F[metric_11]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_11_metric_11 ( + .re (perf_cnt_sel_11_metric_11_re), + .we (perf_cnt_sel_11_metric_11_we), + .wd (perf_cnt_sel_11_metric_11_wd), + .d (hw2reg.perf_cnt_sel[11].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[11].metric.qe), + .q (reg2hw.perf_cnt_sel[11].metric.q ), + .qs (perf_cnt_sel_11_metric_11_qs) + ); - // to register interface (read) - .qs (perf_counter_enable_0_icache_hit_0_qs) + + // Subregister 12 of Multireg perf_cnt_sel + // R[perf_cnt_sel_12]: V(True) + + // F[hart_12]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_12_hart_12 ( + .re (perf_cnt_sel_12_hart_12_re), + .we (perf_cnt_sel_12_hart_12_we), + .wd (perf_cnt_sel_12_hart_12_wd), + .d (hw2reg.perf_cnt_sel[12].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[12].hart.qe), + .q (reg2hw.perf_cnt_sel[12].hart.q ), + .qs (perf_cnt_sel_12_hart_12_qs) ); - // F[icache_prefetch_0]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_icache_prefetch_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + // F[metric_12]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_12_metric_12 ( + .re (perf_cnt_sel_12_metric_12_re), + .we (perf_cnt_sel_12_metric_12_we), + .wd (perf_cnt_sel_12_metric_12_wd), + .d (hw2reg.perf_cnt_sel[12].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[12].metric.qe), + .q (reg2hw.perf_cnt_sel[12].metric.q ), + .qs (perf_cnt_sel_12_metric_12_qs) + ); - // from register interface - .we (perf_counter_enable_0_icache_prefetch_0_we), - .wd (perf_counter_enable_0_icache_prefetch_0_wd), - // from internal hardware - .de (1'b0), - .d ('0 ), + // Subregister 13 of Multireg perf_cnt_sel + // R[perf_cnt_sel_13]: V(True) - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].icache_prefetch.q ), + // F[hart_13]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_13_hart_13 ( + .re (perf_cnt_sel_13_hart_13_re), + .we (perf_cnt_sel_13_hart_13_we), + .wd (perf_cnt_sel_13_hart_13_wd), + .d (hw2reg.perf_cnt_sel[13].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[13].hart.qe), + .q (reg2hw.perf_cnt_sel[13].hart.q ), + .qs (perf_cnt_sel_13_hart_13_qs) + ); - // to register interface (read) - .qs (perf_counter_enable_0_icache_prefetch_0_qs) + + // F[metric_13]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_13_metric_13 ( + .re (perf_cnt_sel_13_metric_13_re), + .we (perf_cnt_sel_13_metric_13_we), + .wd (perf_cnt_sel_13_metric_13_wd), + .d (hw2reg.perf_cnt_sel[13].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[13].metric.qe), + .q (reg2hw.perf_cnt_sel[13].metric.q ), + .qs (perf_cnt_sel_13_metric_13_qs) ); - // F[icache_double_hit_0]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_icache_double_hit_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_icache_double_hit_0_we), - .wd (perf_counter_enable_0_icache_double_hit_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_0_icache_double_hit_0_qs) - ); - - - // F[icache_stall_0]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_0_icache_stall_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_0_icache_stall_0_we), - .wd (perf_counter_enable_0_icache_stall_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[0].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_0_icache_stall_0_qs) - ); - - - // Subregister 1 of Multireg perf_counter_enable - // R[perf_counter_enable_1]: V(False) - - // F[cycle_1]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_cycle_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_cycle_1_we), - .wd (perf_counter_enable_1_cycle_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_cycle_1_qs) - ); - - - // F[tcdm_accessed_1]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_tcdm_accessed_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_tcdm_accessed_1_we), - .wd (perf_counter_enable_1_tcdm_accessed_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_tcdm_accessed_1_qs) - ); - - - // F[tcdm_congested_1]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_tcdm_congested_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_tcdm_congested_1_we), - .wd (perf_counter_enable_1_tcdm_congested_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_tcdm_congested_1_qs) - ); - - - // F[issue_fpu_1]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_issue_fpu_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_issue_fpu_1_we), - .wd (perf_counter_enable_1_issue_fpu_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_issue_fpu_1_qs) - ); - - - // F[issue_fpu_seq_1]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_issue_fpu_seq_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_issue_fpu_seq_1_we), - .wd (perf_counter_enable_1_issue_fpu_seq_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_issue_fpu_seq_1_qs) - ); - - - // F[issue_core_to_fpu_1]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_issue_core_to_fpu_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_issue_core_to_fpu_1_we), - .wd (perf_counter_enable_1_issue_core_to_fpu_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_issue_core_to_fpu_1_qs) - ); - - - // F[retired_instr_1]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_retired_instr_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_retired_instr_1_we), - .wd (perf_counter_enable_1_retired_instr_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_retired_instr_1_qs) - ); - - - // F[retired_load_1]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_retired_load_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_retired_load_1_we), - .wd (perf_counter_enable_1_retired_load_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_retired_load_1_qs) - ); - - - // F[retired_i_1]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_retired_i_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_retired_i_1_we), - .wd (perf_counter_enable_1_retired_i_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_retired_i_1_qs) - ); - - - // F[retired_acc_1]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_retired_acc_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_retired_acc_1_we), - .wd (perf_counter_enable_1_retired_acc_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_retired_acc_1_qs) - ); - - - // F[dma_aw_stall_1]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_aw_stall_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_aw_stall_1_we), - .wd (perf_counter_enable_1_dma_aw_stall_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_aw_stall_1_qs) - ); - - - // F[dma_ar_stall_1]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_ar_stall_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_ar_stall_1_we), - .wd (perf_counter_enable_1_dma_ar_stall_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_ar_stall_1_qs) - ); - - - // F[dma_r_stall_1]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_r_stall_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_r_stall_1_we), - .wd (perf_counter_enable_1_dma_r_stall_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_r_stall_1_qs) - ); - - - // F[dma_w_stall_1]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_w_stall_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_w_stall_1_we), - .wd (perf_counter_enable_1_dma_w_stall_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_w_stall_1_qs) - ); - - - // F[dma_buf_w_stall_1]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_buf_w_stall_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_buf_w_stall_1_we), - .wd (perf_counter_enable_1_dma_buf_w_stall_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_buf_w_stall_1_qs) - ); - - - // F[dma_buf_r_stall_1]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_buf_r_stall_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_buf_r_stall_1_we), - .wd (perf_counter_enable_1_dma_buf_r_stall_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_buf_r_stall_1_qs) - ); - - - // F[dma_aw_done_1]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_aw_done_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_aw_done_1_we), - .wd (perf_counter_enable_1_dma_aw_done_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_aw_done_1_qs) - ); - - - // F[dma_aw_bw_1]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_aw_bw_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_aw_bw_1_we), - .wd (perf_counter_enable_1_dma_aw_bw_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_aw_bw_1_qs) - ); - - - // F[dma_ar_done_1]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_ar_done_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_ar_done_1_we), - .wd (perf_counter_enable_1_dma_ar_done_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_ar_done_1_qs) - ); - - - // F[dma_ar_bw_1]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_ar_bw_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_ar_bw_1_we), - .wd (perf_counter_enable_1_dma_ar_bw_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_ar_bw_1_qs) - ); - - - // F[dma_r_done_1]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_r_done_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_r_done_1_we), - .wd (perf_counter_enable_1_dma_r_done_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_r_done_1_qs) - ); - - - // F[dma_r_bw_1]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_r_bw_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_r_bw_1_we), - .wd (perf_counter_enable_1_dma_r_bw_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_r_bw_1_qs) - ); - - - // F[dma_w_done_1]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_w_done_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_w_done_1_we), - .wd (perf_counter_enable_1_dma_w_done_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_w_done_1_qs) - ); - - - // F[dma_w_bw_1]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_w_bw_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_w_bw_1_we), - .wd (perf_counter_enable_1_dma_w_bw_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_w_bw_1_qs) - ); - - - // F[dma_b_done_1]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_b_done_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_b_done_1_we), - .wd (perf_counter_enable_1_dma_b_done_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_b_done_1_qs) - ); - - - // F[dma_busy_1]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_dma_busy_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_dma_busy_1_we), - .wd (perf_counter_enable_1_dma_busy_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_dma_busy_1_qs) - ); - - - // F[icache_miss_1]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_icache_miss_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_icache_miss_1_we), - .wd (perf_counter_enable_1_icache_miss_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_icache_miss_1_qs) - ); - - - // F[icache_hit_1]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_icache_hit_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_icache_hit_1_we), - .wd (perf_counter_enable_1_icache_hit_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_icache_hit_1_qs) - ); - - - // F[icache_prefetch_1]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_icache_prefetch_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_icache_prefetch_1_we), - .wd (perf_counter_enable_1_icache_prefetch_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_icache_prefetch_1_qs) - ); - - - // F[icache_double_hit_1]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_icache_double_hit_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_icache_double_hit_1_we), - .wd (perf_counter_enable_1_icache_double_hit_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_icache_double_hit_1_qs) - ); - - - // F[icache_stall_1]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_1_icache_stall_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_1_icache_stall_1_we), - .wd (perf_counter_enable_1_icache_stall_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[1].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_1_icache_stall_1_qs) - ); - - - // Subregister 2 of Multireg perf_counter_enable - // R[perf_counter_enable_2]: V(False) - - // F[cycle_2]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_cycle_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_cycle_2_we), - .wd (perf_counter_enable_2_cycle_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_cycle_2_qs) - ); - - - // F[tcdm_accessed_2]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_tcdm_accessed_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_tcdm_accessed_2_we), - .wd (perf_counter_enable_2_tcdm_accessed_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_tcdm_accessed_2_qs) - ); - - - // F[tcdm_congested_2]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_tcdm_congested_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_tcdm_congested_2_we), - .wd (perf_counter_enable_2_tcdm_congested_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_tcdm_congested_2_qs) - ); - - - // F[issue_fpu_2]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_issue_fpu_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_issue_fpu_2_we), - .wd (perf_counter_enable_2_issue_fpu_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_issue_fpu_2_qs) - ); - - - // F[issue_fpu_seq_2]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_issue_fpu_seq_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_issue_fpu_seq_2_we), - .wd (perf_counter_enable_2_issue_fpu_seq_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_issue_fpu_seq_2_qs) - ); - - - // F[issue_core_to_fpu_2]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_issue_core_to_fpu_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_issue_core_to_fpu_2_we), - .wd (perf_counter_enable_2_issue_core_to_fpu_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_issue_core_to_fpu_2_qs) - ); - - - // F[retired_instr_2]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_retired_instr_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_retired_instr_2_we), - .wd (perf_counter_enable_2_retired_instr_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_retired_instr_2_qs) - ); - - - // F[retired_load_2]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_retired_load_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_retired_load_2_we), - .wd (perf_counter_enable_2_retired_load_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_retired_load_2_qs) - ); - - - // F[retired_i_2]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_retired_i_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_retired_i_2_we), - .wd (perf_counter_enable_2_retired_i_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_retired_i_2_qs) - ); - - - // F[retired_acc_2]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_retired_acc_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_retired_acc_2_we), - .wd (perf_counter_enable_2_retired_acc_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_retired_acc_2_qs) - ); - - - // F[dma_aw_stall_2]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_aw_stall_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_aw_stall_2_we), - .wd (perf_counter_enable_2_dma_aw_stall_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_aw_stall_2_qs) - ); - - - // F[dma_ar_stall_2]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_ar_stall_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_ar_stall_2_we), - .wd (perf_counter_enable_2_dma_ar_stall_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_ar_stall_2_qs) - ); - - - // F[dma_r_stall_2]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_r_stall_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_r_stall_2_we), - .wd (perf_counter_enable_2_dma_r_stall_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_r_stall_2_qs) - ); - - - // F[dma_w_stall_2]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_w_stall_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_w_stall_2_we), - .wd (perf_counter_enable_2_dma_w_stall_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_w_stall_2_qs) - ); - - - // F[dma_buf_w_stall_2]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_buf_w_stall_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_buf_w_stall_2_we), - .wd (perf_counter_enable_2_dma_buf_w_stall_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_buf_w_stall_2_qs) - ); - - - // F[dma_buf_r_stall_2]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_buf_r_stall_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_buf_r_stall_2_we), - .wd (perf_counter_enable_2_dma_buf_r_stall_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_buf_r_stall_2_qs) - ); - - - // F[dma_aw_done_2]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_aw_done_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_aw_done_2_we), - .wd (perf_counter_enable_2_dma_aw_done_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_aw_done_2_qs) - ); - - - // F[dma_aw_bw_2]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_aw_bw_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_aw_bw_2_we), - .wd (perf_counter_enable_2_dma_aw_bw_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_aw_bw_2_qs) - ); - - - // F[dma_ar_done_2]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_ar_done_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_ar_done_2_we), - .wd (perf_counter_enable_2_dma_ar_done_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_ar_done_2_qs) - ); - - - // F[dma_ar_bw_2]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_ar_bw_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_ar_bw_2_we), - .wd (perf_counter_enable_2_dma_ar_bw_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_ar_bw_2_qs) - ); - - - // F[dma_r_done_2]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_r_done_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_r_done_2_we), - .wd (perf_counter_enable_2_dma_r_done_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_r_done_2_qs) - ); - - - // F[dma_r_bw_2]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_r_bw_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_r_bw_2_we), - .wd (perf_counter_enable_2_dma_r_bw_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_r_bw_2_qs) - ); - - - // F[dma_w_done_2]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_w_done_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_w_done_2_we), - .wd (perf_counter_enable_2_dma_w_done_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_w_done_2_qs) - ); - - - // F[dma_w_bw_2]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_w_bw_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_w_bw_2_we), - .wd (perf_counter_enable_2_dma_w_bw_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_w_bw_2_qs) - ); - - - // F[dma_b_done_2]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_b_done_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_b_done_2_we), - .wd (perf_counter_enable_2_dma_b_done_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_b_done_2_qs) - ); - - - // F[dma_busy_2]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_dma_busy_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_dma_busy_2_we), - .wd (perf_counter_enable_2_dma_busy_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_dma_busy_2_qs) - ); - - - // F[icache_miss_2]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_icache_miss_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_icache_miss_2_we), - .wd (perf_counter_enable_2_icache_miss_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_icache_miss_2_qs) - ); - - - // F[icache_hit_2]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_icache_hit_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_icache_hit_2_we), - .wd (perf_counter_enable_2_icache_hit_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_icache_hit_2_qs) - ); - - - // F[icache_prefetch_2]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_icache_prefetch_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_icache_prefetch_2_we), - .wd (perf_counter_enable_2_icache_prefetch_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_icache_prefetch_2_qs) - ); - - - // F[icache_double_hit_2]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_icache_double_hit_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_icache_double_hit_2_we), - .wd (perf_counter_enable_2_icache_double_hit_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_icache_double_hit_2_qs) - ); - - - // F[icache_stall_2]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_2_icache_stall_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_2_icache_stall_2_we), - .wd (perf_counter_enable_2_icache_stall_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[2].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_2_icache_stall_2_qs) - ); - - - // Subregister 3 of Multireg perf_counter_enable - // R[perf_counter_enable_3]: V(False) - - // F[cycle_3]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_cycle_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_cycle_3_we), - .wd (perf_counter_enable_3_cycle_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_cycle_3_qs) - ); - - - // F[tcdm_accessed_3]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_tcdm_accessed_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_tcdm_accessed_3_we), - .wd (perf_counter_enable_3_tcdm_accessed_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_tcdm_accessed_3_qs) - ); - - - // F[tcdm_congested_3]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_tcdm_congested_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_tcdm_congested_3_we), - .wd (perf_counter_enable_3_tcdm_congested_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_tcdm_congested_3_qs) - ); - - - // F[issue_fpu_3]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_issue_fpu_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_issue_fpu_3_we), - .wd (perf_counter_enable_3_issue_fpu_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_issue_fpu_3_qs) - ); - - - // F[issue_fpu_seq_3]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_issue_fpu_seq_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_issue_fpu_seq_3_we), - .wd (perf_counter_enable_3_issue_fpu_seq_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_issue_fpu_seq_3_qs) - ); - - - // F[issue_core_to_fpu_3]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_issue_core_to_fpu_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_issue_core_to_fpu_3_we), - .wd (perf_counter_enable_3_issue_core_to_fpu_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_issue_core_to_fpu_3_qs) - ); - - - // F[retired_instr_3]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_retired_instr_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_retired_instr_3_we), - .wd (perf_counter_enable_3_retired_instr_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_retired_instr_3_qs) - ); - - - // F[retired_load_3]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_retired_load_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_retired_load_3_we), - .wd (perf_counter_enable_3_retired_load_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_retired_load_3_qs) - ); - - - // F[retired_i_3]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_retired_i_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_retired_i_3_we), - .wd (perf_counter_enable_3_retired_i_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_retired_i_3_qs) - ); - - - // F[retired_acc_3]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_retired_acc_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_retired_acc_3_we), - .wd (perf_counter_enable_3_retired_acc_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_retired_acc_3_qs) - ); - - - // F[dma_aw_stall_3]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_aw_stall_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_aw_stall_3_we), - .wd (perf_counter_enable_3_dma_aw_stall_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_aw_stall_3_qs) - ); - - - // F[dma_ar_stall_3]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_ar_stall_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_ar_stall_3_we), - .wd (perf_counter_enable_3_dma_ar_stall_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_ar_stall_3_qs) - ); - - - // F[dma_r_stall_3]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_r_stall_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_r_stall_3_we), - .wd (perf_counter_enable_3_dma_r_stall_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_r_stall_3_qs) - ); - - - // F[dma_w_stall_3]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_w_stall_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_w_stall_3_we), - .wd (perf_counter_enable_3_dma_w_stall_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_w_stall_3_qs) - ); - - - // F[dma_buf_w_stall_3]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_buf_w_stall_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_buf_w_stall_3_we), - .wd (perf_counter_enable_3_dma_buf_w_stall_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_buf_w_stall_3_qs) - ); - - - // F[dma_buf_r_stall_3]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_buf_r_stall_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_buf_r_stall_3_we), - .wd (perf_counter_enable_3_dma_buf_r_stall_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_buf_r_stall_3_qs) - ); - - - // F[dma_aw_done_3]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_aw_done_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_aw_done_3_we), - .wd (perf_counter_enable_3_dma_aw_done_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_aw_done_3_qs) - ); - - - // F[dma_aw_bw_3]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_aw_bw_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_aw_bw_3_we), - .wd (perf_counter_enable_3_dma_aw_bw_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_aw_bw_3_qs) - ); - - - // F[dma_ar_done_3]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_ar_done_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_ar_done_3_we), - .wd (perf_counter_enable_3_dma_ar_done_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_ar_done_3_qs) - ); - - - // F[dma_ar_bw_3]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_ar_bw_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_ar_bw_3_we), - .wd (perf_counter_enable_3_dma_ar_bw_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_ar_bw_3_qs) - ); - - - // F[dma_r_done_3]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_r_done_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_r_done_3_we), - .wd (perf_counter_enable_3_dma_r_done_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_r_done_3_qs) - ); - - - // F[dma_r_bw_3]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_r_bw_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_r_bw_3_we), - .wd (perf_counter_enable_3_dma_r_bw_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_r_bw_3_qs) - ); - - - // F[dma_w_done_3]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_w_done_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_w_done_3_we), - .wd (perf_counter_enable_3_dma_w_done_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_w_done_3_qs) - ); - - - // F[dma_w_bw_3]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_w_bw_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_w_bw_3_we), - .wd (perf_counter_enable_3_dma_w_bw_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_w_bw_3_qs) - ); - - - // F[dma_b_done_3]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_b_done_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_b_done_3_we), - .wd (perf_counter_enable_3_dma_b_done_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_b_done_3_qs) - ); - - - // F[dma_busy_3]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_dma_busy_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_dma_busy_3_we), - .wd (perf_counter_enable_3_dma_busy_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_dma_busy_3_qs) - ); - - - // F[icache_miss_3]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_icache_miss_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_icache_miss_3_we), - .wd (perf_counter_enable_3_icache_miss_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_icache_miss_3_qs) - ); - - - // F[icache_hit_3]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_icache_hit_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_icache_hit_3_we), - .wd (perf_counter_enable_3_icache_hit_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_icache_hit_3_qs) - ); - - - // F[icache_prefetch_3]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_icache_prefetch_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_icache_prefetch_3_we), - .wd (perf_counter_enable_3_icache_prefetch_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_icache_prefetch_3_qs) - ); - - - // F[icache_double_hit_3]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_icache_double_hit_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_icache_double_hit_3_we), - .wd (perf_counter_enable_3_icache_double_hit_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_icache_double_hit_3_qs) - ); - - - // F[icache_stall_3]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_3_icache_stall_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_3_icache_stall_3_we), - .wd (perf_counter_enable_3_icache_stall_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[3].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_3_icache_stall_3_qs) - ); - - - // Subregister 4 of Multireg perf_counter_enable - // R[perf_counter_enable_4]: V(False) - - // F[cycle_4]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_cycle_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_cycle_4_we), - .wd (perf_counter_enable_4_cycle_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_cycle_4_qs) - ); - - - // F[tcdm_accessed_4]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_tcdm_accessed_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_tcdm_accessed_4_we), - .wd (perf_counter_enable_4_tcdm_accessed_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_tcdm_accessed_4_qs) - ); - - - // F[tcdm_congested_4]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_tcdm_congested_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_tcdm_congested_4_we), - .wd (perf_counter_enable_4_tcdm_congested_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_tcdm_congested_4_qs) - ); - - - // F[issue_fpu_4]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_issue_fpu_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_issue_fpu_4_we), - .wd (perf_counter_enable_4_issue_fpu_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_issue_fpu_4_qs) - ); - - - // F[issue_fpu_seq_4]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_issue_fpu_seq_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_issue_fpu_seq_4_we), - .wd (perf_counter_enable_4_issue_fpu_seq_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_issue_fpu_seq_4_qs) - ); - - - // F[issue_core_to_fpu_4]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_issue_core_to_fpu_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_issue_core_to_fpu_4_we), - .wd (perf_counter_enable_4_issue_core_to_fpu_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_issue_core_to_fpu_4_qs) - ); - - - // F[retired_instr_4]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_retired_instr_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_retired_instr_4_we), - .wd (perf_counter_enable_4_retired_instr_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_retired_instr_4_qs) - ); - - - // F[retired_load_4]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_retired_load_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_retired_load_4_we), - .wd (perf_counter_enable_4_retired_load_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_retired_load_4_qs) - ); - - - // F[retired_i_4]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_retired_i_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_retired_i_4_we), - .wd (perf_counter_enable_4_retired_i_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_retired_i_4_qs) - ); - - - // F[retired_acc_4]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_retired_acc_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_retired_acc_4_we), - .wd (perf_counter_enable_4_retired_acc_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_retired_acc_4_qs) - ); - - - // F[dma_aw_stall_4]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_aw_stall_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_aw_stall_4_we), - .wd (perf_counter_enable_4_dma_aw_stall_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_aw_stall_4_qs) - ); - - - // F[dma_ar_stall_4]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_ar_stall_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_ar_stall_4_we), - .wd (perf_counter_enable_4_dma_ar_stall_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_ar_stall_4_qs) - ); - - - // F[dma_r_stall_4]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_r_stall_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_r_stall_4_we), - .wd (perf_counter_enable_4_dma_r_stall_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_r_stall_4_qs) - ); - - - // F[dma_w_stall_4]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_w_stall_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_w_stall_4_we), - .wd (perf_counter_enable_4_dma_w_stall_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_w_stall_4_qs) - ); - - - // F[dma_buf_w_stall_4]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_buf_w_stall_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_buf_w_stall_4_we), - .wd (perf_counter_enable_4_dma_buf_w_stall_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_buf_w_stall_4_qs) - ); - - - // F[dma_buf_r_stall_4]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_buf_r_stall_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_buf_r_stall_4_we), - .wd (perf_counter_enable_4_dma_buf_r_stall_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_buf_r_stall_4_qs) - ); - - - // F[dma_aw_done_4]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_aw_done_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_aw_done_4_we), - .wd (perf_counter_enable_4_dma_aw_done_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_aw_done_4_qs) - ); - - - // F[dma_aw_bw_4]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_aw_bw_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_aw_bw_4_we), - .wd (perf_counter_enable_4_dma_aw_bw_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_aw_bw_4_qs) - ); - - - // F[dma_ar_done_4]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_ar_done_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_ar_done_4_we), - .wd (perf_counter_enable_4_dma_ar_done_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_ar_done_4_qs) - ); - - - // F[dma_ar_bw_4]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_ar_bw_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_ar_bw_4_we), - .wd (perf_counter_enable_4_dma_ar_bw_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_ar_bw_4_qs) - ); - - - // F[dma_r_done_4]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_r_done_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_r_done_4_we), - .wd (perf_counter_enable_4_dma_r_done_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_r_done_4_qs) - ); - - - // F[dma_r_bw_4]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_r_bw_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_r_bw_4_we), - .wd (perf_counter_enable_4_dma_r_bw_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_r_bw_4_qs) - ); - - - // F[dma_w_done_4]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_w_done_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_w_done_4_we), - .wd (perf_counter_enable_4_dma_w_done_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_w_done_4_qs) - ); - - - // F[dma_w_bw_4]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_w_bw_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_w_bw_4_we), - .wd (perf_counter_enable_4_dma_w_bw_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_w_bw_4_qs) - ); - - - // F[dma_b_done_4]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_b_done_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_b_done_4_we), - .wd (perf_counter_enable_4_dma_b_done_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_b_done_4_qs) - ); - - - // F[dma_busy_4]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_dma_busy_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_dma_busy_4_we), - .wd (perf_counter_enable_4_dma_busy_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_dma_busy_4_qs) - ); - - - // F[icache_miss_4]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_icache_miss_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_icache_miss_4_we), - .wd (perf_counter_enable_4_icache_miss_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_icache_miss_4_qs) - ); - - - // F[icache_hit_4]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_icache_hit_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_icache_hit_4_we), - .wd (perf_counter_enable_4_icache_hit_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_icache_hit_4_qs) - ); - - - // F[icache_prefetch_4]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_icache_prefetch_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_icache_prefetch_4_we), - .wd (perf_counter_enable_4_icache_prefetch_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_icache_prefetch_4_qs) - ); - - - // F[icache_double_hit_4]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_icache_double_hit_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_icache_double_hit_4_we), - .wd (perf_counter_enable_4_icache_double_hit_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_icache_double_hit_4_qs) - ); - - - // F[icache_stall_4]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_4_icache_stall_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_4_icache_stall_4_we), - .wd (perf_counter_enable_4_icache_stall_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[4].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_4_icache_stall_4_qs) - ); - - - // Subregister 5 of Multireg perf_counter_enable - // R[perf_counter_enable_5]: V(False) - - // F[cycle_5]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_cycle_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_cycle_5_we), - .wd (perf_counter_enable_5_cycle_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_cycle_5_qs) - ); - - - // F[tcdm_accessed_5]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_tcdm_accessed_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_tcdm_accessed_5_we), - .wd (perf_counter_enable_5_tcdm_accessed_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_tcdm_accessed_5_qs) - ); - - - // F[tcdm_congested_5]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_tcdm_congested_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_tcdm_congested_5_we), - .wd (perf_counter_enable_5_tcdm_congested_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_tcdm_congested_5_qs) - ); - - - // F[issue_fpu_5]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_issue_fpu_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_issue_fpu_5_we), - .wd (perf_counter_enable_5_issue_fpu_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_issue_fpu_5_qs) - ); - - - // F[issue_fpu_seq_5]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_issue_fpu_seq_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_issue_fpu_seq_5_we), - .wd (perf_counter_enable_5_issue_fpu_seq_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_issue_fpu_seq_5_qs) - ); - - - // F[issue_core_to_fpu_5]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_issue_core_to_fpu_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_issue_core_to_fpu_5_we), - .wd (perf_counter_enable_5_issue_core_to_fpu_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_issue_core_to_fpu_5_qs) - ); - - - // F[retired_instr_5]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_retired_instr_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_retired_instr_5_we), - .wd (perf_counter_enable_5_retired_instr_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_retired_instr_5_qs) - ); - - - // F[retired_load_5]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_retired_load_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_retired_load_5_we), - .wd (perf_counter_enable_5_retired_load_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_retired_load_5_qs) - ); - - - // F[retired_i_5]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_retired_i_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_retired_i_5_we), - .wd (perf_counter_enable_5_retired_i_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_retired_i_5_qs) - ); - - - // F[retired_acc_5]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_retired_acc_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_retired_acc_5_we), - .wd (perf_counter_enable_5_retired_acc_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_retired_acc_5_qs) - ); - - - // F[dma_aw_stall_5]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_aw_stall_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_aw_stall_5_we), - .wd (perf_counter_enable_5_dma_aw_stall_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_aw_stall_5_qs) - ); - - - // F[dma_ar_stall_5]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_ar_stall_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_ar_stall_5_we), - .wd (perf_counter_enable_5_dma_ar_stall_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_ar_stall_5_qs) - ); - - - // F[dma_r_stall_5]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_r_stall_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_r_stall_5_we), - .wd (perf_counter_enable_5_dma_r_stall_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_r_stall_5_qs) - ); - - - // F[dma_w_stall_5]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_w_stall_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_w_stall_5_we), - .wd (perf_counter_enable_5_dma_w_stall_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_w_stall_5_qs) - ); - - - // F[dma_buf_w_stall_5]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_buf_w_stall_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_buf_w_stall_5_we), - .wd (perf_counter_enable_5_dma_buf_w_stall_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_buf_w_stall_5_qs) - ); - - - // F[dma_buf_r_stall_5]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_buf_r_stall_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_buf_r_stall_5_we), - .wd (perf_counter_enable_5_dma_buf_r_stall_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_buf_r_stall_5_qs) - ); - - - // F[dma_aw_done_5]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_aw_done_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_aw_done_5_we), - .wd (perf_counter_enable_5_dma_aw_done_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_aw_done_5_qs) - ); - - - // F[dma_aw_bw_5]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_aw_bw_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_aw_bw_5_we), - .wd (perf_counter_enable_5_dma_aw_bw_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_aw_bw_5_qs) - ); - - - // F[dma_ar_done_5]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_ar_done_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_ar_done_5_we), - .wd (perf_counter_enable_5_dma_ar_done_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_ar_done_5_qs) - ); - - - // F[dma_ar_bw_5]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_ar_bw_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_ar_bw_5_we), - .wd (perf_counter_enable_5_dma_ar_bw_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_ar_bw_5_qs) - ); - - - // F[dma_r_done_5]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_r_done_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_r_done_5_we), - .wd (perf_counter_enable_5_dma_r_done_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_r_done_5_qs) - ); - - - // F[dma_r_bw_5]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_r_bw_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_r_bw_5_we), - .wd (perf_counter_enable_5_dma_r_bw_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_r_bw_5_qs) - ); - - - // F[dma_w_done_5]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_w_done_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_w_done_5_we), - .wd (perf_counter_enable_5_dma_w_done_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_w_done_5_qs) - ); - - - // F[dma_w_bw_5]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_w_bw_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_w_bw_5_we), - .wd (perf_counter_enable_5_dma_w_bw_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_w_bw_5_qs) - ); - - - // F[dma_b_done_5]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_b_done_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_b_done_5_we), - .wd (perf_counter_enable_5_dma_b_done_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_b_done_5_qs) - ); - - - // F[dma_busy_5]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_dma_busy_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_dma_busy_5_we), - .wd (perf_counter_enable_5_dma_busy_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_dma_busy_5_qs) - ); - - - // F[icache_miss_5]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_icache_miss_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_icache_miss_5_we), - .wd (perf_counter_enable_5_icache_miss_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_icache_miss_5_qs) - ); - - - // F[icache_hit_5]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_icache_hit_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_icache_hit_5_we), - .wd (perf_counter_enable_5_icache_hit_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_icache_hit_5_qs) - ); - - - // F[icache_prefetch_5]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_icache_prefetch_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_icache_prefetch_5_we), - .wd (perf_counter_enable_5_icache_prefetch_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_icache_prefetch_5_qs) - ); - - - // F[icache_double_hit_5]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_icache_double_hit_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_icache_double_hit_5_we), - .wd (perf_counter_enable_5_icache_double_hit_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_icache_double_hit_5_qs) - ); - - - // F[icache_stall_5]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_5_icache_stall_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_5_icache_stall_5_we), - .wd (perf_counter_enable_5_icache_stall_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[5].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_5_icache_stall_5_qs) - ); - - - // Subregister 6 of Multireg perf_counter_enable - // R[perf_counter_enable_6]: V(False) - - // F[cycle_6]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_cycle_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_cycle_6_we), - .wd (perf_counter_enable_6_cycle_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_cycle_6_qs) - ); - - - // F[tcdm_accessed_6]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_tcdm_accessed_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_tcdm_accessed_6_we), - .wd (perf_counter_enable_6_tcdm_accessed_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_tcdm_accessed_6_qs) - ); - - - // F[tcdm_congested_6]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_tcdm_congested_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_tcdm_congested_6_we), - .wd (perf_counter_enable_6_tcdm_congested_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_tcdm_congested_6_qs) - ); - - - // F[issue_fpu_6]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_issue_fpu_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_issue_fpu_6_we), - .wd (perf_counter_enable_6_issue_fpu_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_issue_fpu_6_qs) - ); - - - // F[issue_fpu_seq_6]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_issue_fpu_seq_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_issue_fpu_seq_6_we), - .wd (perf_counter_enable_6_issue_fpu_seq_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_issue_fpu_seq_6_qs) - ); - - - // F[issue_core_to_fpu_6]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_issue_core_to_fpu_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_issue_core_to_fpu_6_we), - .wd (perf_counter_enable_6_issue_core_to_fpu_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_issue_core_to_fpu_6_qs) - ); - - - // F[retired_instr_6]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_retired_instr_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_retired_instr_6_we), - .wd (perf_counter_enable_6_retired_instr_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_retired_instr_6_qs) - ); - - - // F[retired_load_6]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_retired_load_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_retired_load_6_we), - .wd (perf_counter_enable_6_retired_load_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_retired_load_6_qs) - ); - - - // F[retired_i_6]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_retired_i_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_retired_i_6_we), - .wd (perf_counter_enable_6_retired_i_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_retired_i_6_qs) - ); - - - // F[retired_acc_6]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_retired_acc_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_retired_acc_6_we), - .wd (perf_counter_enable_6_retired_acc_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_retired_acc_6_qs) - ); - - - // F[dma_aw_stall_6]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_aw_stall_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_aw_stall_6_we), - .wd (perf_counter_enable_6_dma_aw_stall_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_aw_stall_6_qs) - ); - - - // F[dma_ar_stall_6]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_ar_stall_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_ar_stall_6_we), - .wd (perf_counter_enable_6_dma_ar_stall_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_ar_stall_6_qs) - ); - - - // F[dma_r_stall_6]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_r_stall_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_r_stall_6_we), - .wd (perf_counter_enable_6_dma_r_stall_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_r_stall_6_qs) - ); - - - // F[dma_w_stall_6]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_w_stall_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_w_stall_6_we), - .wd (perf_counter_enable_6_dma_w_stall_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_w_stall_6_qs) - ); - - - // F[dma_buf_w_stall_6]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_buf_w_stall_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_buf_w_stall_6_we), - .wd (perf_counter_enable_6_dma_buf_w_stall_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_buf_w_stall_6_qs) - ); - - - // F[dma_buf_r_stall_6]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_buf_r_stall_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_buf_r_stall_6_we), - .wd (perf_counter_enable_6_dma_buf_r_stall_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_buf_r_stall_6_qs) - ); - - - // F[dma_aw_done_6]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_aw_done_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_aw_done_6_we), - .wd (perf_counter_enable_6_dma_aw_done_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_aw_done_6_qs) - ); - - - // F[dma_aw_bw_6]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_aw_bw_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_aw_bw_6_we), - .wd (perf_counter_enable_6_dma_aw_bw_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_aw_bw_6_qs) - ); - - - // F[dma_ar_done_6]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_ar_done_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_ar_done_6_we), - .wd (perf_counter_enable_6_dma_ar_done_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_ar_done_6_qs) - ); - - - // F[dma_ar_bw_6]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_ar_bw_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_ar_bw_6_we), - .wd (perf_counter_enable_6_dma_ar_bw_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_ar_bw_6_qs) - ); - - - // F[dma_r_done_6]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_r_done_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_r_done_6_we), - .wd (perf_counter_enable_6_dma_r_done_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_r_done_6_qs) - ); - - - // F[dma_r_bw_6]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_r_bw_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_r_bw_6_we), - .wd (perf_counter_enable_6_dma_r_bw_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_r_bw_6_qs) - ); - - - // F[dma_w_done_6]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_w_done_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_w_done_6_we), - .wd (perf_counter_enable_6_dma_w_done_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_w_done_6_qs) - ); - - - // F[dma_w_bw_6]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_w_bw_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_w_bw_6_we), - .wd (perf_counter_enable_6_dma_w_bw_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_w_bw_6_qs) - ); - - - // F[dma_b_done_6]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_b_done_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_b_done_6_we), - .wd (perf_counter_enable_6_dma_b_done_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_b_done_6_qs) - ); - - - // F[dma_busy_6]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_dma_busy_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_dma_busy_6_we), - .wd (perf_counter_enable_6_dma_busy_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_dma_busy_6_qs) - ); - - - // F[icache_miss_6]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_icache_miss_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_icache_miss_6_we), - .wd (perf_counter_enable_6_icache_miss_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_icache_miss_6_qs) - ); - - - // F[icache_hit_6]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_icache_hit_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_icache_hit_6_we), - .wd (perf_counter_enable_6_icache_hit_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_icache_hit_6_qs) - ); - - - // F[icache_prefetch_6]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_icache_prefetch_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_icache_prefetch_6_we), - .wd (perf_counter_enable_6_icache_prefetch_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_icache_prefetch_6_qs) - ); - - - // F[icache_double_hit_6]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_icache_double_hit_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_icache_double_hit_6_we), - .wd (perf_counter_enable_6_icache_double_hit_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_icache_double_hit_6_qs) - ); - - - // F[icache_stall_6]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_6_icache_stall_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_6_icache_stall_6_we), - .wd (perf_counter_enable_6_icache_stall_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[6].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_6_icache_stall_6_qs) - ); - - - // Subregister 7 of Multireg perf_counter_enable - // R[perf_counter_enable_7]: V(False) - - // F[cycle_7]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_cycle_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_cycle_7_we), - .wd (perf_counter_enable_7_cycle_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_cycle_7_qs) - ); - - - // F[tcdm_accessed_7]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_tcdm_accessed_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_tcdm_accessed_7_we), - .wd (perf_counter_enable_7_tcdm_accessed_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_tcdm_accessed_7_qs) - ); - - - // F[tcdm_congested_7]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_tcdm_congested_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_tcdm_congested_7_we), - .wd (perf_counter_enable_7_tcdm_congested_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_tcdm_congested_7_qs) - ); - - - // F[issue_fpu_7]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_issue_fpu_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_issue_fpu_7_we), - .wd (perf_counter_enable_7_issue_fpu_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_issue_fpu_7_qs) - ); - - - // F[issue_fpu_seq_7]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_issue_fpu_seq_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_issue_fpu_seq_7_we), - .wd (perf_counter_enable_7_issue_fpu_seq_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_issue_fpu_seq_7_qs) - ); - - - // F[issue_core_to_fpu_7]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_issue_core_to_fpu_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_issue_core_to_fpu_7_we), - .wd (perf_counter_enable_7_issue_core_to_fpu_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_issue_core_to_fpu_7_qs) - ); - - - // F[retired_instr_7]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_retired_instr_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_retired_instr_7_we), - .wd (perf_counter_enable_7_retired_instr_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_retired_instr_7_qs) - ); - - - // F[retired_load_7]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_retired_load_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_retired_load_7_we), - .wd (perf_counter_enable_7_retired_load_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_retired_load_7_qs) - ); - - - // F[retired_i_7]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_retired_i_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_retired_i_7_we), - .wd (perf_counter_enable_7_retired_i_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_retired_i_7_qs) - ); - - - // F[retired_acc_7]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_retired_acc_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_retired_acc_7_we), - .wd (perf_counter_enable_7_retired_acc_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_retired_acc_7_qs) - ); - - - // F[dma_aw_stall_7]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_aw_stall_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_aw_stall_7_we), - .wd (perf_counter_enable_7_dma_aw_stall_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_aw_stall_7_qs) - ); - - - // F[dma_ar_stall_7]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_ar_stall_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_ar_stall_7_we), - .wd (perf_counter_enable_7_dma_ar_stall_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_ar_stall_7_qs) - ); - - - // F[dma_r_stall_7]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_r_stall_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_r_stall_7_we), - .wd (perf_counter_enable_7_dma_r_stall_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_r_stall_7_qs) - ); - - - // F[dma_w_stall_7]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_w_stall_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_w_stall_7_we), - .wd (perf_counter_enable_7_dma_w_stall_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_w_stall_7_qs) - ); - - - // F[dma_buf_w_stall_7]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_buf_w_stall_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_buf_w_stall_7_we), - .wd (perf_counter_enable_7_dma_buf_w_stall_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_buf_w_stall_7_qs) - ); - - - // F[dma_buf_r_stall_7]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_buf_r_stall_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_buf_r_stall_7_we), - .wd (perf_counter_enable_7_dma_buf_r_stall_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_buf_r_stall_7_qs) - ); - - - // F[dma_aw_done_7]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_aw_done_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_aw_done_7_we), - .wd (perf_counter_enable_7_dma_aw_done_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_aw_done_7_qs) - ); - - - // F[dma_aw_bw_7]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_aw_bw_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_aw_bw_7_we), - .wd (perf_counter_enable_7_dma_aw_bw_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_aw_bw_7_qs) - ); - - - // F[dma_ar_done_7]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_ar_done_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_ar_done_7_we), - .wd (perf_counter_enable_7_dma_ar_done_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_ar_done_7_qs) - ); - - - // F[dma_ar_bw_7]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_ar_bw_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_ar_bw_7_we), - .wd (perf_counter_enable_7_dma_ar_bw_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_ar_bw_7_qs) - ); - - - // F[dma_r_done_7]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_r_done_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_r_done_7_we), - .wd (perf_counter_enable_7_dma_r_done_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_r_done_7_qs) - ); - - - // F[dma_r_bw_7]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_r_bw_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_r_bw_7_we), - .wd (perf_counter_enable_7_dma_r_bw_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_r_bw_7_qs) - ); - - - // F[dma_w_done_7]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_w_done_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_w_done_7_we), - .wd (perf_counter_enable_7_dma_w_done_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_w_done_7_qs) - ); - - - // F[dma_w_bw_7]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_w_bw_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_w_bw_7_we), - .wd (perf_counter_enable_7_dma_w_bw_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_w_bw_7_qs) - ); - - - // F[dma_b_done_7]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_b_done_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_b_done_7_we), - .wd (perf_counter_enable_7_dma_b_done_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_b_done_7_qs) - ); - - - // F[dma_busy_7]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_dma_busy_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_dma_busy_7_we), - .wd (perf_counter_enable_7_dma_busy_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_dma_busy_7_qs) - ); - - - // F[icache_miss_7]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_icache_miss_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_icache_miss_7_we), - .wd (perf_counter_enable_7_icache_miss_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_icache_miss_7_qs) - ); - - - // F[icache_hit_7]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_icache_hit_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_icache_hit_7_we), - .wd (perf_counter_enable_7_icache_hit_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_icache_hit_7_qs) - ); - - - // F[icache_prefetch_7]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_icache_prefetch_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_icache_prefetch_7_we), - .wd (perf_counter_enable_7_icache_prefetch_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_icache_prefetch_7_qs) - ); - - - // F[icache_double_hit_7]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_icache_double_hit_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_icache_double_hit_7_we), - .wd (perf_counter_enable_7_icache_double_hit_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_icache_double_hit_7_qs) - ); - - - // F[icache_stall_7]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_7_icache_stall_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_7_icache_stall_7_we), - .wd (perf_counter_enable_7_icache_stall_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[7].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_7_icache_stall_7_qs) - ); - - - // Subregister 8 of Multireg perf_counter_enable - // R[perf_counter_enable_8]: V(False) - - // F[cycle_8]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_cycle_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_cycle_8_we), - .wd (perf_counter_enable_8_cycle_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_cycle_8_qs) - ); - - - // F[tcdm_accessed_8]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_tcdm_accessed_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_tcdm_accessed_8_we), - .wd (perf_counter_enable_8_tcdm_accessed_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_tcdm_accessed_8_qs) - ); - - - // F[tcdm_congested_8]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_tcdm_congested_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_tcdm_congested_8_we), - .wd (perf_counter_enable_8_tcdm_congested_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_tcdm_congested_8_qs) - ); - - - // F[issue_fpu_8]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_issue_fpu_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_issue_fpu_8_we), - .wd (perf_counter_enable_8_issue_fpu_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_issue_fpu_8_qs) - ); - - - // F[issue_fpu_seq_8]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_issue_fpu_seq_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_issue_fpu_seq_8_we), - .wd (perf_counter_enable_8_issue_fpu_seq_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_issue_fpu_seq_8_qs) - ); - - - // F[issue_core_to_fpu_8]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_issue_core_to_fpu_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_issue_core_to_fpu_8_we), - .wd (perf_counter_enable_8_issue_core_to_fpu_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_issue_core_to_fpu_8_qs) - ); - - - // F[retired_instr_8]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_retired_instr_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_retired_instr_8_we), - .wd (perf_counter_enable_8_retired_instr_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_retired_instr_8_qs) - ); - - - // F[retired_load_8]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_retired_load_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_retired_load_8_we), - .wd (perf_counter_enable_8_retired_load_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_retired_load_8_qs) - ); - - - // F[retired_i_8]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_retired_i_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_retired_i_8_we), - .wd (perf_counter_enable_8_retired_i_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_retired_i_8_qs) - ); - - - // F[retired_acc_8]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_retired_acc_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_retired_acc_8_we), - .wd (perf_counter_enable_8_retired_acc_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_retired_acc_8_qs) - ); - - - // F[dma_aw_stall_8]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_aw_stall_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_aw_stall_8_we), - .wd (perf_counter_enable_8_dma_aw_stall_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_aw_stall_8_qs) - ); - - - // F[dma_ar_stall_8]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_ar_stall_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_ar_stall_8_we), - .wd (perf_counter_enable_8_dma_ar_stall_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_ar_stall_8_qs) - ); - - - // F[dma_r_stall_8]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_r_stall_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_r_stall_8_we), - .wd (perf_counter_enable_8_dma_r_stall_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_r_stall_8_qs) - ); - - - // F[dma_w_stall_8]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_w_stall_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_w_stall_8_we), - .wd (perf_counter_enable_8_dma_w_stall_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_w_stall_8_qs) - ); - - - // F[dma_buf_w_stall_8]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_buf_w_stall_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_buf_w_stall_8_we), - .wd (perf_counter_enable_8_dma_buf_w_stall_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_buf_w_stall_8_qs) - ); - - - // F[dma_buf_r_stall_8]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_buf_r_stall_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_buf_r_stall_8_we), - .wd (perf_counter_enable_8_dma_buf_r_stall_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_buf_r_stall_8_qs) - ); - - - // F[dma_aw_done_8]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_aw_done_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_aw_done_8_we), - .wd (perf_counter_enable_8_dma_aw_done_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_aw_done_8_qs) - ); - - - // F[dma_aw_bw_8]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_aw_bw_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_aw_bw_8_we), - .wd (perf_counter_enable_8_dma_aw_bw_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_aw_bw_8_qs) - ); - - - // F[dma_ar_done_8]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_ar_done_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_ar_done_8_we), - .wd (perf_counter_enable_8_dma_ar_done_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_ar_done_8_qs) - ); - - - // F[dma_ar_bw_8]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_ar_bw_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_ar_bw_8_we), - .wd (perf_counter_enable_8_dma_ar_bw_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_ar_bw_8_qs) - ); - - - // F[dma_r_done_8]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_r_done_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_r_done_8_we), - .wd (perf_counter_enable_8_dma_r_done_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_r_done_8_qs) - ); - - - // F[dma_r_bw_8]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_r_bw_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_r_bw_8_we), - .wd (perf_counter_enable_8_dma_r_bw_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_r_bw_8_qs) - ); - - - // F[dma_w_done_8]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_w_done_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_w_done_8_we), - .wd (perf_counter_enable_8_dma_w_done_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_w_done_8_qs) - ); - - - // F[dma_w_bw_8]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_w_bw_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_w_bw_8_we), - .wd (perf_counter_enable_8_dma_w_bw_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_w_bw_8_qs) - ); - - - // F[dma_b_done_8]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_b_done_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_b_done_8_we), - .wd (perf_counter_enable_8_dma_b_done_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_b_done_8_qs) - ); - - - // F[dma_busy_8]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_dma_busy_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_dma_busy_8_we), - .wd (perf_counter_enable_8_dma_busy_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_dma_busy_8_qs) - ); - - - // F[icache_miss_8]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_icache_miss_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_icache_miss_8_we), - .wd (perf_counter_enable_8_icache_miss_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_icache_miss_8_qs) - ); - - - // F[icache_hit_8]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_icache_hit_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_icache_hit_8_we), - .wd (perf_counter_enable_8_icache_hit_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_icache_hit_8_qs) - ); - - - // F[icache_prefetch_8]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_icache_prefetch_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_icache_prefetch_8_we), - .wd (perf_counter_enable_8_icache_prefetch_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_icache_prefetch_8_qs) - ); - - - // F[icache_double_hit_8]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_icache_double_hit_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_icache_double_hit_8_we), - .wd (perf_counter_enable_8_icache_double_hit_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_icache_double_hit_8_qs) - ); - - - // F[icache_stall_8]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_8_icache_stall_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_8_icache_stall_8_we), - .wd (perf_counter_enable_8_icache_stall_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[8].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_8_icache_stall_8_qs) - ); - - - // Subregister 9 of Multireg perf_counter_enable - // R[perf_counter_enable_9]: V(False) - - // F[cycle_9]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_cycle_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_cycle_9_we), - .wd (perf_counter_enable_9_cycle_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_cycle_9_qs) - ); - - - // F[tcdm_accessed_9]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_tcdm_accessed_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_tcdm_accessed_9_we), - .wd (perf_counter_enable_9_tcdm_accessed_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_tcdm_accessed_9_qs) - ); - - - // F[tcdm_congested_9]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_tcdm_congested_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_tcdm_congested_9_we), - .wd (perf_counter_enable_9_tcdm_congested_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_tcdm_congested_9_qs) - ); - - - // F[issue_fpu_9]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_issue_fpu_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_issue_fpu_9_we), - .wd (perf_counter_enable_9_issue_fpu_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_issue_fpu_9_qs) - ); - - - // F[issue_fpu_seq_9]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_issue_fpu_seq_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_issue_fpu_seq_9_we), - .wd (perf_counter_enable_9_issue_fpu_seq_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_issue_fpu_seq_9_qs) - ); - - - // F[issue_core_to_fpu_9]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_issue_core_to_fpu_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_issue_core_to_fpu_9_we), - .wd (perf_counter_enable_9_issue_core_to_fpu_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_issue_core_to_fpu_9_qs) - ); - - - // F[retired_instr_9]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_retired_instr_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_retired_instr_9_we), - .wd (perf_counter_enable_9_retired_instr_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_retired_instr_9_qs) - ); - - - // F[retired_load_9]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_retired_load_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_retired_load_9_we), - .wd (perf_counter_enable_9_retired_load_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_retired_load_9_qs) - ); - - - // F[retired_i_9]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_retired_i_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_retired_i_9_we), - .wd (perf_counter_enable_9_retired_i_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_retired_i_9_qs) - ); - - - // F[retired_acc_9]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_retired_acc_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_retired_acc_9_we), - .wd (perf_counter_enable_9_retired_acc_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_retired_acc_9_qs) - ); - - - // F[dma_aw_stall_9]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_aw_stall_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_aw_stall_9_we), - .wd (perf_counter_enable_9_dma_aw_stall_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_aw_stall_9_qs) - ); - - - // F[dma_ar_stall_9]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_ar_stall_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_ar_stall_9_we), - .wd (perf_counter_enable_9_dma_ar_stall_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_ar_stall_9_qs) - ); - - - // F[dma_r_stall_9]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_r_stall_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_r_stall_9_we), - .wd (perf_counter_enable_9_dma_r_stall_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_r_stall_9_qs) - ); - - - // F[dma_w_stall_9]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_w_stall_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_w_stall_9_we), - .wd (perf_counter_enable_9_dma_w_stall_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_w_stall_9_qs) - ); - - - // F[dma_buf_w_stall_9]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_buf_w_stall_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_buf_w_stall_9_we), - .wd (perf_counter_enable_9_dma_buf_w_stall_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_buf_w_stall_9_qs) - ); - - - // F[dma_buf_r_stall_9]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_buf_r_stall_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_buf_r_stall_9_we), - .wd (perf_counter_enable_9_dma_buf_r_stall_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_buf_r_stall_9_qs) - ); - - - // F[dma_aw_done_9]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_aw_done_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_aw_done_9_we), - .wd (perf_counter_enable_9_dma_aw_done_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_aw_done_9_qs) - ); - - - // F[dma_aw_bw_9]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_aw_bw_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_aw_bw_9_we), - .wd (perf_counter_enable_9_dma_aw_bw_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_aw_bw_9_qs) - ); - - - // F[dma_ar_done_9]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_ar_done_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_ar_done_9_we), - .wd (perf_counter_enable_9_dma_ar_done_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_ar_done_9_qs) - ); - - - // F[dma_ar_bw_9]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_ar_bw_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_ar_bw_9_we), - .wd (perf_counter_enable_9_dma_ar_bw_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_ar_bw_9_qs) - ); - - - // F[dma_r_done_9]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_r_done_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_r_done_9_we), - .wd (perf_counter_enable_9_dma_r_done_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_r_done_9_qs) - ); - - - // F[dma_r_bw_9]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_r_bw_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_r_bw_9_we), - .wd (perf_counter_enable_9_dma_r_bw_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_r_bw_9_qs) - ); - - - // F[dma_w_done_9]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_w_done_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_w_done_9_we), - .wd (perf_counter_enable_9_dma_w_done_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_w_done_9_qs) - ); - - - // F[dma_w_bw_9]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_w_bw_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_w_bw_9_we), - .wd (perf_counter_enable_9_dma_w_bw_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_w_bw_9_qs) - ); - - - // F[dma_b_done_9]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_b_done_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_b_done_9_we), - .wd (perf_counter_enable_9_dma_b_done_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_b_done_9_qs) - ); - - - // F[dma_busy_9]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_dma_busy_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_dma_busy_9_we), - .wd (perf_counter_enable_9_dma_busy_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_dma_busy_9_qs) - ); - - - // F[icache_miss_9]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_icache_miss_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_icache_miss_9_we), - .wd (perf_counter_enable_9_icache_miss_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_icache_miss_9_qs) - ); - - - // F[icache_hit_9]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_icache_hit_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_icache_hit_9_we), - .wd (perf_counter_enable_9_icache_hit_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_icache_hit_9_qs) - ); - - - // F[icache_prefetch_9]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_icache_prefetch_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_icache_prefetch_9_we), - .wd (perf_counter_enable_9_icache_prefetch_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_icache_prefetch_9_qs) - ); - - - // F[icache_double_hit_9]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_icache_double_hit_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_icache_double_hit_9_we), - .wd (perf_counter_enable_9_icache_double_hit_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_icache_double_hit_9_qs) - ); - - - // F[icache_stall_9]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_9_icache_stall_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_9_icache_stall_9_we), - .wd (perf_counter_enable_9_icache_stall_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[9].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_9_icache_stall_9_qs) - ); - - - // Subregister 10 of Multireg perf_counter_enable - // R[perf_counter_enable_10]: V(False) - - // F[cycle_10]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_cycle_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_cycle_10_we), - .wd (perf_counter_enable_10_cycle_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_cycle_10_qs) - ); - - - // F[tcdm_accessed_10]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_tcdm_accessed_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_tcdm_accessed_10_we), - .wd (perf_counter_enable_10_tcdm_accessed_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_tcdm_accessed_10_qs) - ); - - - // F[tcdm_congested_10]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_tcdm_congested_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_tcdm_congested_10_we), - .wd (perf_counter_enable_10_tcdm_congested_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_tcdm_congested_10_qs) - ); - - - // F[issue_fpu_10]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_issue_fpu_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_issue_fpu_10_we), - .wd (perf_counter_enable_10_issue_fpu_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_issue_fpu_10_qs) - ); - - - // F[issue_fpu_seq_10]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_issue_fpu_seq_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_issue_fpu_seq_10_we), - .wd (perf_counter_enable_10_issue_fpu_seq_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_issue_fpu_seq_10_qs) - ); - - - // F[issue_core_to_fpu_10]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_issue_core_to_fpu_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_issue_core_to_fpu_10_we), - .wd (perf_counter_enable_10_issue_core_to_fpu_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_issue_core_to_fpu_10_qs) - ); - - - // F[retired_instr_10]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_retired_instr_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_retired_instr_10_we), - .wd (perf_counter_enable_10_retired_instr_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_retired_instr_10_qs) - ); - - - // F[retired_load_10]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_retired_load_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_retired_load_10_we), - .wd (perf_counter_enable_10_retired_load_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_retired_load_10_qs) - ); - - - // F[retired_i_10]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_retired_i_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_retired_i_10_we), - .wd (perf_counter_enable_10_retired_i_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_retired_i_10_qs) - ); - - - // F[retired_acc_10]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_retired_acc_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_retired_acc_10_we), - .wd (perf_counter_enable_10_retired_acc_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_retired_acc_10_qs) - ); - - - // F[dma_aw_stall_10]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_aw_stall_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_aw_stall_10_we), - .wd (perf_counter_enable_10_dma_aw_stall_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_aw_stall_10_qs) - ); - - - // F[dma_ar_stall_10]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_ar_stall_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_ar_stall_10_we), - .wd (perf_counter_enable_10_dma_ar_stall_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_ar_stall_10_qs) - ); - - - // F[dma_r_stall_10]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_r_stall_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_r_stall_10_we), - .wd (perf_counter_enable_10_dma_r_stall_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_r_stall_10_qs) - ); - - - // F[dma_w_stall_10]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_w_stall_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_w_stall_10_we), - .wd (perf_counter_enable_10_dma_w_stall_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_w_stall_10_qs) - ); - - - // F[dma_buf_w_stall_10]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_buf_w_stall_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_buf_w_stall_10_we), - .wd (perf_counter_enable_10_dma_buf_w_stall_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_buf_w_stall_10_qs) - ); - - - // F[dma_buf_r_stall_10]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_buf_r_stall_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_buf_r_stall_10_we), - .wd (perf_counter_enable_10_dma_buf_r_stall_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_buf_r_stall_10_qs) - ); - - - // F[dma_aw_done_10]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_aw_done_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_aw_done_10_we), - .wd (perf_counter_enable_10_dma_aw_done_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_aw_done_10_qs) - ); - - - // F[dma_aw_bw_10]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_aw_bw_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_aw_bw_10_we), - .wd (perf_counter_enable_10_dma_aw_bw_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_aw_bw_10_qs) - ); - - - // F[dma_ar_done_10]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_ar_done_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_ar_done_10_we), - .wd (perf_counter_enable_10_dma_ar_done_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_ar_done_10_qs) - ); - - - // F[dma_ar_bw_10]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_ar_bw_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_ar_bw_10_we), - .wd (perf_counter_enable_10_dma_ar_bw_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_ar_bw_10_qs) - ); - - - // F[dma_r_done_10]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_r_done_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_r_done_10_we), - .wd (perf_counter_enable_10_dma_r_done_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_r_done_10_qs) - ); - - - // F[dma_r_bw_10]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_r_bw_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_r_bw_10_we), - .wd (perf_counter_enable_10_dma_r_bw_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_r_bw_10_qs) - ); - - - // F[dma_w_done_10]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_w_done_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_w_done_10_we), - .wd (perf_counter_enable_10_dma_w_done_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_w_done_10_qs) - ); - - - // F[dma_w_bw_10]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_w_bw_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_w_bw_10_we), - .wd (perf_counter_enable_10_dma_w_bw_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_w_bw_10_qs) - ); - - - // F[dma_b_done_10]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_b_done_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_b_done_10_we), - .wd (perf_counter_enable_10_dma_b_done_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_b_done_10_qs) - ); - - - // F[dma_busy_10]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_dma_busy_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_dma_busy_10_we), - .wd (perf_counter_enable_10_dma_busy_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_dma_busy_10_qs) - ); - - - // F[icache_miss_10]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_icache_miss_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_icache_miss_10_we), - .wd (perf_counter_enable_10_icache_miss_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_icache_miss_10_qs) - ); - - - // F[icache_hit_10]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_icache_hit_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_icache_hit_10_we), - .wd (perf_counter_enable_10_icache_hit_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_icache_hit_10_qs) - ); - - - // F[icache_prefetch_10]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_icache_prefetch_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_icache_prefetch_10_we), - .wd (perf_counter_enable_10_icache_prefetch_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_icache_prefetch_10_qs) - ); - - - // F[icache_double_hit_10]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_icache_double_hit_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_icache_double_hit_10_we), - .wd (perf_counter_enable_10_icache_double_hit_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_icache_double_hit_10_qs) - ); - - - // F[icache_stall_10]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_10_icache_stall_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_10_icache_stall_10_we), - .wd (perf_counter_enable_10_icache_stall_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[10].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_10_icache_stall_10_qs) - ); - - - // Subregister 11 of Multireg perf_counter_enable - // R[perf_counter_enable_11]: V(False) - - // F[cycle_11]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_cycle_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_cycle_11_we), - .wd (perf_counter_enable_11_cycle_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_cycle_11_qs) - ); - - - // F[tcdm_accessed_11]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_tcdm_accessed_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_tcdm_accessed_11_we), - .wd (perf_counter_enable_11_tcdm_accessed_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_tcdm_accessed_11_qs) - ); - - - // F[tcdm_congested_11]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_tcdm_congested_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_tcdm_congested_11_we), - .wd (perf_counter_enable_11_tcdm_congested_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_tcdm_congested_11_qs) - ); - - - // F[issue_fpu_11]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_issue_fpu_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_issue_fpu_11_we), - .wd (perf_counter_enable_11_issue_fpu_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_issue_fpu_11_qs) - ); - - - // F[issue_fpu_seq_11]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_issue_fpu_seq_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_issue_fpu_seq_11_we), - .wd (perf_counter_enable_11_issue_fpu_seq_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_issue_fpu_seq_11_qs) - ); - - - // F[issue_core_to_fpu_11]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_issue_core_to_fpu_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_issue_core_to_fpu_11_we), - .wd (perf_counter_enable_11_issue_core_to_fpu_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_issue_core_to_fpu_11_qs) - ); - - - // F[retired_instr_11]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_retired_instr_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_retired_instr_11_we), - .wd (perf_counter_enable_11_retired_instr_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_retired_instr_11_qs) - ); - - - // F[retired_load_11]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_retired_load_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_retired_load_11_we), - .wd (perf_counter_enable_11_retired_load_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_retired_load_11_qs) - ); - - - // F[retired_i_11]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_retired_i_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_retired_i_11_we), - .wd (perf_counter_enable_11_retired_i_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_retired_i_11_qs) - ); - - - // F[retired_acc_11]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_retired_acc_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_retired_acc_11_we), - .wd (perf_counter_enable_11_retired_acc_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_retired_acc_11_qs) - ); - - - // F[dma_aw_stall_11]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_aw_stall_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_aw_stall_11_we), - .wd (perf_counter_enable_11_dma_aw_stall_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_aw_stall_11_qs) - ); - - - // F[dma_ar_stall_11]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_ar_stall_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_ar_stall_11_we), - .wd (perf_counter_enable_11_dma_ar_stall_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_ar_stall_11_qs) - ); - - - // F[dma_r_stall_11]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_r_stall_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_r_stall_11_we), - .wd (perf_counter_enable_11_dma_r_stall_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_r_stall_11_qs) - ); - - - // F[dma_w_stall_11]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_w_stall_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_w_stall_11_we), - .wd (perf_counter_enable_11_dma_w_stall_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_w_stall_11_qs) - ); - - - // F[dma_buf_w_stall_11]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_buf_w_stall_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_buf_w_stall_11_we), - .wd (perf_counter_enable_11_dma_buf_w_stall_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_buf_w_stall_11_qs) - ); - - - // F[dma_buf_r_stall_11]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_buf_r_stall_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_buf_r_stall_11_we), - .wd (perf_counter_enable_11_dma_buf_r_stall_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_buf_r_stall_11_qs) - ); - - - // F[dma_aw_done_11]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_aw_done_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_aw_done_11_we), - .wd (perf_counter_enable_11_dma_aw_done_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_aw_done_11_qs) - ); - - - // F[dma_aw_bw_11]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_aw_bw_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_aw_bw_11_we), - .wd (perf_counter_enable_11_dma_aw_bw_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_aw_bw_11_qs) - ); - - - // F[dma_ar_done_11]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_ar_done_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_ar_done_11_we), - .wd (perf_counter_enable_11_dma_ar_done_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_ar_done_11_qs) - ); - - - // F[dma_ar_bw_11]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_ar_bw_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_ar_bw_11_we), - .wd (perf_counter_enable_11_dma_ar_bw_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_ar_bw_11_qs) - ); - - - // F[dma_r_done_11]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_r_done_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_r_done_11_we), - .wd (perf_counter_enable_11_dma_r_done_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_r_done_11_qs) - ); - - - // F[dma_r_bw_11]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_r_bw_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_r_bw_11_we), - .wd (perf_counter_enable_11_dma_r_bw_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_r_bw_11_qs) - ); - - - // F[dma_w_done_11]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_w_done_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_w_done_11_we), - .wd (perf_counter_enable_11_dma_w_done_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_w_done_11_qs) - ); - - - // F[dma_w_bw_11]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_w_bw_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_w_bw_11_we), - .wd (perf_counter_enable_11_dma_w_bw_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_w_bw_11_qs) - ); - - - // F[dma_b_done_11]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_b_done_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_b_done_11_we), - .wd (perf_counter_enable_11_dma_b_done_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_b_done_11_qs) - ); - - - // F[dma_busy_11]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_dma_busy_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_dma_busy_11_we), - .wd (perf_counter_enable_11_dma_busy_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_dma_busy_11_qs) - ); - - - // F[icache_miss_11]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_icache_miss_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_icache_miss_11_we), - .wd (perf_counter_enable_11_icache_miss_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_icache_miss_11_qs) - ); - - - // F[icache_hit_11]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_icache_hit_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_icache_hit_11_we), - .wd (perf_counter_enable_11_icache_hit_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_icache_hit_11_qs) - ); - - - // F[icache_prefetch_11]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_icache_prefetch_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_icache_prefetch_11_we), - .wd (perf_counter_enable_11_icache_prefetch_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_icache_prefetch_11_qs) - ); - - - // F[icache_double_hit_11]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_icache_double_hit_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_icache_double_hit_11_we), - .wd (perf_counter_enable_11_icache_double_hit_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_icache_double_hit_11_qs) - ); - - - // F[icache_stall_11]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_11_icache_stall_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_11_icache_stall_11_we), - .wd (perf_counter_enable_11_icache_stall_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[11].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_11_icache_stall_11_qs) - ); - - - // Subregister 12 of Multireg perf_counter_enable - // R[perf_counter_enable_12]: V(False) - - // F[cycle_12]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_cycle_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_cycle_12_we), - .wd (perf_counter_enable_12_cycle_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_cycle_12_qs) - ); - - - // F[tcdm_accessed_12]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_tcdm_accessed_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_tcdm_accessed_12_we), - .wd (perf_counter_enable_12_tcdm_accessed_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_tcdm_accessed_12_qs) - ); - - - // F[tcdm_congested_12]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_tcdm_congested_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_tcdm_congested_12_we), - .wd (perf_counter_enable_12_tcdm_congested_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_tcdm_congested_12_qs) - ); - - - // F[issue_fpu_12]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_issue_fpu_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_issue_fpu_12_we), - .wd (perf_counter_enable_12_issue_fpu_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_issue_fpu_12_qs) - ); - - - // F[issue_fpu_seq_12]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_issue_fpu_seq_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_issue_fpu_seq_12_we), - .wd (perf_counter_enable_12_issue_fpu_seq_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_issue_fpu_seq_12_qs) - ); - - - // F[issue_core_to_fpu_12]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_issue_core_to_fpu_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_issue_core_to_fpu_12_we), - .wd (perf_counter_enable_12_issue_core_to_fpu_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_issue_core_to_fpu_12_qs) - ); - - - // F[retired_instr_12]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_retired_instr_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_retired_instr_12_we), - .wd (perf_counter_enable_12_retired_instr_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_retired_instr_12_qs) - ); - - - // F[retired_load_12]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_retired_load_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_retired_load_12_we), - .wd (perf_counter_enable_12_retired_load_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_retired_load_12_qs) - ); - - - // F[retired_i_12]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_retired_i_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_retired_i_12_we), - .wd (perf_counter_enable_12_retired_i_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_retired_i_12_qs) - ); - - - // F[retired_acc_12]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_retired_acc_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_retired_acc_12_we), - .wd (perf_counter_enable_12_retired_acc_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_retired_acc_12_qs) - ); - - - // F[dma_aw_stall_12]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_aw_stall_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_aw_stall_12_we), - .wd (perf_counter_enable_12_dma_aw_stall_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_aw_stall_12_qs) - ); - - - // F[dma_ar_stall_12]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_ar_stall_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_ar_stall_12_we), - .wd (perf_counter_enable_12_dma_ar_stall_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_ar_stall_12_qs) - ); - - - // F[dma_r_stall_12]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_r_stall_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_r_stall_12_we), - .wd (perf_counter_enable_12_dma_r_stall_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_r_stall_12_qs) - ); - - - // F[dma_w_stall_12]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_w_stall_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_w_stall_12_we), - .wd (perf_counter_enable_12_dma_w_stall_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_w_stall_12_qs) - ); - - - // F[dma_buf_w_stall_12]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_buf_w_stall_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_buf_w_stall_12_we), - .wd (perf_counter_enable_12_dma_buf_w_stall_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_buf_w_stall_12_qs) - ); - - - // F[dma_buf_r_stall_12]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_buf_r_stall_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_buf_r_stall_12_we), - .wd (perf_counter_enable_12_dma_buf_r_stall_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_buf_r_stall_12_qs) - ); - - - // F[dma_aw_done_12]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_aw_done_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_aw_done_12_we), - .wd (perf_counter_enable_12_dma_aw_done_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_aw_done_12_qs) - ); - - - // F[dma_aw_bw_12]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_aw_bw_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_aw_bw_12_we), - .wd (perf_counter_enable_12_dma_aw_bw_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_aw_bw_12_qs) - ); - - - // F[dma_ar_done_12]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_ar_done_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_ar_done_12_we), - .wd (perf_counter_enable_12_dma_ar_done_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_ar_done_12_qs) - ); - - - // F[dma_ar_bw_12]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_ar_bw_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_ar_bw_12_we), - .wd (perf_counter_enable_12_dma_ar_bw_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_ar_bw_12_qs) - ); - - - // F[dma_r_done_12]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_r_done_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_r_done_12_we), - .wd (perf_counter_enable_12_dma_r_done_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_r_done_12_qs) - ); - - - // F[dma_r_bw_12]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_r_bw_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_r_bw_12_we), - .wd (perf_counter_enable_12_dma_r_bw_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_r_bw_12_qs) - ); - - - // F[dma_w_done_12]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_w_done_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_w_done_12_we), - .wd (perf_counter_enable_12_dma_w_done_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_w_done_12_qs) - ); - - - // F[dma_w_bw_12]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_w_bw_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_w_bw_12_we), - .wd (perf_counter_enable_12_dma_w_bw_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_w_bw_12_qs) - ); - - - // F[dma_b_done_12]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_b_done_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_b_done_12_we), - .wd (perf_counter_enable_12_dma_b_done_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_b_done_12_qs) - ); - - - // F[dma_busy_12]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_dma_busy_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_dma_busy_12_we), - .wd (perf_counter_enable_12_dma_busy_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_dma_busy_12_qs) - ); - - - // F[icache_miss_12]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_icache_miss_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_icache_miss_12_we), - .wd (perf_counter_enable_12_icache_miss_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_icache_miss_12_qs) - ); - - - // F[icache_hit_12]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_icache_hit_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_icache_hit_12_we), - .wd (perf_counter_enable_12_icache_hit_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_icache_hit_12_qs) - ); - - - // F[icache_prefetch_12]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_icache_prefetch_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_icache_prefetch_12_we), - .wd (perf_counter_enable_12_icache_prefetch_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_icache_prefetch_12_qs) - ); - - - // F[icache_double_hit_12]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_icache_double_hit_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_icache_double_hit_12_we), - .wd (perf_counter_enable_12_icache_double_hit_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_icache_double_hit_12_qs) - ); - - - // F[icache_stall_12]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_12_icache_stall_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_12_icache_stall_12_we), - .wd (perf_counter_enable_12_icache_stall_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[12].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_12_icache_stall_12_qs) - ); - - - // Subregister 13 of Multireg perf_counter_enable - // R[perf_counter_enable_13]: V(False) - - // F[cycle_13]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_cycle_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_cycle_13_we), - .wd (perf_counter_enable_13_cycle_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_cycle_13_qs) - ); - - - // F[tcdm_accessed_13]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_tcdm_accessed_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_tcdm_accessed_13_we), - .wd (perf_counter_enable_13_tcdm_accessed_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_tcdm_accessed_13_qs) - ); - - - // F[tcdm_congested_13]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_tcdm_congested_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_tcdm_congested_13_we), - .wd (perf_counter_enable_13_tcdm_congested_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_tcdm_congested_13_qs) - ); - - - // F[issue_fpu_13]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_issue_fpu_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_issue_fpu_13_we), - .wd (perf_counter_enable_13_issue_fpu_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_issue_fpu_13_qs) - ); - - - // F[issue_fpu_seq_13]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_issue_fpu_seq_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_issue_fpu_seq_13_we), - .wd (perf_counter_enable_13_issue_fpu_seq_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_issue_fpu_seq_13_qs) - ); - - - // F[issue_core_to_fpu_13]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_issue_core_to_fpu_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_issue_core_to_fpu_13_we), - .wd (perf_counter_enable_13_issue_core_to_fpu_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_issue_core_to_fpu_13_qs) - ); - - - // F[retired_instr_13]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_retired_instr_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_retired_instr_13_we), - .wd (perf_counter_enable_13_retired_instr_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_retired_instr_13_qs) - ); - - - // F[retired_load_13]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_retired_load_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_retired_load_13_we), - .wd (perf_counter_enable_13_retired_load_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_retired_load_13_qs) - ); - - - // F[retired_i_13]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_retired_i_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_retired_i_13_we), - .wd (perf_counter_enable_13_retired_i_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_retired_i_13_qs) - ); - - - // F[retired_acc_13]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_retired_acc_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_retired_acc_13_we), - .wd (perf_counter_enable_13_retired_acc_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_retired_acc_13_qs) - ); - - - // F[dma_aw_stall_13]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_aw_stall_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_aw_stall_13_we), - .wd (perf_counter_enable_13_dma_aw_stall_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_aw_stall_13_qs) - ); - - - // F[dma_ar_stall_13]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_ar_stall_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_ar_stall_13_we), - .wd (perf_counter_enable_13_dma_ar_stall_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_ar_stall_13_qs) - ); - - - // F[dma_r_stall_13]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_r_stall_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_r_stall_13_we), - .wd (perf_counter_enable_13_dma_r_stall_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_r_stall_13_qs) - ); - - - // F[dma_w_stall_13]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_w_stall_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_w_stall_13_we), - .wd (perf_counter_enable_13_dma_w_stall_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_w_stall_13_qs) - ); - - - // F[dma_buf_w_stall_13]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_buf_w_stall_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_buf_w_stall_13_we), - .wd (perf_counter_enable_13_dma_buf_w_stall_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_buf_w_stall_13_qs) - ); - - - // F[dma_buf_r_stall_13]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_buf_r_stall_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_buf_r_stall_13_we), - .wd (perf_counter_enable_13_dma_buf_r_stall_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_buf_r_stall_13_qs) - ); - - - // F[dma_aw_done_13]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_aw_done_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_aw_done_13_we), - .wd (perf_counter_enable_13_dma_aw_done_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_aw_done_13_qs) - ); - - - // F[dma_aw_bw_13]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_aw_bw_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_aw_bw_13_we), - .wd (perf_counter_enable_13_dma_aw_bw_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_aw_bw_13_qs) - ); - - - // F[dma_ar_done_13]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_ar_done_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_ar_done_13_we), - .wd (perf_counter_enable_13_dma_ar_done_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_ar_done_13_qs) - ); - - - // F[dma_ar_bw_13]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_ar_bw_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_ar_bw_13_we), - .wd (perf_counter_enable_13_dma_ar_bw_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_ar_bw_13_qs) - ); - - - // F[dma_r_done_13]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_r_done_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_r_done_13_we), - .wd (perf_counter_enable_13_dma_r_done_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_r_done_13_qs) - ); - - - // F[dma_r_bw_13]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_r_bw_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_r_bw_13_we), - .wd (perf_counter_enable_13_dma_r_bw_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_r_bw_13_qs) - ); - - - // F[dma_w_done_13]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_w_done_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_w_done_13_we), - .wd (perf_counter_enable_13_dma_w_done_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_w_done_13_qs) - ); - - - // F[dma_w_bw_13]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_w_bw_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_w_bw_13_we), - .wd (perf_counter_enable_13_dma_w_bw_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_w_bw_13_qs) - ); - - - // F[dma_b_done_13]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_b_done_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_b_done_13_we), - .wd (perf_counter_enable_13_dma_b_done_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_b_done_13_qs) - ); - - - // F[dma_busy_13]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_dma_busy_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_dma_busy_13_we), - .wd (perf_counter_enable_13_dma_busy_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_dma_busy_13_qs) - ); - - - // F[icache_miss_13]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_icache_miss_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_icache_miss_13_we), - .wd (perf_counter_enable_13_icache_miss_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_icache_miss_13_qs) - ); - - - // F[icache_hit_13]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_icache_hit_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_icache_hit_13_we), - .wd (perf_counter_enable_13_icache_hit_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_icache_hit_13_qs) - ); - - - // F[icache_prefetch_13]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_icache_prefetch_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_icache_prefetch_13_we), - .wd (perf_counter_enable_13_icache_prefetch_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_icache_prefetch_13_qs) - ); - - - // F[icache_double_hit_13]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_icache_double_hit_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_icache_double_hit_13_we), - .wd (perf_counter_enable_13_icache_double_hit_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_icache_double_hit_13_qs) - ); - - - // F[icache_stall_13]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_13_icache_stall_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_13_icache_stall_13_we), - .wd (perf_counter_enable_13_icache_stall_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[13].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_13_icache_stall_13_qs) - ); - - - // Subregister 14 of Multireg perf_counter_enable - // R[perf_counter_enable_14]: V(False) - - // F[cycle_14]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_cycle_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_cycle_14_we), - .wd (perf_counter_enable_14_cycle_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_cycle_14_qs) - ); - - - // F[tcdm_accessed_14]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_tcdm_accessed_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_tcdm_accessed_14_we), - .wd (perf_counter_enable_14_tcdm_accessed_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_tcdm_accessed_14_qs) - ); - - - // F[tcdm_congested_14]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_tcdm_congested_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_tcdm_congested_14_we), - .wd (perf_counter_enable_14_tcdm_congested_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_tcdm_congested_14_qs) - ); - - - // F[issue_fpu_14]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_issue_fpu_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_issue_fpu_14_we), - .wd (perf_counter_enable_14_issue_fpu_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_issue_fpu_14_qs) - ); - - - // F[issue_fpu_seq_14]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_issue_fpu_seq_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_issue_fpu_seq_14_we), - .wd (perf_counter_enable_14_issue_fpu_seq_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_issue_fpu_seq_14_qs) - ); - - - // F[issue_core_to_fpu_14]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_issue_core_to_fpu_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_issue_core_to_fpu_14_we), - .wd (perf_counter_enable_14_issue_core_to_fpu_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_issue_core_to_fpu_14_qs) - ); - - - // F[retired_instr_14]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_retired_instr_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_retired_instr_14_we), - .wd (perf_counter_enable_14_retired_instr_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_retired_instr_14_qs) - ); - - - // F[retired_load_14]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_retired_load_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_retired_load_14_we), - .wd (perf_counter_enable_14_retired_load_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_retired_load_14_qs) - ); - - - // F[retired_i_14]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_retired_i_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_retired_i_14_we), - .wd (perf_counter_enable_14_retired_i_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_retired_i_14_qs) - ); - - - // F[retired_acc_14]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_retired_acc_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_retired_acc_14_we), - .wd (perf_counter_enable_14_retired_acc_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_retired_acc_14_qs) - ); - - - // F[dma_aw_stall_14]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_aw_stall_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_aw_stall_14_we), - .wd (perf_counter_enable_14_dma_aw_stall_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_aw_stall_14_qs) - ); - - - // F[dma_ar_stall_14]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_ar_stall_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_ar_stall_14_we), - .wd (perf_counter_enable_14_dma_ar_stall_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_ar_stall_14_qs) - ); - - - // F[dma_r_stall_14]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_r_stall_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_r_stall_14_we), - .wd (perf_counter_enable_14_dma_r_stall_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_r_stall_14_qs) - ); - - - // F[dma_w_stall_14]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_w_stall_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_w_stall_14_we), - .wd (perf_counter_enable_14_dma_w_stall_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_w_stall_14_qs) - ); - - - // F[dma_buf_w_stall_14]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_buf_w_stall_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_buf_w_stall_14_we), - .wd (perf_counter_enable_14_dma_buf_w_stall_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_buf_w_stall_14_qs) - ); - - - // F[dma_buf_r_stall_14]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_buf_r_stall_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_buf_r_stall_14_we), - .wd (perf_counter_enable_14_dma_buf_r_stall_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_buf_r_stall_14_qs) - ); - - - // F[dma_aw_done_14]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_aw_done_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_aw_done_14_we), - .wd (perf_counter_enable_14_dma_aw_done_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_aw_done_14_qs) - ); - - - // F[dma_aw_bw_14]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_aw_bw_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_aw_bw_14_we), - .wd (perf_counter_enable_14_dma_aw_bw_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_aw_bw_14_qs) - ); - - - // F[dma_ar_done_14]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_ar_done_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_ar_done_14_we), - .wd (perf_counter_enable_14_dma_ar_done_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_ar_done_14_qs) - ); - - - // F[dma_ar_bw_14]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_ar_bw_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_ar_bw_14_we), - .wd (perf_counter_enable_14_dma_ar_bw_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_ar_bw_14_qs) - ); - - - // F[dma_r_done_14]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_r_done_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_r_done_14_we), - .wd (perf_counter_enable_14_dma_r_done_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_r_done_14_qs) - ); - - - // F[dma_r_bw_14]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_r_bw_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_r_bw_14_we), - .wd (perf_counter_enable_14_dma_r_bw_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_r_bw_14_qs) - ); - - - // F[dma_w_done_14]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_w_done_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_w_done_14_we), - .wd (perf_counter_enable_14_dma_w_done_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_w_done_14_qs) - ); - - - // F[dma_w_bw_14]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_w_bw_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_w_bw_14_we), - .wd (perf_counter_enable_14_dma_w_bw_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_w_bw_14_qs) - ); - - - // F[dma_b_done_14]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_b_done_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_b_done_14_we), - .wd (perf_counter_enable_14_dma_b_done_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_b_done_14_qs) - ); - - - // F[dma_busy_14]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_dma_busy_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_dma_busy_14_we), - .wd (perf_counter_enable_14_dma_busy_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_dma_busy_14_qs) - ); - - - // F[icache_miss_14]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_icache_miss_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_icache_miss_14_we), - .wd (perf_counter_enable_14_icache_miss_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_icache_miss_14_qs) - ); - - - // F[icache_hit_14]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_icache_hit_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_icache_hit_14_we), - .wd (perf_counter_enable_14_icache_hit_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_icache_hit_14_qs) - ); - - - // F[icache_prefetch_14]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_icache_prefetch_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_icache_prefetch_14_we), - .wd (perf_counter_enable_14_icache_prefetch_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_icache_prefetch_14_qs) - ); - - - // F[icache_double_hit_14]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_icache_double_hit_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_icache_double_hit_14_we), - .wd (perf_counter_enable_14_icache_double_hit_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_icache_double_hit_14_qs) - ); - - - // F[icache_stall_14]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_14_icache_stall_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_14_icache_stall_14_we), - .wd (perf_counter_enable_14_icache_stall_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[14].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_14_icache_stall_14_qs) - ); - - - // Subregister 15 of Multireg perf_counter_enable - // R[perf_counter_enable_15]: V(False) - - // F[cycle_15]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_cycle_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_cycle_15_we), - .wd (perf_counter_enable_15_cycle_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].cycle.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_cycle_15_qs) - ); - - - // F[tcdm_accessed_15]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_tcdm_accessed_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_tcdm_accessed_15_we), - .wd (perf_counter_enable_15_tcdm_accessed_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].tcdm_accessed.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_tcdm_accessed_15_qs) - ); - - - // F[tcdm_congested_15]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_tcdm_congested_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_tcdm_congested_15_we), - .wd (perf_counter_enable_15_tcdm_congested_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].tcdm_congested.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_tcdm_congested_15_qs) - ); - - - // F[issue_fpu_15]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_issue_fpu_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_issue_fpu_15_we), - .wd (perf_counter_enable_15_issue_fpu_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].issue_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_issue_fpu_15_qs) - ); - - - // F[issue_fpu_seq_15]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_issue_fpu_seq_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_issue_fpu_seq_15_we), - .wd (perf_counter_enable_15_issue_fpu_seq_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].issue_fpu_seq.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_issue_fpu_seq_15_qs) - ); - - - // F[issue_core_to_fpu_15]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_issue_core_to_fpu_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_issue_core_to_fpu_15_we), - .wd (perf_counter_enable_15_issue_core_to_fpu_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].issue_core_to_fpu.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_issue_core_to_fpu_15_qs) - ); - - - // F[retired_instr_15]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_retired_instr_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_retired_instr_15_we), - .wd (perf_counter_enable_15_retired_instr_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].retired_instr.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_retired_instr_15_qs) - ); - - - // F[retired_load_15]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_retired_load_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_retired_load_15_we), - .wd (perf_counter_enable_15_retired_load_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].retired_load.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_retired_load_15_qs) - ); - - - // F[retired_i_15]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_retired_i_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_retired_i_15_we), - .wd (perf_counter_enable_15_retired_i_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].retired_i.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_retired_i_15_qs) - ); - - - // F[retired_acc_15]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_retired_acc_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_retired_acc_15_we), - .wd (perf_counter_enable_15_retired_acc_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].retired_acc.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_retired_acc_15_qs) - ); - - - // F[dma_aw_stall_15]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_aw_stall_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_aw_stall_15_we), - .wd (perf_counter_enable_15_dma_aw_stall_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_aw_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_aw_stall_15_qs) - ); - - - // F[dma_ar_stall_15]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_ar_stall_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_ar_stall_15_we), - .wd (perf_counter_enable_15_dma_ar_stall_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_ar_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_ar_stall_15_qs) - ); - - - // F[dma_r_stall_15]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_r_stall_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_r_stall_15_we), - .wd (perf_counter_enable_15_dma_r_stall_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_r_stall_15_qs) - ); - - - // F[dma_w_stall_15]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_w_stall_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_w_stall_15_we), - .wd (perf_counter_enable_15_dma_w_stall_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_w_stall_15_qs) - ); - - - // F[dma_buf_w_stall_15]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_buf_w_stall_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_buf_w_stall_15_we), - .wd (perf_counter_enable_15_dma_buf_w_stall_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_buf_w_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_buf_w_stall_15_qs) - ); - - - // F[dma_buf_r_stall_15]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_buf_r_stall_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_buf_r_stall_15_we), - .wd (perf_counter_enable_15_dma_buf_r_stall_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_buf_r_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_buf_r_stall_15_qs) - ); - - - // F[dma_aw_done_15]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_aw_done_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_aw_done_15_we), - .wd (perf_counter_enable_15_dma_aw_done_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_aw_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_aw_done_15_qs) - ); - - - // F[dma_aw_bw_15]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_aw_bw_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_aw_bw_15_we), - .wd (perf_counter_enable_15_dma_aw_bw_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_aw_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_aw_bw_15_qs) - ); - - - // F[dma_ar_done_15]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_ar_done_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_ar_done_15_we), - .wd (perf_counter_enable_15_dma_ar_done_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_ar_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_ar_done_15_qs) - ); - - - // F[dma_ar_bw_15]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_ar_bw_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_ar_bw_15_we), - .wd (perf_counter_enable_15_dma_ar_bw_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_ar_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_ar_bw_15_qs) - ); - - - // F[dma_r_done_15]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_r_done_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_r_done_15_we), - .wd (perf_counter_enable_15_dma_r_done_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_r_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_r_done_15_qs) - ); - - - // F[dma_r_bw_15]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_r_bw_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_r_bw_15_we), - .wd (perf_counter_enable_15_dma_r_bw_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_r_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_r_bw_15_qs) - ); - - - // F[dma_w_done_15]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_w_done_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_w_done_15_we), - .wd (perf_counter_enable_15_dma_w_done_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_w_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_w_done_15_qs) - ); - - - // F[dma_w_bw_15]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_w_bw_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_w_bw_15_we), - .wd (perf_counter_enable_15_dma_w_bw_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_w_bw.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_w_bw_15_qs) - ); - - - // F[dma_b_done_15]: 24:24 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_b_done_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_b_done_15_we), - .wd (perf_counter_enable_15_dma_b_done_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_b_done.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_b_done_15_qs) - ); - - - // F[dma_busy_15]: 25:25 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_dma_busy_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_dma_busy_15_we), - .wd (perf_counter_enable_15_dma_busy_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].dma_busy.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_dma_busy_15_qs) - ); - - - // F[icache_miss_15]: 26:26 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_icache_miss_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_icache_miss_15_we), - .wd (perf_counter_enable_15_icache_miss_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].icache_miss.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_icache_miss_15_qs) - ); - - - // F[icache_hit_15]: 27:27 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_icache_hit_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_icache_hit_15_we), - .wd (perf_counter_enable_15_icache_hit_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].icache_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_icache_hit_15_qs) - ); - - - // F[icache_prefetch_15]: 28:28 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_icache_prefetch_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_icache_prefetch_15_we), - .wd (perf_counter_enable_15_icache_prefetch_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].icache_prefetch.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_icache_prefetch_15_qs) - ); - - - // F[icache_double_hit_15]: 29:29 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_icache_double_hit_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_icache_double_hit_15_we), - .wd (perf_counter_enable_15_icache_double_hit_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].icache_double_hit.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_icache_double_hit_15_qs) - ); - - - // F[icache_stall_15]: 30:30 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_perf_counter_enable_15_icache_stall_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (perf_counter_enable_15_icache_stall_15_we), - .wd (perf_counter_enable_15_icache_stall_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.perf_counter_enable[15].icache_stall.q ), - - // to register interface (read) - .qs (perf_counter_enable_15_icache_stall_15_qs) - ); - - - - - // Subregister 0 of Multireg hart_select - // R[hart_select_0]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_0_we), - .wd (hart_select_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[0].q ), - - // to register interface (read) - .qs (hart_select_0_qs) - ); - - // Subregister 1 of Multireg hart_select - // R[hart_select_1]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_1_we), - .wd (hart_select_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[1].q ), - - // to register interface (read) - .qs (hart_select_1_qs) - ); - - // Subregister 2 of Multireg hart_select - // R[hart_select_2]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_2_we), - .wd (hart_select_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[2].q ), - - // to register interface (read) - .qs (hart_select_2_qs) - ); - - // Subregister 3 of Multireg hart_select - // R[hart_select_3]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_3_we), - .wd (hart_select_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[3].q ), - - // to register interface (read) - .qs (hart_select_3_qs) - ); - - // Subregister 4 of Multireg hart_select - // R[hart_select_4]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_4_we), - .wd (hart_select_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[4].q ), - - // to register interface (read) - .qs (hart_select_4_qs) - ); - - // Subregister 5 of Multireg hart_select - // R[hart_select_5]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_5_we), - .wd (hart_select_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[5].q ), - - // to register interface (read) - .qs (hart_select_5_qs) - ); - - // Subregister 6 of Multireg hart_select - // R[hart_select_6]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_6_we), - .wd (hart_select_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[6].q ), - - // to register interface (read) - .qs (hart_select_6_qs) - ); - - // Subregister 7 of Multireg hart_select - // R[hart_select_7]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_7_we), - .wd (hart_select_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[7].q ), - - // to register interface (read) - .qs (hart_select_7_qs) - ); - - // Subregister 8 of Multireg hart_select - // R[hart_select_8]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_8_we), - .wd (hart_select_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[8].q ), - - // to register interface (read) - .qs (hart_select_8_qs) - ); - - // Subregister 9 of Multireg hart_select - // R[hart_select_9]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_9_we), - .wd (hart_select_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[9].q ), - - // to register interface (read) - .qs (hart_select_9_qs) - ); - - // Subregister 10 of Multireg hart_select - // R[hart_select_10]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_10_we), - .wd (hart_select_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[10].q ), - - // to register interface (read) - .qs (hart_select_10_qs) - ); - - // Subregister 11 of Multireg hart_select - // R[hart_select_11]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_11_we), - .wd (hart_select_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[11].q ), - - // to register interface (read) - .qs (hart_select_11_qs) - ); - - // Subregister 12 of Multireg hart_select - // R[hart_select_12]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_12_we), - .wd (hart_select_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[12].q ), - - // to register interface (read) - .qs (hart_select_12_qs) - ); - - // Subregister 13 of Multireg hart_select - // R[hart_select_13]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_13_we), - .wd (hart_select_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[13].q ), - - // to register interface (read) - .qs (hart_select_13_qs) - ); - - // Subregister 14 of Multireg hart_select - // R[hart_select_14]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_14_we), - .wd (hart_select_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[14].q ), - - // to register interface (read) - .qs (hart_select_14_qs) - ); - - // Subregister 15 of Multireg hart_select - // R[hart_select_15]: V(False) - - prim_subreg #( - .DW (10), - .SWACCESS("RW"), - .RESVAL (10'h0) - ) u_hart_select_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (hart_select_15_we), - .wd (hart_select_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.hart_select[15].q ), - - // to register interface (read) - .qs (hart_select_15_qs) - ); - - - - // Subregister 0 of Multireg perf_counter - // R[perf_counter_0]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_0 ( - .re (perf_counter_0_re), - .we (perf_counter_0_we), - .wd (perf_counter_0_wd), - .d (hw2reg.perf_counter[0].d), - .qre (), - .qe (reg2hw.perf_counter[0].qe), - .q (reg2hw.perf_counter[0].q ), - .qs (perf_counter_0_qs) - ); - - // Subregister 1 of Multireg perf_counter - // R[perf_counter_1]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_1 ( - .re (perf_counter_1_re), - .we (perf_counter_1_we), - .wd (perf_counter_1_wd), - .d (hw2reg.perf_counter[1].d), - .qre (), - .qe (reg2hw.perf_counter[1].qe), - .q (reg2hw.perf_counter[1].q ), - .qs (perf_counter_1_qs) - ); - - // Subregister 2 of Multireg perf_counter - // R[perf_counter_2]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_2 ( - .re (perf_counter_2_re), - .we (perf_counter_2_we), - .wd (perf_counter_2_wd), - .d (hw2reg.perf_counter[2].d), - .qre (), - .qe (reg2hw.perf_counter[2].qe), - .q (reg2hw.perf_counter[2].q ), - .qs (perf_counter_2_qs) - ); - - // Subregister 3 of Multireg perf_counter - // R[perf_counter_3]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_3 ( - .re (perf_counter_3_re), - .we (perf_counter_3_we), - .wd (perf_counter_3_wd), - .d (hw2reg.perf_counter[3].d), - .qre (), - .qe (reg2hw.perf_counter[3].qe), - .q (reg2hw.perf_counter[3].q ), - .qs (perf_counter_3_qs) - ); - - // Subregister 4 of Multireg perf_counter - // R[perf_counter_4]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_4 ( - .re (perf_counter_4_re), - .we (perf_counter_4_we), - .wd (perf_counter_4_wd), - .d (hw2reg.perf_counter[4].d), - .qre (), - .qe (reg2hw.perf_counter[4].qe), - .q (reg2hw.perf_counter[4].q ), - .qs (perf_counter_4_qs) - ); - - // Subregister 5 of Multireg perf_counter - // R[perf_counter_5]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_5 ( - .re (perf_counter_5_re), - .we (perf_counter_5_we), - .wd (perf_counter_5_wd), - .d (hw2reg.perf_counter[5].d), - .qre (), - .qe (reg2hw.perf_counter[5].qe), - .q (reg2hw.perf_counter[5].q ), - .qs (perf_counter_5_qs) - ); - - // Subregister 6 of Multireg perf_counter - // R[perf_counter_6]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_6 ( - .re (perf_counter_6_re), - .we (perf_counter_6_we), - .wd (perf_counter_6_wd), - .d (hw2reg.perf_counter[6].d), - .qre (), - .qe (reg2hw.perf_counter[6].qe), - .q (reg2hw.perf_counter[6].q ), - .qs (perf_counter_6_qs) - ); - - // Subregister 7 of Multireg perf_counter - // R[perf_counter_7]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_7 ( - .re (perf_counter_7_re), - .we (perf_counter_7_we), - .wd (perf_counter_7_wd), - .d (hw2reg.perf_counter[7].d), - .qre (), - .qe (reg2hw.perf_counter[7].qe), - .q (reg2hw.perf_counter[7].q ), - .qs (perf_counter_7_qs) - ); - - // Subregister 8 of Multireg perf_counter - // R[perf_counter_8]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_8 ( - .re (perf_counter_8_re), - .we (perf_counter_8_we), - .wd (perf_counter_8_wd), - .d (hw2reg.perf_counter[8].d), - .qre (), - .qe (reg2hw.perf_counter[8].qe), - .q (reg2hw.perf_counter[8].q ), - .qs (perf_counter_8_qs) - ); - - // Subregister 9 of Multireg perf_counter - // R[perf_counter_9]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_9 ( - .re (perf_counter_9_re), - .we (perf_counter_9_we), - .wd (perf_counter_9_wd), - .d (hw2reg.perf_counter[9].d), - .qre (), - .qe (reg2hw.perf_counter[9].qe), - .q (reg2hw.perf_counter[9].q ), - .qs (perf_counter_9_qs) - ); - - // Subregister 10 of Multireg perf_counter - // R[perf_counter_10]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_10 ( - .re (perf_counter_10_re), - .we (perf_counter_10_we), - .wd (perf_counter_10_wd), - .d (hw2reg.perf_counter[10].d), - .qre (), - .qe (reg2hw.perf_counter[10].qe), - .q (reg2hw.perf_counter[10].q ), - .qs (perf_counter_10_qs) - ); - - // Subregister 11 of Multireg perf_counter - // R[perf_counter_11]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_11 ( - .re (perf_counter_11_re), - .we (perf_counter_11_we), - .wd (perf_counter_11_wd), - .d (hw2reg.perf_counter[11].d), - .qre (), - .qe (reg2hw.perf_counter[11].qe), - .q (reg2hw.perf_counter[11].q ), - .qs (perf_counter_11_qs) - ); - - // Subregister 12 of Multireg perf_counter - // R[perf_counter_12]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_12 ( - .re (perf_counter_12_re), - .we (perf_counter_12_we), - .wd (perf_counter_12_wd), - .d (hw2reg.perf_counter[12].d), - .qre (), - .qe (reg2hw.perf_counter[12].qe), - .q (reg2hw.perf_counter[12].q ), - .qs (perf_counter_12_qs) - ); - - // Subregister 13 of Multireg perf_counter - // R[perf_counter_13]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_13 ( - .re (perf_counter_13_re), - .we (perf_counter_13_we), - .wd (perf_counter_13_wd), - .d (hw2reg.perf_counter[13].d), - .qre (), - .qe (reg2hw.perf_counter[13].qe), - .q (reg2hw.perf_counter[13].q ), - .qs (perf_counter_13_qs) - ); - - // Subregister 14 of Multireg perf_counter - // R[perf_counter_14]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_14 ( - .re (perf_counter_14_re), - .we (perf_counter_14_we), - .wd (perf_counter_14_wd), - .d (hw2reg.perf_counter[14].d), - .qre (), - .qe (reg2hw.perf_counter[14].qe), - .q (reg2hw.perf_counter[14].q ), - .qs (perf_counter_14_qs) - ); - - // Subregister 15 of Multireg perf_counter - // R[perf_counter_15]: V(True) - - prim_subreg_ext #( - .DW (48) - ) u_perf_counter_15 ( - .re (perf_counter_15_re), - .we (perf_counter_15_we), - .wd (perf_counter_15_wd), - .d (hw2reg.perf_counter[15].d), - .qre (), - .qe (reg2hw.perf_counter[15].qe), - .q (reg2hw.perf_counter[15].q ), - .qs (perf_counter_15_qs) - ); - - - // R[cl_clint_set]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_cl_clint_set ( - .re (1'b0), - .we (cl_clint_set_we), - .wd (cl_clint_set_wd), - .d ('0), - .qre (), - .qe (reg2hw.cl_clint_set.qe), - .q (reg2hw.cl_clint_set.q ), - .qs () - ); - - - // R[cl_clint_clear]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_cl_clint_clear ( - .re (1'b0), - .we (cl_clint_clear_we), - .wd (cl_clint_clear_wd), - .d ('0), - .qre (), - .qe (reg2hw.cl_clint_clear.qe), - .q (reg2hw.cl_clint_clear.q ), - .qs () - ); - - - // R[hw_barrier]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_hw_barrier ( - .re (hw_barrier_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.hw_barrier.d), - .qre (), - .qe (), - .q (reg2hw.hw_barrier.q ), - .qs (hw_barrier_qs) - ); - - - // R[icache_prefetch_enable]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("WO"), - .RESVAL (1'h1) - ) u_icache_prefetch_enable ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (icache_prefetch_enable_we), - .wd (icache_prefetch_enable_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.icache_prefetch_enable.q ), - - .qs () - ); - - - - - logic [51:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_OFFSET); - addr_hit[ 1] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_OFFSET); - addr_hit[ 2] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_OFFSET); - addr_hit[ 3] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_OFFSET); - addr_hit[ 4] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_OFFSET); - addr_hit[ 5] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_OFFSET); - addr_hit[ 6] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_OFFSET); - addr_hit[ 7] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_OFFSET); - addr_hit[ 8] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_OFFSET); - addr_hit[ 9] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_OFFSET); - addr_hit[10] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_OFFSET); - addr_hit[11] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_OFFSET); - addr_hit[12] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_OFFSET); - addr_hit[13] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_OFFSET); - addr_hit[14] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_OFFSET); - addr_hit[15] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_OFFSET); - addr_hit[16] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0_OFFSET); - addr_hit[17] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1_OFFSET); - addr_hit[18] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2_OFFSET); - addr_hit[19] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3_OFFSET); - addr_hit[20] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4_OFFSET); - addr_hit[21] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5_OFFSET); - addr_hit[22] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6_OFFSET); - addr_hit[23] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7_OFFSET); - addr_hit[24] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8_OFFSET); - addr_hit[25] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9_OFFSET); - addr_hit[26] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10_OFFSET); - addr_hit[27] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11_OFFSET); - addr_hit[28] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12_OFFSET); - addr_hit[29] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13_OFFSET); - addr_hit[30] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14_OFFSET); - addr_hit[31] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15_OFFSET); - addr_hit[32] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_OFFSET); - addr_hit[33] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_OFFSET); - addr_hit[34] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_OFFSET); - addr_hit[35] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_OFFSET); - addr_hit[36] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_OFFSET); - addr_hit[37] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_OFFSET); - addr_hit[38] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_OFFSET); - addr_hit[39] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_OFFSET); - addr_hit[40] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_OFFSET); - addr_hit[41] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_OFFSET); - addr_hit[42] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_OFFSET); - addr_hit[43] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_OFFSET); - addr_hit[44] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_OFFSET); - addr_hit[45] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_OFFSET); - addr_hit[46] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_OFFSET); - addr_hit[47] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_OFFSET); - addr_hit[48] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET); - addr_hit[49] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET); - addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET); - addr_hit[51] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[17] & ~reg_be))) | - (addr_hit[18] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[18] & ~reg_be))) | - (addr_hit[19] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[19] & ~reg_be))) | - (addr_hit[20] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[20] & ~reg_be))) | - (addr_hit[21] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[21] & ~reg_be))) | - (addr_hit[22] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[22] & ~reg_be))) | - (addr_hit[23] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[23] & ~reg_be))) | - (addr_hit[24] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[24] & ~reg_be))) | - (addr_hit[25] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[25] & ~reg_be))) | - (addr_hit[26] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[26] & ~reg_be))) | - (addr_hit[27] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[27] & ~reg_be))) | - (addr_hit[28] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[28] & ~reg_be))) | - (addr_hit[29] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[29] & ~reg_be))) | - (addr_hit[30] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[30] & ~reg_be))) | - (addr_hit[31] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[31] & ~reg_be))) | - (addr_hit[32] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[32] & ~reg_be))) | - (addr_hit[33] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[33] & ~reg_be))) | - (addr_hit[34] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[34] & ~reg_be))) | - (addr_hit[35] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[35] & ~reg_be))) | - (addr_hit[36] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[36] & ~reg_be))) | - (addr_hit[37] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[37] & ~reg_be))) | - (addr_hit[38] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[38] & ~reg_be))) | - (addr_hit[39] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[39] & ~reg_be))) | - (addr_hit[40] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[40] & ~reg_be))) | - (addr_hit[41] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[41] & ~reg_be))) | - (addr_hit[42] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[42] & ~reg_be))) | - (addr_hit[43] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[43] & ~reg_be))) | - (addr_hit[44] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[44] & ~reg_be))) | - (addr_hit[45] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[45] & ~reg_be))) | - (addr_hit[46] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[46] & ~reg_be))) | - (addr_hit[47] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[47] & ~reg_be))) | - (addr_hit[48] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[48] & ~reg_be))) | - (addr_hit[49] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[49] & ~reg_be))) | - (addr_hit[50] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[50] & ~reg_be))) | - (addr_hit[51] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[51] & ~reg_be))))); - end - - assign perf_counter_enable_0_cycle_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_cycle_0_wd = reg_wdata[0]; - - assign perf_counter_enable_0_tcdm_accessed_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_tcdm_accessed_0_wd = reg_wdata[1]; - - assign perf_counter_enable_0_tcdm_congested_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_tcdm_congested_0_wd = reg_wdata[2]; - - assign perf_counter_enable_0_issue_fpu_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_issue_fpu_0_wd = reg_wdata[3]; - - assign perf_counter_enable_0_issue_fpu_seq_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_issue_fpu_seq_0_wd = reg_wdata[4]; - - assign perf_counter_enable_0_issue_core_to_fpu_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_issue_core_to_fpu_0_wd = reg_wdata[5]; - - assign perf_counter_enable_0_retired_instr_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_retired_instr_0_wd = reg_wdata[6]; - - assign perf_counter_enable_0_retired_load_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_retired_load_0_wd = reg_wdata[7]; - - assign perf_counter_enable_0_retired_i_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_retired_i_0_wd = reg_wdata[8]; - - assign perf_counter_enable_0_retired_acc_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_retired_acc_0_wd = reg_wdata[9]; - - assign perf_counter_enable_0_dma_aw_stall_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_aw_stall_0_wd = reg_wdata[10]; - - assign perf_counter_enable_0_dma_ar_stall_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_ar_stall_0_wd = reg_wdata[11]; - - assign perf_counter_enable_0_dma_r_stall_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_r_stall_0_wd = reg_wdata[12]; - - assign perf_counter_enable_0_dma_w_stall_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_w_stall_0_wd = reg_wdata[13]; - - assign perf_counter_enable_0_dma_buf_w_stall_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_buf_w_stall_0_wd = reg_wdata[14]; - - assign perf_counter_enable_0_dma_buf_r_stall_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_buf_r_stall_0_wd = reg_wdata[15]; - - assign perf_counter_enable_0_dma_aw_done_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_aw_done_0_wd = reg_wdata[16]; - - assign perf_counter_enable_0_dma_aw_bw_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_aw_bw_0_wd = reg_wdata[17]; - - assign perf_counter_enable_0_dma_ar_done_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_ar_done_0_wd = reg_wdata[18]; - - assign perf_counter_enable_0_dma_ar_bw_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_ar_bw_0_wd = reg_wdata[19]; - - assign perf_counter_enable_0_dma_r_done_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_r_done_0_wd = reg_wdata[20]; - - assign perf_counter_enable_0_dma_r_bw_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_r_bw_0_wd = reg_wdata[21]; - - assign perf_counter_enable_0_dma_w_done_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_w_done_0_wd = reg_wdata[22]; - - assign perf_counter_enable_0_dma_w_bw_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_w_bw_0_wd = reg_wdata[23]; - - assign perf_counter_enable_0_dma_b_done_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_b_done_0_wd = reg_wdata[24]; - - assign perf_counter_enable_0_dma_busy_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_dma_busy_0_wd = reg_wdata[25]; - - assign perf_counter_enable_0_icache_miss_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_icache_miss_0_wd = reg_wdata[26]; - - assign perf_counter_enable_0_icache_hit_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_icache_hit_0_wd = reg_wdata[27]; - - assign perf_counter_enable_0_icache_prefetch_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_icache_prefetch_0_wd = reg_wdata[28]; - - assign perf_counter_enable_0_icache_double_hit_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_icache_double_hit_0_wd = reg_wdata[29]; - - assign perf_counter_enable_0_icache_stall_0_we = addr_hit[0] & reg_we & !reg_error; - assign perf_counter_enable_0_icache_stall_0_wd = reg_wdata[30]; - - assign perf_counter_enable_1_cycle_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_cycle_1_wd = reg_wdata[0]; - - assign perf_counter_enable_1_tcdm_accessed_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_tcdm_accessed_1_wd = reg_wdata[1]; - - assign perf_counter_enable_1_tcdm_congested_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_tcdm_congested_1_wd = reg_wdata[2]; - - assign perf_counter_enable_1_issue_fpu_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_issue_fpu_1_wd = reg_wdata[3]; - - assign perf_counter_enable_1_issue_fpu_seq_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_issue_fpu_seq_1_wd = reg_wdata[4]; - - assign perf_counter_enable_1_issue_core_to_fpu_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_issue_core_to_fpu_1_wd = reg_wdata[5]; - - assign perf_counter_enable_1_retired_instr_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_retired_instr_1_wd = reg_wdata[6]; - - assign perf_counter_enable_1_retired_load_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_retired_load_1_wd = reg_wdata[7]; - - assign perf_counter_enable_1_retired_i_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_retired_i_1_wd = reg_wdata[8]; - - assign perf_counter_enable_1_retired_acc_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_retired_acc_1_wd = reg_wdata[9]; - - assign perf_counter_enable_1_dma_aw_stall_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_aw_stall_1_wd = reg_wdata[10]; - - assign perf_counter_enable_1_dma_ar_stall_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_ar_stall_1_wd = reg_wdata[11]; - - assign perf_counter_enable_1_dma_r_stall_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_r_stall_1_wd = reg_wdata[12]; - - assign perf_counter_enable_1_dma_w_stall_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_w_stall_1_wd = reg_wdata[13]; - - assign perf_counter_enable_1_dma_buf_w_stall_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_buf_w_stall_1_wd = reg_wdata[14]; - - assign perf_counter_enable_1_dma_buf_r_stall_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_buf_r_stall_1_wd = reg_wdata[15]; - - assign perf_counter_enable_1_dma_aw_done_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_aw_done_1_wd = reg_wdata[16]; - - assign perf_counter_enable_1_dma_aw_bw_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_aw_bw_1_wd = reg_wdata[17]; - - assign perf_counter_enable_1_dma_ar_done_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_ar_done_1_wd = reg_wdata[18]; - - assign perf_counter_enable_1_dma_ar_bw_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_ar_bw_1_wd = reg_wdata[19]; - - assign perf_counter_enable_1_dma_r_done_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_r_done_1_wd = reg_wdata[20]; - - assign perf_counter_enable_1_dma_r_bw_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_r_bw_1_wd = reg_wdata[21]; - - assign perf_counter_enable_1_dma_w_done_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_w_done_1_wd = reg_wdata[22]; - - assign perf_counter_enable_1_dma_w_bw_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_w_bw_1_wd = reg_wdata[23]; - - assign perf_counter_enable_1_dma_b_done_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_b_done_1_wd = reg_wdata[24]; - - assign perf_counter_enable_1_dma_busy_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_dma_busy_1_wd = reg_wdata[25]; - - assign perf_counter_enable_1_icache_miss_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_icache_miss_1_wd = reg_wdata[26]; - - assign perf_counter_enable_1_icache_hit_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_icache_hit_1_wd = reg_wdata[27]; - - assign perf_counter_enable_1_icache_prefetch_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_icache_prefetch_1_wd = reg_wdata[28]; - - assign perf_counter_enable_1_icache_double_hit_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_icache_double_hit_1_wd = reg_wdata[29]; - - assign perf_counter_enable_1_icache_stall_1_we = addr_hit[1] & reg_we & !reg_error; - assign perf_counter_enable_1_icache_stall_1_wd = reg_wdata[30]; - - assign perf_counter_enable_2_cycle_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_cycle_2_wd = reg_wdata[0]; - - assign perf_counter_enable_2_tcdm_accessed_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_tcdm_accessed_2_wd = reg_wdata[1]; - - assign perf_counter_enable_2_tcdm_congested_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_tcdm_congested_2_wd = reg_wdata[2]; - - assign perf_counter_enable_2_issue_fpu_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_issue_fpu_2_wd = reg_wdata[3]; - - assign perf_counter_enable_2_issue_fpu_seq_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_issue_fpu_seq_2_wd = reg_wdata[4]; - - assign perf_counter_enable_2_issue_core_to_fpu_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_issue_core_to_fpu_2_wd = reg_wdata[5]; - - assign perf_counter_enable_2_retired_instr_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_retired_instr_2_wd = reg_wdata[6]; - - assign perf_counter_enable_2_retired_load_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_retired_load_2_wd = reg_wdata[7]; - - assign perf_counter_enable_2_retired_i_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_retired_i_2_wd = reg_wdata[8]; - - assign perf_counter_enable_2_retired_acc_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_retired_acc_2_wd = reg_wdata[9]; - - assign perf_counter_enable_2_dma_aw_stall_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_aw_stall_2_wd = reg_wdata[10]; - - assign perf_counter_enable_2_dma_ar_stall_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_ar_stall_2_wd = reg_wdata[11]; - - assign perf_counter_enable_2_dma_r_stall_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_r_stall_2_wd = reg_wdata[12]; - - assign perf_counter_enable_2_dma_w_stall_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_w_stall_2_wd = reg_wdata[13]; - - assign perf_counter_enable_2_dma_buf_w_stall_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_buf_w_stall_2_wd = reg_wdata[14]; - - assign perf_counter_enable_2_dma_buf_r_stall_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_buf_r_stall_2_wd = reg_wdata[15]; - - assign perf_counter_enable_2_dma_aw_done_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_aw_done_2_wd = reg_wdata[16]; - - assign perf_counter_enable_2_dma_aw_bw_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_aw_bw_2_wd = reg_wdata[17]; - - assign perf_counter_enable_2_dma_ar_done_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_ar_done_2_wd = reg_wdata[18]; - - assign perf_counter_enable_2_dma_ar_bw_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_ar_bw_2_wd = reg_wdata[19]; - - assign perf_counter_enable_2_dma_r_done_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_r_done_2_wd = reg_wdata[20]; - - assign perf_counter_enable_2_dma_r_bw_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_r_bw_2_wd = reg_wdata[21]; - - assign perf_counter_enable_2_dma_w_done_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_w_done_2_wd = reg_wdata[22]; - - assign perf_counter_enable_2_dma_w_bw_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_w_bw_2_wd = reg_wdata[23]; - - assign perf_counter_enable_2_dma_b_done_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_b_done_2_wd = reg_wdata[24]; - - assign perf_counter_enable_2_dma_busy_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_dma_busy_2_wd = reg_wdata[25]; - - assign perf_counter_enable_2_icache_miss_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_icache_miss_2_wd = reg_wdata[26]; - - assign perf_counter_enable_2_icache_hit_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_icache_hit_2_wd = reg_wdata[27]; - - assign perf_counter_enable_2_icache_prefetch_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_icache_prefetch_2_wd = reg_wdata[28]; - - assign perf_counter_enable_2_icache_double_hit_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_icache_double_hit_2_wd = reg_wdata[29]; - - assign perf_counter_enable_2_icache_stall_2_we = addr_hit[2] & reg_we & !reg_error; - assign perf_counter_enable_2_icache_stall_2_wd = reg_wdata[30]; - - assign perf_counter_enable_3_cycle_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_cycle_3_wd = reg_wdata[0]; - - assign perf_counter_enable_3_tcdm_accessed_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_tcdm_accessed_3_wd = reg_wdata[1]; - - assign perf_counter_enable_3_tcdm_congested_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_tcdm_congested_3_wd = reg_wdata[2]; - - assign perf_counter_enable_3_issue_fpu_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_issue_fpu_3_wd = reg_wdata[3]; - - assign perf_counter_enable_3_issue_fpu_seq_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_issue_fpu_seq_3_wd = reg_wdata[4]; - - assign perf_counter_enable_3_issue_core_to_fpu_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_issue_core_to_fpu_3_wd = reg_wdata[5]; - - assign perf_counter_enable_3_retired_instr_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_retired_instr_3_wd = reg_wdata[6]; - - assign perf_counter_enable_3_retired_load_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_retired_load_3_wd = reg_wdata[7]; - - assign perf_counter_enable_3_retired_i_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_retired_i_3_wd = reg_wdata[8]; - - assign perf_counter_enable_3_retired_acc_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_retired_acc_3_wd = reg_wdata[9]; - - assign perf_counter_enable_3_dma_aw_stall_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_aw_stall_3_wd = reg_wdata[10]; - - assign perf_counter_enable_3_dma_ar_stall_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_ar_stall_3_wd = reg_wdata[11]; - - assign perf_counter_enable_3_dma_r_stall_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_r_stall_3_wd = reg_wdata[12]; - - assign perf_counter_enable_3_dma_w_stall_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_w_stall_3_wd = reg_wdata[13]; - - assign perf_counter_enable_3_dma_buf_w_stall_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_buf_w_stall_3_wd = reg_wdata[14]; - - assign perf_counter_enable_3_dma_buf_r_stall_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_buf_r_stall_3_wd = reg_wdata[15]; - - assign perf_counter_enable_3_dma_aw_done_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_aw_done_3_wd = reg_wdata[16]; - - assign perf_counter_enable_3_dma_aw_bw_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_aw_bw_3_wd = reg_wdata[17]; - - assign perf_counter_enable_3_dma_ar_done_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_ar_done_3_wd = reg_wdata[18]; - - assign perf_counter_enable_3_dma_ar_bw_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_ar_bw_3_wd = reg_wdata[19]; - - assign perf_counter_enable_3_dma_r_done_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_r_done_3_wd = reg_wdata[20]; - - assign perf_counter_enable_3_dma_r_bw_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_r_bw_3_wd = reg_wdata[21]; - - assign perf_counter_enable_3_dma_w_done_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_w_done_3_wd = reg_wdata[22]; - - assign perf_counter_enable_3_dma_w_bw_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_w_bw_3_wd = reg_wdata[23]; - - assign perf_counter_enable_3_dma_b_done_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_b_done_3_wd = reg_wdata[24]; - - assign perf_counter_enable_3_dma_busy_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_dma_busy_3_wd = reg_wdata[25]; - - assign perf_counter_enable_3_icache_miss_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_icache_miss_3_wd = reg_wdata[26]; - - assign perf_counter_enable_3_icache_hit_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_icache_hit_3_wd = reg_wdata[27]; - - assign perf_counter_enable_3_icache_prefetch_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_icache_prefetch_3_wd = reg_wdata[28]; - - assign perf_counter_enable_3_icache_double_hit_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_icache_double_hit_3_wd = reg_wdata[29]; - - assign perf_counter_enable_3_icache_stall_3_we = addr_hit[3] & reg_we & !reg_error; - assign perf_counter_enable_3_icache_stall_3_wd = reg_wdata[30]; - - assign perf_counter_enable_4_cycle_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_cycle_4_wd = reg_wdata[0]; - - assign perf_counter_enable_4_tcdm_accessed_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_tcdm_accessed_4_wd = reg_wdata[1]; - - assign perf_counter_enable_4_tcdm_congested_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_tcdm_congested_4_wd = reg_wdata[2]; - - assign perf_counter_enable_4_issue_fpu_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_issue_fpu_4_wd = reg_wdata[3]; - - assign perf_counter_enable_4_issue_fpu_seq_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_issue_fpu_seq_4_wd = reg_wdata[4]; - - assign perf_counter_enable_4_issue_core_to_fpu_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_issue_core_to_fpu_4_wd = reg_wdata[5]; - - assign perf_counter_enable_4_retired_instr_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_retired_instr_4_wd = reg_wdata[6]; - - assign perf_counter_enable_4_retired_load_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_retired_load_4_wd = reg_wdata[7]; - - assign perf_counter_enable_4_retired_i_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_retired_i_4_wd = reg_wdata[8]; - - assign perf_counter_enable_4_retired_acc_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_retired_acc_4_wd = reg_wdata[9]; - - assign perf_counter_enable_4_dma_aw_stall_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_aw_stall_4_wd = reg_wdata[10]; - - assign perf_counter_enable_4_dma_ar_stall_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_ar_stall_4_wd = reg_wdata[11]; - - assign perf_counter_enable_4_dma_r_stall_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_r_stall_4_wd = reg_wdata[12]; - - assign perf_counter_enable_4_dma_w_stall_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_w_stall_4_wd = reg_wdata[13]; - - assign perf_counter_enable_4_dma_buf_w_stall_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_buf_w_stall_4_wd = reg_wdata[14]; - - assign perf_counter_enable_4_dma_buf_r_stall_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_buf_r_stall_4_wd = reg_wdata[15]; - - assign perf_counter_enable_4_dma_aw_done_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_aw_done_4_wd = reg_wdata[16]; - - assign perf_counter_enable_4_dma_aw_bw_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_aw_bw_4_wd = reg_wdata[17]; - - assign perf_counter_enable_4_dma_ar_done_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_ar_done_4_wd = reg_wdata[18]; - - assign perf_counter_enable_4_dma_ar_bw_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_ar_bw_4_wd = reg_wdata[19]; - - assign perf_counter_enable_4_dma_r_done_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_r_done_4_wd = reg_wdata[20]; - - assign perf_counter_enable_4_dma_r_bw_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_r_bw_4_wd = reg_wdata[21]; - - assign perf_counter_enable_4_dma_w_done_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_w_done_4_wd = reg_wdata[22]; - - assign perf_counter_enable_4_dma_w_bw_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_w_bw_4_wd = reg_wdata[23]; - - assign perf_counter_enable_4_dma_b_done_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_b_done_4_wd = reg_wdata[24]; - - assign perf_counter_enable_4_dma_busy_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_dma_busy_4_wd = reg_wdata[25]; - - assign perf_counter_enable_4_icache_miss_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_icache_miss_4_wd = reg_wdata[26]; - - assign perf_counter_enable_4_icache_hit_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_icache_hit_4_wd = reg_wdata[27]; - - assign perf_counter_enable_4_icache_prefetch_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_icache_prefetch_4_wd = reg_wdata[28]; - - assign perf_counter_enable_4_icache_double_hit_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_icache_double_hit_4_wd = reg_wdata[29]; - - assign perf_counter_enable_4_icache_stall_4_we = addr_hit[4] & reg_we & !reg_error; - assign perf_counter_enable_4_icache_stall_4_wd = reg_wdata[30]; - - assign perf_counter_enable_5_cycle_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_cycle_5_wd = reg_wdata[0]; - - assign perf_counter_enable_5_tcdm_accessed_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_tcdm_accessed_5_wd = reg_wdata[1]; - - assign perf_counter_enable_5_tcdm_congested_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_tcdm_congested_5_wd = reg_wdata[2]; - - assign perf_counter_enable_5_issue_fpu_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_issue_fpu_5_wd = reg_wdata[3]; - - assign perf_counter_enable_5_issue_fpu_seq_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_issue_fpu_seq_5_wd = reg_wdata[4]; - - assign perf_counter_enable_5_issue_core_to_fpu_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_issue_core_to_fpu_5_wd = reg_wdata[5]; - - assign perf_counter_enable_5_retired_instr_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_retired_instr_5_wd = reg_wdata[6]; - - assign perf_counter_enable_5_retired_load_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_retired_load_5_wd = reg_wdata[7]; - - assign perf_counter_enable_5_retired_i_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_retired_i_5_wd = reg_wdata[8]; - - assign perf_counter_enable_5_retired_acc_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_retired_acc_5_wd = reg_wdata[9]; - - assign perf_counter_enable_5_dma_aw_stall_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_aw_stall_5_wd = reg_wdata[10]; - - assign perf_counter_enable_5_dma_ar_stall_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_ar_stall_5_wd = reg_wdata[11]; - - assign perf_counter_enable_5_dma_r_stall_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_r_stall_5_wd = reg_wdata[12]; - - assign perf_counter_enable_5_dma_w_stall_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_w_stall_5_wd = reg_wdata[13]; - - assign perf_counter_enable_5_dma_buf_w_stall_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_buf_w_stall_5_wd = reg_wdata[14]; - - assign perf_counter_enable_5_dma_buf_r_stall_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_buf_r_stall_5_wd = reg_wdata[15]; - - assign perf_counter_enable_5_dma_aw_done_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_aw_done_5_wd = reg_wdata[16]; - - assign perf_counter_enable_5_dma_aw_bw_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_aw_bw_5_wd = reg_wdata[17]; - - assign perf_counter_enable_5_dma_ar_done_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_ar_done_5_wd = reg_wdata[18]; - - assign perf_counter_enable_5_dma_ar_bw_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_ar_bw_5_wd = reg_wdata[19]; - - assign perf_counter_enable_5_dma_r_done_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_r_done_5_wd = reg_wdata[20]; - - assign perf_counter_enable_5_dma_r_bw_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_r_bw_5_wd = reg_wdata[21]; - - assign perf_counter_enable_5_dma_w_done_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_w_done_5_wd = reg_wdata[22]; - - assign perf_counter_enable_5_dma_w_bw_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_w_bw_5_wd = reg_wdata[23]; - - assign perf_counter_enable_5_dma_b_done_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_b_done_5_wd = reg_wdata[24]; - - assign perf_counter_enable_5_dma_busy_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_dma_busy_5_wd = reg_wdata[25]; - - assign perf_counter_enable_5_icache_miss_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_icache_miss_5_wd = reg_wdata[26]; - - assign perf_counter_enable_5_icache_hit_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_icache_hit_5_wd = reg_wdata[27]; - - assign perf_counter_enable_5_icache_prefetch_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_icache_prefetch_5_wd = reg_wdata[28]; - - assign perf_counter_enable_5_icache_double_hit_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_icache_double_hit_5_wd = reg_wdata[29]; - - assign perf_counter_enable_5_icache_stall_5_we = addr_hit[5] & reg_we & !reg_error; - assign perf_counter_enable_5_icache_stall_5_wd = reg_wdata[30]; - - assign perf_counter_enable_6_cycle_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_cycle_6_wd = reg_wdata[0]; - - assign perf_counter_enable_6_tcdm_accessed_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_tcdm_accessed_6_wd = reg_wdata[1]; - - assign perf_counter_enable_6_tcdm_congested_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_tcdm_congested_6_wd = reg_wdata[2]; - - assign perf_counter_enable_6_issue_fpu_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_issue_fpu_6_wd = reg_wdata[3]; - - assign perf_counter_enable_6_issue_fpu_seq_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_issue_fpu_seq_6_wd = reg_wdata[4]; - - assign perf_counter_enable_6_issue_core_to_fpu_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_issue_core_to_fpu_6_wd = reg_wdata[5]; - - assign perf_counter_enable_6_retired_instr_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_retired_instr_6_wd = reg_wdata[6]; - - assign perf_counter_enable_6_retired_load_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_retired_load_6_wd = reg_wdata[7]; - - assign perf_counter_enable_6_retired_i_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_retired_i_6_wd = reg_wdata[8]; - - assign perf_counter_enable_6_retired_acc_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_retired_acc_6_wd = reg_wdata[9]; - - assign perf_counter_enable_6_dma_aw_stall_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_aw_stall_6_wd = reg_wdata[10]; - - assign perf_counter_enable_6_dma_ar_stall_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_ar_stall_6_wd = reg_wdata[11]; - - assign perf_counter_enable_6_dma_r_stall_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_r_stall_6_wd = reg_wdata[12]; - - assign perf_counter_enable_6_dma_w_stall_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_w_stall_6_wd = reg_wdata[13]; - - assign perf_counter_enable_6_dma_buf_w_stall_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_buf_w_stall_6_wd = reg_wdata[14]; - - assign perf_counter_enable_6_dma_buf_r_stall_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_buf_r_stall_6_wd = reg_wdata[15]; - - assign perf_counter_enable_6_dma_aw_done_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_aw_done_6_wd = reg_wdata[16]; - - assign perf_counter_enable_6_dma_aw_bw_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_aw_bw_6_wd = reg_wdata[17]; - - assign perf_counter_enable_6_dma_ar_done_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_ar_done_6_wd = reg_wdata[18]; - - assign perf_counter_enable_6_dma_ar_bw_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_ar_bw_6_wd = reg_wdata[19]; - - assign perf_counter_enable_6_dma_r_done_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_r_done_6_wd = reg_wdata[20]; - - assign perf_counter_enable_6_dma_r_bw_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_r_bw_6_wd = reg_wdata[21]; - - assign perf_counter_enable_6_dma_w_done_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_w_done_6_wd = reg_wdata[22]; - - assign perf_counter_enable_6_dma_w_bw_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_w_bw_6_wd = reg_wdata[23]; - - assign perf_counter_enable_6_dma_b_done_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_b_done_6_wd = reg_wdata[24]; - - assign perf_counter_enable_6_dma_busy_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_dma_busy_6_wd = reg_wdata[25]; - - assign perf_counter_enable_6_icache_miss_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_icache_miss_6_wd = reg_wdata[26]; - - assign perf_counter_enable_6_icache_hit_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_icache_hit_6_wd = reg_wdata[27]; - - assign perf_counter_enable_6_icache_prefetch_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_icache_prefetch_6_wd = reg_wdata[28]; - - assign perf_counter_enable_6_icache_double_hit_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_icache_double_hit_6_wd = reg_wdata[29]; - - assign perf_counter_enable_6_icache_stall_6_we = addr_hit[6] & reg_we & !reg_error; - assign perf_counter_enable_6_icache_stall_6_wd = reg_wdata[30]; - - assign perf_counter_enable_7_cycle_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_cycle_7_wd = reg_wdata[0]; - - assign perf_counter_enable_7_tcdm_accessed_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_tcdm_accessed_7_wd = reg_wdata[1]; - - assign perf_counter_enable_7_tcdm_congested_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_tcdm_congested_7_wd = reg_wdata[2]; - - assign perf_counter_enable_7_issue_fpu_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_issue_fpu_7_wd = reg_wdata[3]; - - assign perf_counter_enable_7_issue_fpu_seq_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_issue_fpu_seq_7_wd = reg_wdata[4]; - - assign perf_counter_enable_7_issue_core_to_fpu_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_issue_core_to_fpu_7_wd = reg_wdata[5]; - - assign perf_counter_enable_7_retired_instr_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_retired_instr_7_wd = reg_wdata[6]; - - assign perf_counter_enable_7_retired_load_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_retired_load_7_wd = reg_wdata[7]; - - assign perf_counter_enable_7_retired_i_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_retired_i_7_wd = reg_wdata[8]; - - assign perf_counter_enable_7_retired_acc_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_retired_acc_7_wd = reg_wdata[9]; - - assign perf_counter_enable_7_dma_aw_stall_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_aw_stall_7_wd = reg_wdata[10]; - - assign perf_counter_enable_7_dma_ar_stall_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_ar_stall_7_wd = reg_wdata[11]; - - assign perf_counter_enable_7_dma_r_stall_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_r_stall_7_wd = reg_wdata[12]; - - assign perf_counter_enable_7_dma_w_stall_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_w_stall_7_wd = reg_wdata[13]; - - assign perf_counter_enable_7_dma_buf_w_stall_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_buf_w_stall_7_wd = reg_wdata[14]; - - assign perf_counter_enable_7_dma_buf_r_stall_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_buf_r_stall_7_wd = reg_wdata[15]; - - assign perf_counter_enable_7_dma_aw_done_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_aw_done_7_wd = reg_wdata[16]; - - assign perf_counter_enable_7_dma_aw_bw_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_aw_bw_7_wd = reg_wdata[17]; - - assign perf_counter_enable_7_dma_ar_done_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_ar_done_7_wd = reg_wdata[18]; - - assign perf_counter_enable_7_dma_ar_bw_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_ar_bw_7_wd = reg_wdata[19]; - - assign perf_counter_enable_7_dma_r_done_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_r_done_7_wd = reg_wdata[20]; - - assign perf_counter_enable_7_dma_r_bw_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_r_bw_7_wd = reg_wdata[21]; - - assign perf_counter_enable_7_dma_w_done_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_w_done_7_wd = reg_wdata[22]; - - assign perf_counter_enable_7_dma_w_bw_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_w_bw_7_wd = reg_wdata[23]; - - assign perf_counter_enable_7_dma_b_done_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_b_done_7_wd = reg_wdata[24]; - - assign perf_counter_enable_7_dma_busy_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_dma_busy_7_wd = reg_wdata[25]; - - assign perf_counter_enable_7_icache_miss_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_icache_miss_7_wd = reg_wdata[26]; - - assign perf_counter_enable_7_icache_hit_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_icache_hit_7_wd = reg_wdata[27]; - - assign perf_counter_enable_7_icache_prefetch_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_icache_prefetch_7_wd = reg_wdata[28]; - - assign perf_counter_enable_7_icache_double_hit_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_icache_double_hit_7_wd = reg_wdata[29]; - - assign perf_counter_enable_7_icache_stall_7_we = addr_hit[7] & reg_we & !reg_error; - assign perf_counter_enable_7_icache_stall_7_wd = reg_wdata[30]; - - assign perf_counter_enable_8_cycle_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_cycle_8_wd = reg_wdata[0]; - - assign perf_counter_enable_8_tcdm_accessed_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_tcdm_accessed_8_wd = reg_wdata[1]; - - assign perf_counter_enable_8_tcdm_congested_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_tcdm_congested_8_wd = reg_wdata[2]; - - assign perf_counter_enable_8_issue_fpu_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_issue_fpu_8_wd = reg_wdata[3]; - - assign perf_counter_enable_8_issue_fpu_seq_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_issue_fpu_seq_8_wd = reg_wdata[4]; - - assign perf_counter_enable_8_issue_core_to_fpu_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_issue_core_to_fpu_8_wd = reg_wdata[5]; - - assign perf_counter_enable_8_retired_instr_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_retired_instr_8_wd = reg_wdata[6]; - - assign perf_counter_enable_8_retired_load_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_retired_load_8_wd = reg_wdata[7]; - - assign perf_counter_enable_8_retired_i_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_retired_i_8_wd = reg_wdata[8]; - - assign perf_counter_enable_8_retired_acc_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_retired_acc_8_wd = reg_wdata[9]; - - assign perf_counter_enable_8_dma_aw_stall_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_aw_stall_8_wd = reg_wdata[10]; - - assign perf_counter_enable_8_dma_ar_stall_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_ar_stall_8_wd = reg_wdata[11]; - - assign perf_counter_enable_8_dma_r_stall_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_r_stall_8_wd = reg_wdata[12]; - - assign perf_counter_enable_8_dma_w_stall_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_w_stall_8_wd = reg_wdata[13]; - - assign perf_counter_enable_8_dma_buf_w_stall_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_buf_w_stall_8_wd = reg_wdata[14]; - - assign perf_counter_enable_8_dma_buf_r_stall_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_buf_r_stall_8_wd = reg_wdata[15]; - - assign perf_counter_enable_8_dma_aw_done_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_aw_done_8_wd = reg_wdata[16]; - - assign perf_counter_enable_8_dma_aw_bw_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_aw_bw_8_wd = reg_wdata[17]; - - assign perf_counter_enable_8_dma_ar_done_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_ar_done_8_wd = reg_wdata[18]; - - assign perf_counter_enable_8_dma_ar_bw_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_ar_bw_8_wd = reg_wdata[19]; - - assign perf_counter_enable_8_dma_r_done_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_r_done_8_wd = reg_wdata[20]; - - assign perf_counter_enable_8_dma_r_bw_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_r_bw_8_wd = reg_wdata[21]; - - assign perf_counter_enable_8_dma_w_done_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_w_done_8_wd = reg_wdata[22]; - - assign perf_counter_enable_8_dma_w_bw_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_w_bw_8_wd = reg_wdata[23]; - - assign perf_counter_enable_8_dma_b_done_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_b_done_8_wd = reg_wdata[24]; - - assign perf_counter_enable_8_dma_busy_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_dma_busy_8_wd = reg_wdata[25]; - - assign perf_counter_enable_8_icache_miss_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_icache_miss_8_wd = reg_wdata[26]; - - assign perf_counter_enable_8_icache_hit_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_icache_hit_8_wd = reg_wdata[27]; - - assign perf_counter_enable_8_icache_prefetch_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_icache_prefetch_8_wd = reg_wdata[28]; - - assign perf_counter_enable_8_icache_double_hit_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_icache_double_hit_8_wd = reg_wdata[29]; - - assign perf_counter_enable_8_icache_stall_8_we = addr_hit[8] & reg_we & !reg_error; - assign perf_counter_enable_8_icache_stall_8_wd = reg_wdata[30]; - - assign perf_counter_enable_9_cycle_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_cycle_9_wd = reg_wdata[0]; - - assign perf_counter_enable_9_tcdm_accessed_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_tcdm_accessed_9_wd = reg_wdata[1]; - - assign perf_counter_enable_9_tcdm_congested_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_tcdm_congested_9_wd = reg_wdata[2]; - - assign perf_counter_enable_9_issue_fpu_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_issue_fpu_9_wd = reg_wdata[3]; - - assign perf_counter_enable_9_issue_fpu_seq_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_issue_fpu_seq_9_wd = reg_wdata[4]; - - assign perf_counter_enable_9_issue_core_to_fpu_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_issue_core_to_fpu_9_wd = reg_wdata[5]; - - assign perf_counter_enable_9_retired_instr_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_retired_instr_9_wd = reg_wdata[6]; - - assign perf_counter_enable_9_retired_load_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_retired_load_9_wd = reg_wdata[7]; - - assign perf_counter_enable_9_retired_i_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_retired_i_9_wd = reg_wdata[8]; - - assign perf_counter_enable_9_retired_acc_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_retired_acc_9_wd = reg_wdata[9]; - - assign perf_counter_enable_9_dma_aw_stall_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_aw_stall_9_wd = reg_wdata[10]; - - assign perf_counter_enable_9_dma_ar_stall_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_ar_stall_9_wd = reg_wdata[11]; - - assign perf_counter_enable_9_dma_r_stall_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_r_stall_9_wd = reg_wdata[12]; - - assign perf_counter_enable_9_dma_w_stall_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_w_stall_9_wd = reg_wdata[13]; - - assign perf_counter_enable_9_dma_buf_w_stall_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_buf_w_stall_9_wd = reg_wdata[14]; - - assign perf_counter_enable_9_dma_buf_r_stall_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_buf_r_stall_9_wd = reg_wdata[15]; - - assign perf_counter_enable_9_dma_aw_done_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_aw_done_9_wd = reg_wdata[16]; - - assign perf_counter_enable_9_dma_aw_bw_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_aw_bw_9_wd = reg_wdata[17]; - - assign perf_counter_enable_9_dma_ar_done_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_ar_done_9_wd = reg_wdata[18]; - - assign perf_counter_enable_9_dma_ar_bw_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_ar_bw_9_wd = reg_wdata[19]; - - assign perf_counter_enable_9_dma_r_done_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_r_done_9_wd = reg_wdata[20]; - - assign perf_counter_enable_9_dma_r_bw_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_r_bw_9_wd = reg_wdata[21]; - - assign perf_counter_enable_9_dma_w_done_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_w_done_9_wd = reg_wdata[22]; - - assign perf_counter_enable_9_dma_w_bw_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_w_bw_9_wd = reg_wdata[23]; - - assign perf_counter_enable_9_dma_b_done_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_b_done_9_wd = reg_wdata[24]; - - assign perf_counter_enable_9_dma_busy_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_dma_busy_9_wd = reg_wdata[25]; - - assign perf_counter_enable_9_icache_miss_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_icache_miss_9_wd = reg_wdata[26]; - - assign perf_counter_enable_9_icache_hit_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_icache_hit_9_wd = reg_wdata[27]; - - assign perf_counter_enable_9_icache_prefetch_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_icache_prefetch_9_wd = reg_wdata[28]; - - assign perf_counter_enable_9_icache_double_hit_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_icache_double_hit_9_wd = reg_wdata[29]; - - assign perf_counter_enable_9_icache_stall_9_we = addr_hit[9] & reg_we & !reg_error; - assign perf_counter_enable_9_icache_stall_9_wd = reg_wdata[30]; - - assign perf_counter_enable_10_cycle_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_cycle_10_wd = reg_wdata[0]; - - assign perf_counter_enable_10_tcdm_accessed_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_tcdm_accessed_10_wd = reg_wdata[1]; - - assign perf_counter_enable_10_tcdm_congested_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_tcdm_congested_10_wd = reg_wdata[2]; - - assign perf_counter_enable_10_issue_fpu_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_issue_fpu_10_wd = reg_wdata[3]; - - assign perf_counter_enable_10_issue_fpu_seq_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_issue_fpu_seq_10_wd = reg_wdata[4]; - - assign perf_counter_enable_10_issue_core_to_fpu_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_issue_core_to_fpu_10_wd = reg_wdata[5]; - - assign perf_counter_enable_10_retired_instr_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_retired_instr_10_wd = reg_wdata[6]; - - assign perf_counter_enable_10_retired_load_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_retired_load_10_wd = reg_wdata[7]; - - assign perf_counter_enable_10_retired_i_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_retired_i_10_wd = reg_wdata[8]; - - assign perf_counter_enable_10_retired_acc_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_retired_acc_10_wd = reg_wdata[9]; - - assign perf_counter_enable_10_dma_aw_stall_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_aw_stall_10_wd = reg_wdata[10]; - - assign perf_counter_enable_10_dma_ar_stall_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_ar_stall_10_wd = reg_wdata[11]; - - assign perf_counter_enable_10_dma_r_stall_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_r_stall_10_wd = reg_wdata[12]; - - assign perf_counter_enable_10_dma_w_stall_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_w_stall_10_wd = reg_wdata[13]; - - assign perf_counter_enable_10_dma_buf_w_stall_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_buf_w_stall_10_wd = reg_wdata[14]; - - assign perf_counter_enable_10_dma_buf_r_stall_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_buf_r_stall_10_wd = reg_wdata[15]; - - assign perf_counter_enable_10_dma_aw_done_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_aw_done_10_wd = reg_wdata[16]; - - assign perf_counter_enable_10_dma_aw_bw_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_aw_bw_10_wd = reg_wdata[17]; - - assign perf_counter_enable_10_dma_ar_done_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_ar_done_10_wd = reg_wdata[18]; - - assign perf_counter_enable_10_dma_ar_bw_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_ar_bw_10_wd = reg_wdata[19]; - - assign perf_counter_enable_10_dma_r_done_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_r_done_10_wd = reg_wdata[20]; - - assign perf_counter_enable_10_dma_r_bw_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_r_bw_10_wd = reg_wdata[21]; - - assign perf_counter_enable_10_dma_w_done_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_w_done_10_wd = reg_wdata[22]; - - assign perf_counter_enable_10_dma_w_bw_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_w_bw_10_wd = reg_wdata[23]; - - assign perf_counter_enable_10_dma_b_done_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_b_done_10_wd = reg_wdata[24]; - - assign perf_counter_enable_10_dma_busy_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_dma_busy_10_wd = reg_wdata[25]; - - assign perf_counter_enable_10_icache_miss_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_icache_miss_10_wd = reg_wdata[26]; - - assign perf_counter_enable_10_icache_hit_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_icache_hit_10_wd = reg_wdata[27]; - - assign perf_counter_enable_10_icache_prefetch_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_icache_prefetch_10_wd = reg_wdata[28]; - - assign perf_counter_enable_10_icache_double_hit_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_icache_double_hit_10_wd = reg_wdata[29]; - - assign perf_counter_enable_10_icache_stall_10_we = addr_hit[10] & reg_we & !reg_error; - assign perf_counter_enable_10_icache_stall_10_wd = reg_wdata[30]; + // Subregister 14 of Multireg perf_cnt_sel + // R[perf_cnt_sel_14]: V(True) - assign perf_counter_enable_11_cycle_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_cycle_11_wd = reg_wdata[0]; - - assign perf_counter_enable_11_tcdm_accessed_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_tcdm_accessed_11_wd = reg_wdata[1]; - - assign perf_counter_enable_11_tcdm_congested_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_tcdm_congested_11_wd = reg_wdata[2]; - - assign perf_counter_enable_11_issue_fpu_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_issue_fpu_11_wd = reg_wdata[3]; - - assign perf_counter_enable_11_issue_fpu_seq_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_issue_fpu_seq_11_wd = reg_wdata[4]; - - assign perf_counter_enable_11_issue_core_to_fpu_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_issue_core_to_fpu_11_wd = reg_wdata[5]; - - assign perf_counter_enable_11_retired_instr_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_retired_instr_11_wd = reg_wdata[6]; - - assign perf_counter_enable_11_retired_load_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_retired_load_11_wd = reg_wdata[7]; - - assign perf_counter_enable_11_retired_i_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_retired_i_11_wd = reg_wdata[8]; - - assign perf_counter_enable_11_retired_acc_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_retired_acc_11_wd = reg_wdata[9]; - - assign perf_counter_enable_11_dma_aw_stall_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_aw_stall_11_wd = reg_wdata[10]; - - assign perf_counter_enable_11_dma_ar_stall_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_ar_stall_11_wd = reg_wdata[11]; - - assign perf_counter_enable_11_dma_r_stall_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_r_stall_11_wd = reg_wdata[12]; - - assign perf_counter_enable_11_dma_w_stall_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_w_stall_11_wd = reg_wdata[13]; - - assign perf_counter_enable_11_dma_buf_w_stall_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_buf_w_stall_11_wd = reg_wdata[14]; - - assign perf_counter_enable_11_dma_buf_r_stall_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_buf_r_stall_11_wd = reg_wdata[15]; - - assign perf_counter_enable_11_dma_aw_done_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_aw_done_11_wd = reg_wdata[16]; - - assign perf_counter_enable_11_dma_aw_bw_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_aw_bw_11_wd = reg_wdata[17]; - - assign perf_counter_enable_11_dma_ar_done_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_ar_done_11_wd = reg_wdata[18]; - - assign perf_counter_enable_11_dma_ar_bw_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_ar_bw_11_wd = reg_wdata[19]; - - assign perf_counter_enable_11_dma_r_done_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_r_done_11_wd = reg_wdata[20]; - - assign perf_counter_enable_11_dma_r_bw_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_r_bw_11_wd = reg_wdata[21]; - - assign perf_counter_enable_11_dma_w_done_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_w_done_11_wd = reg_wdata[22]; - - assign perf_counter_enable_11_dma_w_bw_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_w_bw_11_wd = reg_wdata[23]; - - assign perf_counter_enable_11_dma_b_done_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_b_done_11_wd = reg_wdata[24]; - - assign perf_counter_enable_11_dma_busy_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_dma_busy_11_wd = reg_wdata[25]; - - assign perf_counter_enable_11_icache_miss_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_icache_miss_11_wd = reg_wdata[26]; - - assign perf_counter_enable_11_icache_hit_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_icache_hit_11_wd = reg_wdata[27]; - - assign perf_counter_enable_11_icache_prefetch_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_icache_prefetch_11_wd = reg_wdata[28]; - - assign perf_counter_enable_11_icache_double_hit_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_icache_double_hit_11_wd = reg_wdata[29]; - - assign perf_counter_enable_11_icache_stall_11_we = addr_hit[11] & reg_we & !reg_error; - assign perf_counter_enable_11_icache_stall_11_wd = reg_wdata[30]; - - assign perf_counter_enable_12_cycle_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_cycle_12_wd = reg_wdata[0]; - - assign perf_counter_enable_12_tcdm_accessed_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_tcdm_accessed_12_wd = reg_wdata[1]; - - assign perf_counter_enable_12_tcdm_congested_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_tcdm_congested_12_wd = reg_wdata[2]; - - assign perf_counter_enable_12_issue_fpu_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_issue_fpu_12_wd = reg_wdata[3]; - - assign perf_counter_enable_12_issue_fpu_seq_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_issue_fpu_seq_12_wd = reg_wdata[4]; - - assign perf_counter_enable_12_issue_core_to_fpu_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_issue_core_to_fpu_12_wd = reg_wdata[5]; - - assign perf_counter_enable_12_retired_instr_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_retired_instr_12_wd = reg_wdata[6]; - - assign perf_counter_enable_12_retired_load_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_retired_load_12_wd = reg_wdata[7]; - - assign perf_counter_enable_12_retired_i_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_retired_i_12_wd = reg_wdata[8]; - - assign perf_counter_enable_12_retired_acc_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_retired_acc_12_wd = reg_wdata[9]; - - assign perf_counter_enable_12_dma_aw_stall_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_aw_stall_12_wd = reg_wdata[10]; - - assign perf_counter_enable_12_dma_ar_stall_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_ar_stall_12_wd = reg_wdata[11]; - - assign perf_counter_enable_12_dma_r_stall_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_r_stall_12_wd = reg_wdata[12]; - - assign perf_counter_enable_12_dma_w_stall_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_w_stall_12_wd = reg_wdata[13]; - - assign perf_counter_enable_12_dma_buf_w_stall_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_buf_w_stall_12_wd = reg_wdata[14]; - - assign perf_counter_enable_12_dma_buf_r_stall_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_buf_r_stall_12_wd = reg_wdata[15]; - - assign perf_counter_enable_12_dma_aw_done_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_aw_done_12_wd = reg_wdata[16]; - - assign perf_counter_enable_12_dma_aw_bw_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_aw_bw_12_wd = reg_wdata[17]; - - assign perf_counter_enable_12_dma_ar_done_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_ar_done_12_wd = reg_wdata[18]; - - assign perf_counter_enable_12_dma_ar_bw_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_ar_bw_12_wd = reg_wdata[19]; - - assign perf_counter_enable_12_dma_r_done_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_r_done_12_wd = reg_wdata[20]; - - assign perf_counter_enable_12_dma_r_bw_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_r_bw_12_wd = reg_wdata[21]; - - assign perf_counter_enable_12_dma_w_done_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_w_done_12_wd = reg_wdata[22]; - - assign perf_counter_enable_12_dma_w_bw_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_w_bw_12_wd = reg_wdata[23]; - - assign perf_counter_enable_12_dma_b_done_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_b_done_12_wd = reg_wdata[24]; - - assign perf_counter_enable_12_dma_busy_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_dma_busy_12_wd = reg_wdata[25]; - - assign perf_counter_enable_12_icache_miss_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_icache_miss_12_wd = reg_wdata[26]; - - assign perf_counter_enable_12_icache_hit_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_icache_hit_12_wd = reg_wdata[27]; - - assign perf_counter_enable_12_icache_prefetch_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_icache_prefetch_12_wd = reg_wdata[28]; - - assign perf_counter_enable_12_icache_double_hit_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_icache_double_hit_12_wd = reg_wdata[29]; - - assign perf_counter_enable_12_icache_stall_12_we = addr_hit[12] & reg_we & !reg_error; - assign perf_counter_enable_12_icache_stall_12_wd = reg_wdata[30]; + // F[hart_14]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_14_hart_14 ( + .re (perf_cnt_sel_14_hart_14_re), + .we (perf_cnt_sel_14_hart_14_we), + .wd (perf_cnt_sel_14_hart_14_wd), + .d (hw2reg.perf_cnt_sel[14].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[14].hart.qe), + .q (reg2hw.perf_cnt_sel[14].hart.q ), + .qs (perf_cnt_sel_14_hart_14_qs) + ); - assign perf_counter_enable_13_cycle_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_cycle_13_wd = reg_wdata[0]; - assign perf_counter_enable_13_tcdm_accessed_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_tcdm_accessed_13_wd = reg_wdata[1]; + // F[metric_14]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_14_metric_14 ( + .re (perf_cnt_sel_14_metric_14_re), + .we (perf_cnt_sel_14_metric_14_we), + .wd (perf_cnt_sel_14_metric_14_wd), + .d (hw2reg.perf_cnt_sel[14].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[14].metric.qe), + .q (reg2hw.perf_cnt_sel[14].metric.q ), + .qs (perf_cnt_sel_14_metric_14_qs) + ); - assign perf_counter_enable_13_tcdm_congested_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_tcdm_congested_13_wd = reg_wdata[2]; - assign perf_counter_enable_13_issue_fpu_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_issue_fpu_13_wd = reg_wdata[3]; + // Subregister 15 of Multireg perf_cnt_sel + // R[perf_cnt_sel_15]: V(True) - assign perf_counter_enable_13_issue_fpu_seq_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_issue_fpu_seq_13_wd = reg_wdata[4]; + // F[hart_15]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_15_hart_15 ( + .re (perf_cnt_sel_15_hart_15_re), + .we (perf_cnt_sel_15_hart_15_we), + .wd (perf_cnt_sel_15_hart_15_wd), + .d (hw2reg.perf_cnt_sel[15].hart.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[15].hart.qe), + .q (reg2hw.perf_cnt_sel[15].hart.q ), + .qs (perf_cnt_sel_15_hart_15_qs) + ); - assign perf_counter_enable_13_issue_core_to_fpu_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_issue_core_to_fpu_13_wd = reg_wdata[5]; - assign perf_counter_enable_13_retired_instr_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_retired_instr_13_wd = reg_wdata[6]; + // F[metric_15]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_perf_cnt_sel_15_metric_15 ( + .re (perf_cnt_sel_15_metric_15_re), + .we (perf_cnt_sel_15_metric_15_we), + .wd (perf_cnt_sel_15_metric_15_wd), + .d (hw2reg.perf_cnt_sel[15].metric.d), + .qre (), + .qe (reg2hw.perf_cnt_sel[15].metric.qe), + .q (reg2hw.perf_cnt_sel[15].metric.q ), + .qs (perf_cnt_sel_15_metric_15_qs) + ); - assign perf_counter_enable_13_retired_load_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_retired_load_13_wd = reg_wdata[7]; - assign perf_counter_enable_13_retired_i_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_retired_i_13_wd = reg_wdata[8]; - assign perf_counter_enable_13_retired_acc_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_retired_acc_13_wd = reg_wdata[9]; - assign perf_counter_enable_13_dma_aw_stall_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_aw_stall_13_wd = reg_wdata[10]; + // Subregister 0 of Multireg perf_cnt + // R[perf_cnt_0]: V(True) - assign perf_counter_enable_13_dma_ar_stall_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_ar_stall_13_wd = reg_wdata[11]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_0 ( + .re (perf_cnt_0_re), + .we (perf_cnt_0_we), + .wd (perf_cnt_0_wd), + .d (hw2reg.perf_cnt[0].d), + .qre (), + .qe (reg2hw.perf_cnt[0].qe), + .q (reg2hw.perf_cnt[0].q ), + .qs (perf_cnt_0_qs) + ); - assign perf_counter_enable_13_dma_r_stall_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_r_stall_13_wd = reg_wdata[12]; + // Subregister 1 of Multireg perf_cnt + // R[perf_cnt_1]: V(True) - assign perf_counter_enable_13_dma_w_stall_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_w_stall_13_wd = reg_wdata[13]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_1 ( + .re (perf_cnt_1_re), + .we (perf_cnt_1_we), + .wd (perf_cnt_1_wd), + .d (hw2reg.perf_cnt[1].d), + .qre (), + .qe (reg2hw.perf_cnt[1].qe), + .q (reg2hw.perf_cnt[1].q ), + .qs (perf_cnt_1_qs) + ); - assign perf_counter_enable_13_dma_buf_w_stall_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_buf_w_stall_13_wd = reg_wdata[14]; + // Subregister 2 of Multireg perf_cnt + // R[perf_cnt_2]: V(True) - assign perf_counter_enable_13_dma_buf_r_stall_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_buf_r_stall_13_wd = reg_wdata[15]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_2 ( + .re (perf_cnt_2_re), + .we (perf_cnt_2_we), + .wd (perf_cnt_2_wd), + .d (hw2reg.perf_cnt[2].d), + .qre (), + .qe (reg2hw.perf_cnt[2].qe), + .q (reg2hw.perf_cnt[2].q ), + .qs (perf_cnt_2_qs) + ); - assign perf_counter_enable_13_dma_aw_done_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_aw_done_13_wd = reg_wdata[16]; + // Subregister 3 of Multireg perf_cnt + // R[perf_cnt_3]: V(True) - assign perf_counter_enable_13_dma_aw_bw_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_aw_bw_13_wd = reg_wdata[17]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_3 ( + .re (perf_cnt_3_re), + .we (perf_cnt_3_we), + .wd (perf_cnt_3_wd), + .d (hw2reg.perf_cnt[3].d), + .qre (), + .qe (reg2hw.perf_cnt[3].qe), + .q (reg2hw.perf_cnt[3].q ), + .qs (perf_cnt_3_qs) + ); - assign perf_counter_enable_13_dma_ar_done_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_ar_done_13_wd = reg_wdata[18]; + // Subregister 4 of Multireg perf_cnt + // R[perf_cnt_4]: V(True) - assign perf_counter_enable_13_dma_ar_bw_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_ar_bw_13_wd = reg_wdata[19]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_4 ( + .re (perf_cnt_4_re), + .we (perf_cnt_4_we), + .wd (perf_cnt_4_wd), + .d (hw2reg.perf_cnt[4].d), + .qre (), + .qe (reg2hw.perf_cnt[4].qe), + .q (reg2hw.perf_cnt[4].q ), + .qs (perf_cnt_4_qs) + ); - assign perf_counter_enable_13_dma_r_done_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_r_done_13_wd = reg_wdata[20]; + // Subregister 5 of Multireg perf_cnt + // R[perf_cnt_5]: V(True) - assign perf_counter_enable_13_dma_r_bw_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_r_bw_13_wd = reg_wdata[21]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_5 ( + .re (perf_cnt_5_re), + .we (perf_cnt_5_we), + .wd (perf_cnt_5_wd), + .d (hw2reg.perf_cnt[5].d), + .qre (), + .qe (reg2hw.perf_cnt[5].qe), + .q (reg2hw.perf_cnt[5].q ), + .qs (perf_cnt_5_qs) + ); - assign perf_counter_enable_13_dma_w_done_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_w_done_13_wd = reg_wdata[22]; + // Subregister 6 of Multireg perf_cnt + // R[perf_cnt_6]: V(True) - assign perf_counter_enable_13_dma_w_bw_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_w_bw_13_wd = reg_wdata[23]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_6 ( + .re (perf_cnt_6_re), + .we (perf_cnt_6_we), + .wd (perf_cnt_6_wd), + .d (hw2reg.perf_cnt[6].d), + .qre (), + .qe (reg2hw.perf_cnt[6].qe), + .q (reg2hw.perf_cnt[6].q ), + .qs (perf_cnt_6_qs) + ); - assign perf_counter_enable_13_dma_b_done_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_b_done_13_wd = reg_wdata[24]; + // Subregister 7 of Multireg perf_cnt + // R[perf_cnt_7]: V(True) - assign perf_counter_enable_13_dma_busy_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_dma_busy_13_wd = reg_wdata[25]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_7 ( + .re (perf_cnt_7_re), + .we (perf_cnt_7_we), + .wd (perf_cnt_7_wd), + .d (hw2reg.perf_cnt[7].d), + .qre (), + .qe (reg2hw.perf_cnt[7].qe), + .q (reg2hw.perf_cnt[7].q ), + .qs (perf_cnt_7_qs) + ); - assign perf_counter_enable_13_icache_miss_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_icache_miss_13_wd = reg_wdata[26]; + // Subregister 8 of Multireg perf_cnt + // R[perf_cnt_8]: V(True) - assign perf_counter_enable_13_icache_hit_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_icache_hit_13_wd = reg_wdata[27]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_8 ( + .re (perf_cnt_8_re), + .we (perf_cnt_8_we), + .wd (perf_cnt_8_wd), + .d (hw2reg.perf_cnt[8].d), + .qre (), + .qe (reg2hw.perf_cnt[8].qe), + .q (reg2hw.perf_cnt[8].q ), + .qs (perf_cnt_8_qs) + ); - assign perf_counter_enable_13_icache_prefetch_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_icache_prefetch_13_wd = reg_wdata[28]; + // Subregister 9 of Multireg perf_cnt + // R[perf_cnt_9]: V(True) - assign perf_counter_enable_13_icache_double_hit_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_icache_double_hit_13_wd = reg_wdata[29]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_9 ( + .re (perf_cnt_9_re), + .we (perf_cnt_9_we), + .wd (perf_cnt_9_wd), + .d (hw2reg.perf_cnt[9].d), + .qre (), + .qe (reg2hw.perf_cnt[9].qe), + .q (reg2hw.perf_cnt[9].q ), + .qs (perf_cnt_9_qs) + ); - assign perf_counter_enable_13_icache_stall_13_we = addr_hit[13] & reg_we & !reg_error; - assign perf_counter_enable_13_icache_stall_13_wd = reg_wdata[30]; + // Subregister 10 of Multireg perf_cnt + // R[perf_cnt_10]: V(True) - assign perf_counter_enable_14_cycle_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_cycle_14_wd = reg_wdata[0]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_10 ( + .re (perf_cnt_10_re), + .we (perf_cnt_10_we), + .wd (perf_cnt_10_wd), + .d (hw2reg.perf_cnt[10].d), + .qre (), + .qe (reg2hw.perf_cnt[10].qe), + .q (reg2hw.perf_cnt[10].q ), + .qs (perf_cnt_10_qs) + ); - assign perf_counter_enable_14_tcdm_accessed_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_tcdm_accessed_14_wd = reg_wdata[1]; + // Subregister 11 of Multireg perf_cnt + // R[perf_cnt_11]: V(True) - assign perf_counter_enable_14_tcdm_congested_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_tcdm_congested_14_wd = reg_wdata[2]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_11 ( + .re (perf_cnt_11_re), + .we (perf_cnt_11_we), + .wd (perf_cnt_11_wd), + .d (hw2reg.perf_cnt[11].d), + .qre (), + .qe (reg2hw.perf_cnt[11].qe), + .q (reg2hw.perf_cnt[11].q ), + .qs (perf_cnt_11_qs) + ); - assign perf_counter_enable_14_issue_fpu_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_issue_fpu_14_wd = reg_wdata[3]; + // Subregister 12 of Multireg perf_cnt + // R[perf_cnt_12]: V(True) - assign perf_counter_enable_14_issue_fpu_seq_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_issue_fpu_seq_14_wd = reg_wdata[4]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_12 ( + .re (perf_cnt_12_re), + .we (perf_cnt_12_we), + .wd (perf_cnt_12_wd), + .d (hw2reg.perf_cnt[12].d), + .qre (), + .qe (reg2hw.perf_cnt[12].qe), + .q (reg2hw.perf_cnt[12].q ), + .qs (perf_cnt_12_qs) + ); - assign perf_counter_enable_14_issue_core_to_fpu_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_issue_core_to_fpu_14_wd = reg_wdata[5]; + // Subregister 13 of Multireg perf_cnt + // R[perf_cnt_13]: V(True) - assign perf_counter_enable_14_retired_instr_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_retired_instr_14_wd = reg_wdata[6]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_13 ( + .re (perf_cnt_13_re), + .we (perf_cnt_13_we), + .wd (perf_cnt_13_wd), + .d (hw2reg.perf_cnt[13].d), + .qre (), + .qe (reg2hw.perf_cnt[13].qe), + .q (reg2hw.perf_cnt[13].q ), + .qs (perf_cnt_13_qs) + ); - assign perf_counter_enable_14_retired_load_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_retired_load_14_wd = reg_wdata[7]; + // Subregister 14 of Multireg perf_cnt + // R[perf_cnt_14]: V(True) - assign perf_counter_enable_14_retired_i_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_retired_i_14_wd = reg_wdata[8]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_14 ( + .re (perf_cnt_14_re), + .we (perf_cnt_14_we), + .wd (perf_cnt_14_wd), + .d (hw2reg.perf_cnt[14].d), + .qre (), + .qe (reg2hw.perf_cnt[14].qe), + .q (reg2hw.perf_cnt[14].q ), + .qs (perf_cnt_14_qs) + ); - assign perf_counter_enable_14_retired_acc_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_retired_acc_14_wd = reg_wdata[9]; + // Subregister 15 of Multireg perf_cnt + // R[perf_cnt_15]: V(True) - assign perf_counter_enable_14_dma_aw_stall_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_aw_stall_14_wd = reg_wdata[10]; + prim_subreg_ext #( + .DW (48) + ) u_perf_cnt_15 ( + .re (perf_cnt_15_re), + .we (perf_cnt_15_we), + .wd (perf_cnt_15_wd), + .d (hw2reg.perf_cnt[15].d), + .qre (), + .qe (reg2hw.perf_cnt[15].qe), + .q (reg2hw.perf_cnt[15].q ), + .qs (perf_cnt_15_qs) + ); - assign perf_counter_enable_14_dma_ar_stall_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_ar_stall_14_wd = reg_wdata[11]; - assign perf_counter_enable_14_dma_r_stall_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_r_stall_14_wd = reg_wdata[12]; + // R[cl_clint_set]: V(True) - assign perf_counter_enable_14_dma_w_stall_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_w_stall_14_wd = reg_wdata[13]; + prim_subreg_ext #( + .DW (32) + ) u_cl_clint_set ( + .re (1'b0), + .we (cl_clint_set_we), + .wd (cl_clint_set_wd), + .d ('0), + .qre (), + .qe (reg2hw.cl_clint_set.qe), + .q (reg2hw.cl_clint_set.q ), + .qs () + ); - assign perf_counter_enable_14_dma_buf_w_stall_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_buf_w_stall_14_wd = reg_wdata[14]; - assign perf_counter_enable_14_dma_buf_r_stall_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_buf_r_stall_14_wd = reg_wdata[15]; + // R[cl_clint_clear]: V(True) - assign perf_counter_enable_14_dma_aw_done_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_aw_done_14_wd = reg_wdata[16]; + prim_subreg_ext #( + .DW (32) + ) u_cl_clint_clear ( + .re (1'b0), + .we (cl_clint_clear_we), + .wd (cl_clint_clear_wd), + .d ('0), + .qre (), + .qe (reg2hw.cl_clint_clear.qe), + .q (reg2hw.cl_clint_clear.q ), + .qs () + ); - assign perf_counter_enable_14_dma_aw_bw_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_aw_bw_14_wd = reg_wdata[17]; - assign perf_counter_enable_14_dma_ar_done_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_ar_done_14_wd = reg_wdata[18]; + // R[icache_prefetch_enable]: V(False) - assign perf_counter_enable_14_dma_ar_bw_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_ar_bw_14_wd = reg_wdata[19]; + prim_subreg #( + .DW (1), + .SWACCESS("WO"), + .RESVAL (1'h1) + ) u_icache_prefetch_enable ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), - assign perf_counter_enable_14_dma_r_done_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_r_done_14_wd = reg_wdata[20]; + // from register interface + .we (icache_prefetch_enable_we), + .wd (icache_prefetch_enable_wd), - assign perf_counter_enable_14_dma_r_bw_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_r_bw_14_wd = reg_wdata[21]; + // from internal hardware + .de (1'b0), + .d ('0 ), - assign perf_counter_enable_14_dma_w_done_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_w_done_14_wd = reg_wdata[22]; + // to internal hardware + .qe (), + .q (reg2hw.icache_prefetch_enable.q ), - assign perf_counter_enable_14_dma_w_bw_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_w_bw_14_wd = reg_wdata[23]; + .qs () + ); - assign perf_counter_enable_14_dma_b_done_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_b_done_14_wd = reg_wdata[24]; - assign perf_counter_enable_14_dma_busy_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_dma_busy_14_wd = reg_wdata[25]; - assign perf_counter_enable_14_icache_miss_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_icache_miss_14_wd = reg_wdata[26]; - assign perf_counter_enable_14_icache_hit_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_icache_hit_14_wd = reg_wdata[27]; + logic [50:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_OFFSET); + addr_hit[ 1] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1_OFFSET); + addr_hit[ 2] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2_OFFSET); + addr_hit[ 3] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_3_OFFSET); + addr_hit[ 4] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_4_OFFSET); + addr_hit[ 5] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_5_OFFSET); + addr_hit[ 6] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_6_OFFSET); + addr_hit[ 7] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_7_OFFSET); + addr_hit[ 8] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_8_OFFSET); + addr_hit[ 9] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_9_OFFSET); + addr_hit[10] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_10_OFFSET); + addr_hit[11] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_11_OFFSET); + addr_hit[12] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_12_OFFSET); + addr_hit[13] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_13_OFFSET); + addr_hit[14] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_14_OFFSET); + addr_hit[15] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_15_OFFSET); + addr_hit[16] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_OFFSET); + addr_hit[17] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_1_OFFSET); + addr_hit[18] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_2_OFFSET); + addr_hit[19] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_3_OFFSET); + addr_hit[20] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_4_OFFSET); + addr_hit[21] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_5_OFFSET); + addr_hit[22] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_6_OFFSET); + addr_hit[23] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_7_OFFSET); + addr_hit[24] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_8_OFFSET); + addr_hit[25] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_9_OFFSET); + addr_hit[26] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_10_OFFSET); + addr_hit[27] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_11_OFFSET); + addr_hit[28] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_12_OFFSET); + addr_hit[29] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_13_OFFSET); + addr_hit[30] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_14_OFFSET); + addr_hit[31] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_15_OFFSET); + addr_hit[32] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_0_OFFSET); + addr_hit[33] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_1_OFFSET); + addr_hit[34] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_2_OFFSET); + addr_hit[35] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_3_OFFSET); + addr_hit[36] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_4_OFFSET); + addr_hit[37] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_5_OFFSET); + addr_hit[38] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_6_OFFSET); + addr_hit[39] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_7_OFFSET); + addr_hit[40] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_8_OFFSET); + addr_hit[41] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_9_OFFSET); + addr_hit[42] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_10_OFFSET); + addr_hit[43] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_11_OFFSET); + addr_hit[44] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_12_OFFSET); + addr_hit[45] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET); + addr_hit[46] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET); + addr_hit[47] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET); + addr_hit[48] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET); + addr_hit[49] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET); + addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET); + end - assign perf_counter_enable_14_icache_prefetch_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_icache_prefetch_14_wd = reg_wdata[28]; + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - assign perf_counter_enable_14_icache_double_hit_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_icache_double_hit_14_wd = reg_wdata[29]; + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[44] & ~reg_be))) | + (addr_hit[45] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[45] & ~reg_be))) | + (addr_hit[46] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[46] & ~reg_be))) | + (addr_hit[47] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[47] & ~reg_be))) | + (addr_hit[48] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[48] & ~reg_be))) | + (addr_hit[49] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[49] & ~reg_be))) | + (addr_hit[50] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[50] & ~reg_be))))); + end - assign perf_counter_enable_14_icache_stall_14_we = addr_hit[14] & reg_we & !reg_error; - assign perf_counter_enable_14_icache_stall_14_wd = reg_wdata[30]; + assign perf_cnt_en_0_we = addr_hit[0] & reg_we & !reg_error; + assign perf_cnt_en_0_wd = reg_wdata[0]; - assign perf_counter_enable_15_cycle_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_cycle_15_wd = reg_wdata[0]; + assign perf_cnt_en_1_we = addr_hit[1] & reg_we & !reg_error; + assign perf_cnt_en_1_wd = reg_wdata[0]; - assign perf_counter_enable_15_tcdm_accessed_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_tcdm_accessed_15_wd = reg_wdata[1]; + assign perf_cnt_en_2_we = addr_hit[2] & reg_we & !reg_error; + assign perf_cnt_en_2_wd = reg_wdata[0]; - assign perf_counter_enable_15_tcdm_congested_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_tcdm_congested_15_wd = reg_wdata[2]; + assign perf_cnt_en_3_we = addr_hit[3] & reg_we & !reg_error; + assign perf_cnt_en_3_wd = reg_wdata[0]; - assign perf_counter_enable_15_issue_fpu_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_issue_fpu_15_wd = reg_wdata[3]; + assign perf_cnt_en_4_we = addr_hit[4] & reg_we & !reg_error; + assign perf_cnt_en_4_wd = reg_wdata[0]; - assign perf_counter_enable_15_issue_fpu_seq_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_issue_fpu_seq_15_wd = reg_wdata[4]; + assign perf_cnt_en_5_we = addr_hit[5] & reg_we & !reg_error; + assign perf_cnt_en_5_wd = reg_wdata[0]; - assign perf_counter_enable_15_issue_core_to_fpu_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_issue_core_to_fpu_15_wd = reg_wdata[5]; + assign perf_cnt_en_6_we = addr_hit[6] & reg_we & !reg_error; + assign perf_cnt_en_6_wd = reg_wdata[0]; - assign perf_counter_enable_15_retired_instr_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_retired_instr_15_wd = reg_wdata[6]; + assign perf_cnt_en_7_we = addr_hit[7] & reg_we & !reg_error; + assign perf_cnt_en_7_wd = reg_wdata[0]; - assign perf_counter_enable_15_retired_load_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_retired_load_15_wd = reg_wdata[7]; + assign perf_cnt_en_8_we = addr_hit[8] & reg_we & !reg_error; + assign perf_cnt_en_8_wd = reg_wdata[0]; - assign perf_counter_enable_15_retired_i_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_retired_i_15_wd = reg_wdata[8]; + assign perf_cnt_en_9_we = addr_hit[9] & reg_we & !reg_error; + assign perf_cnt_en_9_wd = reg_wdata[0]; - assign perf_counter_enable_15_retired_acc_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_retired_acc_15_wd = reg_wdata[9]; + assign perf_cnt_en_10_we = addr_hit[10] & reg_we & !reg_error; + assign perf_cnt_en_10_wd = reg_wdata[0]; - assign perf_counter_enable_15_dma_aw_stall_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_aw_stall_15_wd = reg_wdata[10]; + assign perf_cnt_en_11_we = addr_hit[11] & reg_we & !reg_error; + assign perf_cnt_en_11_wd = reg_wdata[0]; - assign perf_counter_enable_15_dma_ar_stall_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_ar_stall_15_wd = reg_wdata[11]; + assign perf_cnt_en_12_we = addr_hit[12] & reg_we & !reg_error; + assign perf_cnt_en_12_wd = reg_wdata[0]; - assign perf_counter_enable_15_dma_r_stall_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_r_stall_15_wd = reg_wdata[12]; + assign perf_cnt_en_13_we = addr_hit[13] & reg_we & !reg_error; + assign perf_cnt_en_13_wd = reg_wdata[0]; - assign perf_counter_enable_15_dma_w_stall_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_w_stall_15_wd = reg_wdata[13]; + assign perf_cnt_en_14_we = addr_hit[14] & reg_we & !reg_error; + assign perf_cnt_en_14_wd = reg_wdata[0]; - assign perf_counter_enable_15_dma_buf_w_stall_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_buf_w_stall_15_wd = reg_wdata[14]; + assign perf_cnt_en_15_we = addr_hit[15] & reg_we & !reg_error; + assign perf_cnt_en_15_wd = reg_wdata[0]; - assign perf_counter_enable_15_dma_buf_r_stall_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_buf_r_stall_15_wd = reg_wdata[15]; + assign perf_cnt_sel_0_hart_0_we = addr_hit[16] & reg_we & !reg_error; + assign perf_cnt_sel_0_hart_0_wd = reg_wdata[15:0]; + assign perf_cnt_sel_0_hart_0_re = addr_hit[16] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_aw_done_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_aw_done_15_wd = reg_wdata[16]; + assign perf_cnt_sel_0_metric_0_we = addr_hit[16] & reg_we & !reg_error; + assign perf_cnt_sel_0_metric_0_wd = reg_wdata[31:16]; + assign perf_cnt_sel_0_metric_0_re = addr_hit[16] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_aw_bw_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_aw_bw_15_wd = reg_wdata[17]; + assign perf_cnt_sel_1_hart_1_we = addr_hit[17] & reg_we & !reg_error; + assign perf_cnt_sel_1_hart_1_wd = reg_wdata[15:0]; + assign perf_cnt_sel_1_hart_1_re = addr_hit[17] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_ar_done_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_ar_done_15_wd = reg_wdata[18]; + assign perf_cnt_sel_1_metric_1_we = addr_hit[17] & reg_we & !reg_error; + assign perf_cnt_sel_1_metric_1_wd = reg_wdata[31:16]; + assign perf_cnt_sel_1_metric_1_re = addr_hit[17] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_ar_bw_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_ar_bw_15_wd = reg_wdata[19]; + assign perf_cnt_sel_2_hart_2_we = addr_hit[18] & reg_we & !reg_error; + assign perf_cnt_sel_2_hart_2_wd = reg_wdata[15:0]; + assign perf_cnt_sel_2_hart_2_re = addr_hit[18] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_r_done_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_r_done_15_wd = reg_wdata[20]; + assign perf_cnt_sel_2_metric_2_we = addr_hit[18] & reg_we & !reg_error; + assign perf_cnt_sel_2_metric_2_wd = reg_wdata[31:16]; + assign perf_cnt_sel_2_metric_2_re = addr_hit[18] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_r_bw_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_r_bw_15_wd = reg_wdata[21]; + assign perf_cnt_sel_3_hart_3_we = addr_hit[19] & reg_we & !reg_error; + assign perf_cnt_sel_3_hart_3_wd = reg_wdata[15:0]; + assign perf_cnt_sel_3_hart_3_re = addr_hit[19] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_w_done_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_w_done_15_wd = reg_wdata[22]; + assign perf_cnt_sel_3_metric_3_we = addr_hit[19] & reg_we & !reg_error; + assign perf_cnt_sel_3_metric_3_wd = reg_wdata[31:16]; + assign perf_cnt_sel_3_metric_3_re = addr_hit[19] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_w_bw_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_w_bw_15_wd = reg_wdata[23]; + assign perf_cnt_sel_4_hart_4_we = addr_hit[20] & reg_we & !reg_error; + assign perf_cnt_sel_4_hart_4_wd = reg_wdata[15:0]; + assign perf_cnt_sel_4_hart_4_re = addr_hit[20] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_b_done_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_b_done_15_wd = reg_wdata[24]; + assign perf_cnt_sel_4_metric_4_we = addr_hit[20] & reg_we & !reg_error; + assign perf_cnt_sel_4_metric_4_wd = reg_wdata[31:16]; + assign perf_cnt_sel_4_metric_4_re = addr_hit[20] & reg_re & !reg_error; - assign perf_counter_enable_15_dma_busy_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_dma_busy_15_wd = reg_wdata[25]; + assign perf_cnt_sel_5_hart_5_we = addr_hit[21] & reg_we & !reg_error; + assign perf_cnt_sel_5_hart_5_wd = reg_wdata[15:0]; + assign perf_cnt_sel_5_hart_5_re = addr_hit[21] & reg_re & !reg_error; - assign perf_counter_enable_15_icache_miss_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_icache_miss_15_wd = reg_wdata[26]; + assign perf_cnt_sel_5_metric_5_we = addr_hit[21] & reg_we & !reg_error; + assign perf_cnt_sel_5_metric_5_wd = reg_wdata[31:16]; + assign perf_cnt_sel_5_metric_5_re = addr_hit[21] & reg_re & !reg_error; - assign perf_counter_enable_15_icache_hit_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_icache_hit_15_wd = reg_wdata[27]; + assign perf_cnt_sel_6_hart_6_we = addr_hit[22] & reg_we & !reg_error; + assign perf_cnt_sel_6_hart_6_wd = reg_wdata[15:0]; + assign perf_cnt_sel_6_hart_6_re = addr_hit[22] & reg_re & !reg_error; - assign perf_counter_enable_15_icache_prefetch_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_icache_prefetch_15_wd = reg_wdata[28]; + assign perf_cnt_sel_6_metric_6_we = addr_hit[22] & reg_we & !reg_error; + assign perf_cnt_sel_6_metric_6_wd = reg_wdata[31:16]; + assign perf_cnt_sel_6_metric_6_re = addr_hit[22] & reg_re & !reg_error; - assign perf_counter_enable_15_icache_double_hit_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_icache_double_hit_15_wd = reg_wdata[29]; + assign perf_cnt_sel_7_hart_7_we = addr_hit[23] & reg_we & !reg_error; + assign perf_cnt_sel_7_hart_7_wd = reg_wdata[15:0]; + assign perf_cnt_sel_7_hart_7_re = addr_hit[23] & reg_re & !reg_error; - assign perf_counter_enable_15_icache_stall_15_we = addr_hit[15] & reg_we & !reg_error; - assign perf_counter_enable_15_icache_stall_15_wd = reg_wdata[30]; + assign perf_cnt_sel_7_metric_7_we = addr_hit[23] & reg_we & !reg_error; + assign perf_cnt_sel_7_metric_7_wd = reg_wdata[31:16]; + assign perf_cnt_sel_7_metric_7_re = addr_hit[23] & reg_re & !reg_error; - assign hart_select_0_we = addr_hit[16] & reg_we & !reg_error; - assign hart_select_0_wd = reg_wdata[9:0]; + assign perf_cnt_sel_8_hart_8_we = addr_hit[24] & reg_we & !reg_error; + assign perf_cnt_sel_8_hart_8_wd = reg_wdata[15:0]; + assign perf_cnt_sel_8_hart_8_re = addr_hit[24] & reg_re & !reg_error; - assign hart_select_1_we = addr_hit[17] & reg_we & !reg_error; - assign hart_select_1_wd = reg_wdata[9:0]; + assign perf_cnt_sel_8_metric_8_we = addr_hit[24] & reg_we & !reg_error; + assign perf_cnt_sel_8_metric_8_wd = reg_wdata[31:16]; + assign perf_cnt_sel_8_metric_8_re = addr_hit[24] & reg_re & !reg_error; - assign hart_select_2_we = addr_hit[18] & reg_we & !reg_error; - assign hart_select_2_wd = reg_wdata[9:0]; + assign perf_cnt_sel_9_hart_9_we = addr_hit[25] & reg_we & !reg_error; + assign perf_cnt_sel_9_hart_9_wd = reg_wdata[15:0]; + assign perf_cnt_sel_9_hart_9_re = addr_hit[25] & reg_re & !reg_error; - assign hart_select_3_we = addr_hit[19] & reg_we & !reg_error; - assign hart_select_3_wd = reg_wdata[9:0]; + assign perf_cnt_sel_9_metric_9_we = addr_hit[25] & reg_we & !reg_error; + assign perf_cnt_sel_9_metric_9_wd = reg_wdata[31:16]; + assign perf_cnt_sel_9_metric_9_re = addr_hit[25] & reg_re & !reg_error; - assign hart_select_4_we = addr_hit[20] & reg_we & !reg_error; - assign hart_select_4_wd = reg_wdata[9:0]; + assign perf_cnt_sel_10_hart_10_we = addr_hit[26] & reg_we & !reg_error; + assign perf_cnt_sel_10_hart_10_wd = reg_wdata[15:0]; + assign perf_cnt_sel_10_hart_10_re = addr_hit[26] & reg_re & !reg_error; - assign hart_select_5_we = addr_hit[21] & reg_we & !reg_error; - assign hart_select_5_wd = reg_wdata[9:0]; + assign perf_cnt_sel_10_metric_10_we = addr_hit[26] & reg_we & !reg_error; + assign perf_cnt_sel_10_metric_10_wd = reg_wdata[31:16]; + assign perf_cnt_sel_10_metric_10_re = addr_hit[26] & reg_re & !reg_error; - assign hart_select_6_we = addr_hit[22] & reg_we & !reg_error; - assign hart_select_6_wd = reg_wdata[9:0]; + assign perf_cnt_sel_11_hart_11_we = addr_hit[27] & reg_we & !reg_error; + assign perf_cnt_sel_11_hart_11_wd = reg_wdata[15:0]; + assign perf_cnt_sel_11_hart_11_re = addr_hit[27] & reg_re & !reg_error; - assign hart_select_7_we = addr_hit[23] & reg_we & !reg_error; - assign hart_select_7_wd = reg_wdata[9:0]; + assign perf_cnt_sel_11_metric_11_we = addr_hit[27] & reg_we & !reg_error; + assign perf_cnt_sel_11_metric_11_wd = reg_wdata[31:16]; + assign perf_cnt_sel_11_metric_11_re = addr_hit[27] & reg_re & !reg_error; - assign hart_select_8_we = addr_hit[24] & reg_we & !reg_error; - assign hart_select_8_wd = reg_wdata[9:0]; + assign perf_cnt_sel_12_hart_12_we = addr_hit[28] & reg_we & !reg_error; + assign perf_cnt_sel_12_hart_12_wd = reg_wdata[15:0]; + assign perf_cnt_sel_12_hart_12_re = addr_hit[28] & reg_re & !reg_error; - assign hart_select_9_we = addr_hit[25] & reg_we & !reg_error; - assign hart_select_9_wd = reg_wdata[9:0]; + assign perf_cnt_sel_12_metric_12_we = addr_hit[28] & reg_we & !reg_error; + assign perf_cnt_sel_12_metric_12_wd = reg_wdata[31:16]; + assign perf_cnt_sel_12_metric_12_re = addr_hit[28] & reg_re & !reg_error; - assign hart_select_10_we = addr_hit[26] & reg_we & !reg_error; - assign hart_select_10_wd = reg_wdata[9:0]; + assign perf_cnt_sel_13_hart_13_we = addr_hit[29] & reg_we & !reg_error; + assign perf_cnt_sel_13_hart_13_wd = reg_wdata[15:0]; + assign perf_cnt_sel_13_hart_13_re = addr_hit[29] & reg_re & !reg_error; - assign hart_select_11_we = addr_hit[27] & reg_we & !reg_error; - assign hart_select_11_wd = reg_wdata[9:0]; + assign perf_cnt_sel_13_metric_13_we = addr_hit[29] & reg_we & !reg_error; + assign perf_cnt_sel_13_metric_13_wd = reg_wdata[31:16]; + assign perf_cnt_sel_13_metric_13_re = addr_hit[29] & reg_re & !reg_error; - assign hart_select_12_we = addr_hit[28] & reg_we & !reg_error; - assign hart_select_12_wd = reg_wdata[9:0]; + assign perf_cnt_sel_14_hart_14_we = addr_hit[30] & reg_we & !reg_error; + assign perf_cnt_sel_14_hart_14_wd = reg_wdata[15:0]; + assign perf_cnt_sel_14_hart_14_re = addr_hit[30] & reg_re & !reg_error; - assign hart_select_13_we = addr_hit[29] & reg_we & !reg_error; - assign hart_select_13_wd = reg_wdata[9:0]; + assign perf_cnt_sel_14_metric_14_we = addr_hit[30] & reg_we & !reg_error; + assign perf_cnt_sel_14_metric_14_wd = reg_wdata[31:16]; + assign perf_cnt_sel_14_metric_14_re = addr_hit[30] & reg_re & !reg_error; - assign hart_select_14_we = addr_hit[30] & reg_we & !reg_error; - assign hart_select_14_wd = reg_wdata[9:0]; + assign perf_cnt_sel_15_hart_15_we = addr_hit[31] & reg_we & !reg_error; + assign perf_cnt_sel_15_hart_15_wd = reg_wdata[15:0]; + assign perf_cnt_sel_15_hart_15_re = addr_hit[31] & reg_re & !reg_error; - assign hart_select_15_we = addr_hit[31] & reg_we & !reg_error; - assign hart_select_15_wd = reg_wdata[9:0]; + assign perf_cnt_sel_15_metric_15_we = addr_hit[31] & reg_we & !reg_error; + assign perf_cnt_sel_15_metric_15_wd = reg_wdata[31:16]; + assign perf_cnt_sel_15_metric_15_re = addr_hit[31] & reg_re & !reg_error; - assign perf_counter_0_we = addr_hit[32] & reg_we & !reg_error; - assign perf_counter_0_wd = reg_wdata[47:0]; - assign perf_counter_0_re = addr_hit[32] & reg_re & !reg_error; + assign perf_cnt_0_we = addr_hit[32] & reg_we & !reg_error; + assign perf_cnt_0_wd = reg_wdata[47:0]; + assign perf_cnt_0_re = addr_hit[32] & reg_re & !reg_error; - assign perf_counter_1_we = addr_hit[33] & reg_we & !reg_error; - assign perf_counter_1_wd = reg_wdata[47:0]; - assign perf_counter_1_re = addr_hit[33] & reg_re & !reg_error; + assign perf_cnt_1_we = addr_hit[33] & reg_we & !reg_error; + assign perf_cnt_1_wd = reg_wdata[47:0]; + assign perf_cnt_1_re = addr_hit[33] & reg_re & !reg_error; - assign perf_counter_2_we = addr_hit[34] & reg_we & !reg_error; - assign perf_counter_2_wd = reg_wdata[47:0]; - assign perf_counter_2_re = addr_hit[34] & reg_re & !reg_error; + assign perf_cnt_2_we = addr_hit[34] & reg_we & !reg_error; + assign perf_cnt_2_wd = reg_wdata[47:0]; + assign perf_cnt_2_re = addr_hit[34] & reg_re & !reg_error; - assign perf_counter_3_we = addr_hit[35] & reg_we & !reg_error; - assign perf_counter_3_wd = reg_wdata[47:0]; - assign perf_counter_3_re = addr_hit[35] & reg_re & !reg_error; + assign perf_cnt_3_we = addr_hit[35] & reg_we & !reg_error; + assign perf_cnt_3_wd = reg_wdata[47:0]; + assign perf_cnt_3_re = addr_hit[35] & reg_re & !reg_error; - assign perf_counter_4_we = addr_hit[36] & reg_we & !reg_error; - assign perf_counter_4_wd = reg_wdata[47:0]; - assign perf_counter_4_re = addr_hit[36] & reg_re & !reg_error; + assign perf_cnt_4_we = addr_hit[36] & reg_we & !reg_error; + assign perf_cnt_4_wd = reg_wdata[47:0]; + assign perf_cnt_4_re = addr_hit[36] & reg_re & !reg_error; - assign perf_counter_5_we = addr_hit[37] & reg_we & !reg_error; - assign perf_counter_5_wd = reg_wdata[47:0]; - assign perf_counter_5_re = addr_hit[37] & reg_re & !reg_error; + assign perf_cnt_5_we = addr_hit[37] & reg_we & !reg_error; + assign perf_cnt_5_wd = reg_wdata[47:0]; + assign perf_cnt_5_re = addr_hit[37] & reg_re & !reg_error; - assign perf_counter_6_we = addr_hit[38] & reg_we & !reg_error; - assign perf_counter_6_wd = reg_wdata[47:0]; - assign perf_counter_6_re = addr_hit[38] & reg_re & !reg_error; + assign perf_cnt_6_we = addr_hit[38] & reg_we & !reg_error; + assign perf_cnt_6_wd = reg_wdata[47:0]; + assign perf_cnt_6_re = addr_hit[38] & reg_re & !reg_error; - assign perf_counter_7_we = addr_hit[39] & reg_we & !reg_error; - assign perf_counter_7_wd = reg_wdata[47:0]; - assign perf_counter_7_re = addr_hit[39] & reg_re & !reg_error; + assign perf_cnt_7_we = addr_hit[39] & reg_we & !reg_error; + assign perf_cnt_7_wd = reg_wdata[47:0]; + assign perf_cnt_7_re = addr_hit[39] & reg_re & !reg_error; - assign perf_counter_8_we = addr_hit[40] & reg_we & !reg_error; - assign perf_counter_8_wd = reg_wdata[47:0]; - assign perf_counter_8_re = addr_hit[40] & reg_re & !reg_error; + assign perf_cnt_8_we = addr_hit[40] & reg_we & !reg_error; + assign perf_cnt_8_wd = reg_wdata[47:0]; + assign perf_cnt_8_re = addr_hit[40] & reg_re & !reg_error; - assign perf_counter_9_we = addr_hit[41] & reg_we & !reg_error; - assign perf_counter_9_wd = reg_wdata[47:0]; - assign perf_counter_9_re = addr_hit[41] & reg_re & !reg_error; + assign perf_cnt_9_we = addr_hit[41] & reg_we & !reg_error; + assign perf_cnt_9_wd = reg_wdata[47:0]; + assign perf_cnt_9_re = addr_hit[41] & reg_re & !reg_error; - assign perf_counter_10_we = addr_hit[42] & reg_we & !reg_error; - assign perf_counter_10_wd = reg_wdata[47:0]; - assign perf_counter_10_re = addr_hit[42] & reg_re & !reg_error; + assign perf_cnt_10_we = addr_hit[42] & reg_we & !reg_error; + assign perf_cnt_10_wd = reg_wdata[47:0]; + assign perf_cnt_10_re = addr_hit[42] & reg_re & !reg_error; - assign perf_counter_11_we = addr_hit[43] & reg_we & !reg_error; - assign perf_counter_11_wd = reg_wdata[47:0]; - assign perf_counter_11_re = addr_hit[43] & reg_re & !reg_error; + assign perf_cnt_11_we = addr_hit[43] & reg_we & !reg_error; + assign perf_cnt_11_wd = reg_wdata[47:0]; + assign perf_cnt_11_re = addr_hit[43] & reg_re & !reg_error; - assign perf_counter_12_we = addr_hit[44] & reg_we & !reg_error; - assign perf_counter_12_wd = reg_wdata[47:0]; - assign perf_counter_12_re = addr_hit[44] & reg_re & !reg_error; + assign perf_cnt_12_we = addr_hit[44] & reg_we & !reg_error; + assign perf_cnt_12_wd = reg_wdata[47:0]; + assign perf_cnt_12_re = addr_hit[44] & reg_re & !reg_error; - assign perf_counter_13_we = addr_hit[45] & reg_we & !reg_error; - assign perf_counter_13_wd = reg_wdata[47:0]; - assign perf_counter_13_re = addr_hit[45] & reg_re & !reg_error; + assign perf_cnt_13_we = addr_hit[45] & reg_we & !reg_error; + assign perf_cnt_13_wd = reg_wdata[47:0]; + assign perf_cnt_13_re = addr_hit[45] & reg_re & !reg_error; - assign perf_counter_14_we = addr_hit[46] & reg_we & !reg_error; - assign perf_counter_14_wd = reg_wdata[47:0]; - assign perf_counter_14_re = addr_hit[46] & reg_re & !reg_error; + assign perf_cnt_14_we = addr_hit[46] & reg_we & !reg_error; + assign perf_cnt_14_wd = reg_wdata[47:0]; + assign perf_cnt_14_re = addr_hit[46] & reg_re & !reg_error; - assign perf_counter_15_we = addr_hit[47] & reg_we & !reg_error; - assign perf_counter_15_wd = reg_wdata[47:0]; - assign perf_counter_15_re = addr_hit[47] & reg_re & !reg_error; + assign perf_cnt_15_we = addr_hit[47] & reg_we & !reg_error; + assign perf_cnt_15_wd = reg_wdata[47:0]; + assign perf_cnt_15_re = addr_hit[47] & reg_re & !reg_error; assign cl_clint_set_we = addr_hit[48] & reg_we & !reg_error; assign cl_clint_set_wd = reg_wdata[31:0]; @@ -17114,9 +1958,7 @@ module snitch_cluster_peripheral_reg_top #( assign cl_clint_clear_we = addr_hit[49] & reg_we & !reg_error; assign cl_clint_clear_wd = reg_wdata[31:0]; - assign hw_barrier_re = addr_hit[50] & reg_re & !reg_error; - - assign icache_prefetch_enable_we = addr_hit[51] & reg_we & !reg_error; + assign icache_prefetch_enable_we = addr_hit[50] & reg_we & !reg_error; assign icache_prefetch_enable_wd = reg_wdata[0]; // Read data return @@ -17124,675 +1966,211 @@ module snitch_cluster_peripheral_reg_top #( reg_rdata_next = '0; unique case (1'b1) addr_hit[0]: begin - reg_rdata_next[0] = perf_counter_enable_0_cycle_0_qs; - reg_rdata_next[1] = perf_counter_enable_0_tcdm_accessed_0_qs; - reg_rdata_next[2] = perf_counter_enable_0_tcdm_congested_0_qs; - reg_rdata_next[3] = perf_counter_enable_0_issue_fpu_0_qs; - reg_rdata_next[4] = perf_counter_enable_0_issue_fpu_seq_0_qs; - reg_rdata_next[5] = perf_counter_enable_0_issue_core_to_fpu_0_qs; - reg_rdata_next[6] = perf_counter_enable_0_retired_instr_0_qs; - reg_rdata_next[7] = perf_counter_enable_0_retired_load_0_qs; - reg_rdata_next[8] = perf_counter_enable_0_retired_i_0_qs; - reg_rdata_next[9] = perf_counter_enable_0_retired_acc_0_qs; - reg_rdata_next[10] = perf_counter_enable_0_dma_aw_stall_0_qs; - reg_rdata_next[11] = perf_counter_enable_0_dma_ar_stall_0_qs; - reg_rdata_next[12] = perf_counter_enable_0_dma_r_stall_0_qs; - reg_rdata_next[13] = perf_counter_enable_0_dma_w_stall_0_qs; - reg_rdata_next[14] = perf_counter_enable_0_dma_buf_w_stall_0_qs; - reg_rdata_next[15] = perf_counter_enable_0_dma_buf_r_stall_0_qs; - reg_rdata_next[16] = perf_counter_enable_0_dma_aw_done_0_qs; - reg_rdata_next[17] = perf_counter_enable_0_dma_aw_bw_0_qs; - reg_rdata_next[18] = perf_counter_enable_0_dma_ar_done_0_qs; - reg_rdata_next[19] = perf_counter_enable_0_dma_ar_bw_0_qs; - reg_rdata_next[20] = perf_counter_enable_0_dma_r_done_0_qs; - reg_rdata_next[21] = perf_counter_enable_0_dma_r_bw_0_qs; - reg_rdata_next[22] = perf_counter_enable_0_dma_w_done_0_qs; - reg_rdata_next[23] = perf_counter_enable_0_dma_w_bw_0_qs; - reg_rdata_next[24] = perf_counter_enable_0_dma_b_done_0_qs; - reg_rdata_next[25] = perf_counter_enable_0_dma_busy_0_qs; - reg_rdata_next[26] = perf_counter_enable_0_icache_miss_0_qs; - reg_rdata_next[27] = perf_counter_enable_0_icache_hit_0_qs; - reg_rdata_next[28] = perf_counter_enable_0_icache_prefetch_0_qs; - reg_rdata_next[29] = perf_counter_enable_0_icache_double_hit_0_qs; - reg_rdata_next[30] = perf_counter_enable_0_icache_stall_0_qs; + reg_rdata_next[0] = perf_cnt_en_0_qs; end addr_hit[1]: begin - reg_rdata_next[0] = perf_counter_enable_1_cycle_1_qs; - reg_rdata_next[1] = perf_counter_enable_1_tcdm_accessed_1_qs; - reg_rdata_next[2] = perf_counter_enable_1_tcdm_congested_1_qs; - reg_rdata_next[3] = perf_counter_enable_1_issue_fpu_1_qs; - reg_rdata_next[4] = perf_counter_enable_1_issue_fpu_seq_1_qs; - reg_rdata_next[5] = perf_counter_enable_1_issue_core_to_fpu_1_qs; - reg_rdata_next[6] = perf_counter_enable_1_retired_instr_1_qs; - reg_rdata_next[7] = perf_counter_enable_1_retired_load_1_qs; - reg_rdata_next[8] = perf_counter_enable_1_retired_i_1_qs; - reg_rdata_next[9] = perf_counter_enable_1_retired_acc_1_qs; - reg_rdata_next[10] = perf_counter_enable_1_dma_aw_stall_1_qs; - reg_rdata_next[11] = perf_counter_enable_1_dma_ar_stall_1_qs; - reg_rdata_next[12] = perf_counter_enable_1_dma_r_stall_1_qs; - reg_rdata_next[13] = perf_counter_enable_1_dma_w_stall_1_qs; - reg_rdata_next[14] = perf_counter_enable_1_dma_buf_w_stall_1_qs; - reg_rdata_next[15] = perf_counter_enable_1_dma_buf_r_stall_1_qs; - reg_rdata_next[16] = perf_counter_enable_1_dma_aw_done_1_qs; - reg_rdata_next[17] = perf_counter_enable_1_dma_aw_bw_1_qs; - reg_rdata_next[18] = perf_counter_enable_1_dma_ar_done_1_qs; - reg_rdata_next[19] = perf_counter_enable_1_dma_ar_bw_1_qs; - reg_rdata_next[20] = perf_counter_enable_1_dma_r_done_1_qs; - reg_rdata_next[21] = perf_counter_enable_1_dma_r_bw_1_qs; - reg_rdata_next[22] = perf_counter_enable_1_dma_w_done_1_qs; - reg_rdata_next[23] = perf_counter_enable_1_dma_w_bw_1_qs; - reg_rdata_next[24] = perf_counter_enable_1_dma_b_done_1_qs; - reg_rdata_next[25] = perf_counter_enable_1_dma_busy_1_qs; - reg_rdata_next[26] = perf_counter_enable_1_icache_miss_1_qs; - reg_rdata_next[27] = perf_counter_enable_1_icache_hit_1_qs; - reg_rdata_next[28] = perf_counter_enable_1_icache_prefetch_1_qs; - reg_rdata_next[29] = perf_counter_enable_1_icache_double_hit_1_qs; - reg_rdata_next[30] = perf_counter_enable_1_icache_stall_1_qs; + reg_rdata_next[0] = perf_cnt_en_1_qs; end addr_hit[2]: begin - reg_rdata_next[0] = perf_counter_enable_2_cycle_2_qs; - reg_rdata_next[1] = perf_counter_enable_2_tcdm_accessed_2_qs; - reg_rdata_next[2] = perf_counter_enable_2_tcdm_congested_2_qs; - reg_rdata_next[3] = perf_counter_enable_2_issue_fpu_2_qs; - reg_rdata_next[4] = perf_counter_enable_2_issue_fpu_seq_2_qs; - reg_rdata_next[5] = perf_counter_enable_2_issue_core_to_fpu_2_qs; - reg_rdata_next[6] = perf_counter_enable_2_retired_instr_2_qs; - reg_rdata_next[7] = perf_counter_enable_2_retired_load_2_qs; - reg_rdata_next[8] = perf_counter_enable_2_retired_i_2_qs; - reg_rdata_next[9] = perf_counter_enable_2_retired_acc_2_qs; - reg_rdata_next[10] = perf_counter_enable_2_dma_aw_stall_2_qs; - reg_rdata_next[11] = perf_counter_enable_2_dma_ar_stall_2_qs; - reg_rdata_next[12] = perf_counter_enable_2_dma_r_stall_2_qs; - reg_rdata_next[13] = perf_counter_enable_2_dma_w_stall_2_qs; - reg_rdata_next[14] = perf_counter_enable_2_dma_buf_w_stall_2_qs; - reg_rdata_next[15] = perf_counter_enable_2_dma_buf_r_stall_2_qs; - reg_rdata_next[16] = perf_counter_enable_2_dma_aw_done_2_qs; - reg_rdata_next[17] = perf_counter_enable_2_dma_aw_bw_2_qs; - reg_rdata_next[18] = perf_counter_enable_2_dma_ar_done_2_qs; - reg_rdata_next[19] = perf_counter_enable_2_dma_ar_bw_2_qs; - reg_rdata_next[20] = perf_counter_enable_2_dma_r_done_2_qs; - reg_rdata_next[21] = perf_counter_enable_2_dma_r_bw_2_qs; - reg_rdata_next[22] = perf_counter_enable_2_dma_w_done_2_qs; - reg_rdata_next[23] = perf_counter_enable_2_dma_w_bw_2_qs; - reg_rdata_next[24] = perf_counter_enable_2_dma_b_done_2_qs; - reg_rdata_next[25] = perf_counter_enable_2_dma_busy_2_qs; - reg_rdata_next[26] = perf_counter_enable_2_icache_miss_2_qs; - reg_rdata_next[27] = perf_counter_enable_2_icache_hit_2_qs; - reg_rdata_next[28] = perf_counter_enable_2_icache_prefetch_2_qs; - reg_rdata_next[29] = perf_counter_enable_2_icache_double_hit_2_qs; - reg_rdata_next[30] = perf_counter_enable_2_icache_stall_2_qs; + reg_rdata_next[0] = perf_cnt_en_2_qs; end addr_hit[3]: begin - reg_rdata_next[0] = perf_counter_enable_3_cycle_3_qs; - reg_rdata_next[1] = perf_counter_enable_3_tcdm_accessed_3_qs; - reg_rdata_next[2] = perf_counter_enable_3_tcdm_congested_3_qs; - reg_rdata_next[3] = perf_counter_enable_3_issue_fpu_3_qs; - reg_rdata_next[4] = perf_counter_enable_3_issue_fpu_seq_3_qs; - reg_rdata_next[5] = perf_counter_enable_3_issue_core_to_fpu_3_qs; - reg_rdata_next[6] = perf_counter_enable_3_retired_instr_3_qs; - reg_rdata_next[7] = perf_counter_enable_3_retired_load_3_qs; - reg_rdata_next[8] = perf_counter_enable_3_retired_i_3_qs; - reg_rdata_next[9] = perf_counter_enable_3_retired_acc_3_qs; - reg_rdata_next[10] = perf_counter_enable_3_dma_aw_stall_3_qs; - reg_rdata_next[11] = perf_counter_enable_3_dma_ar_stall_3_qs; - reg_rdata_next[12] = perf_counter_enable_3_dma_r_stall_3_qs; - reg_rdata_next[13] = perf_counter_enable_3_dma_w_stall_3_qs; - reg_rdata_next[14] = perf_counter_enable_3_dma_buf_w_stall_3_qs; - reg_rdata_next[15] = perf_counter_enable_3_dma_buf_r_stall_3_qs; - reg_rdata_next[16] = perf_counter_enable_3_dma_aw_done_3_qs; - reg_rdata_next[17] = perf_counter_enable_3_dma_aw_bw_3_qs; - reg_rdata_next[18] = perf_counter_enable_3_dma_ar_done_3_qs; - reg_rdata_next[19] = perf_counter_enable_3_dma_ar_bw_3_qs; - reg_rdata_next[20] = perf_counter_enable_3_dma_r_done_3_qs; - reg_rdata_next[21] = perf_counter_enable_3_dma_r_bw_3_qs; - reg_rdata_next[22] = perf_counter_enable_3_dma_w_done_3_qs; - reg_rdata_next[23] = perf_counter_enable_3_dma_w_bw_3_qs; - reg_rdata_next[24] = perf_counter_enable_3_dma_b_done_3_qs; - reg_rdata_next[25] = perf_counter_enable_3_dma_busy_3_qs; - reg_rdata_next[26] = perf_counter_enable_3_icache_miss_3_qs; - reg_rdata_next[27] = perf_counter_enable_3_icache_hit_3_qs; - reg_rdata_next[28] = perf_counter_enable_3_icache_prefetch_3_qs; - reg_rdata_next[29] = perf_counter_enable_3_icache_double_hit_3_qs; - reg_rdata_next[30] = perf_counter_enable_3_icache_stall_3_qs; + reg_rdata_next[0] = perf_cnt_en_3_qs; end addr_hit[4]: begin - reg_rdata_next[0] = perf_counter_enable_4_cycle_4_qs; - reg_rdata_next[1] = perf_counter_enable_4_tcdm_accessed_4_qs; - reg_rdata_next[2] = perf_counter_enable_4_tcdm_congested_4_qs; - reg_rdata_next[3] = perf_counter_enable_4_issue_fpu_4_qs; - reg_rdata_next[4] = perf_counter_enable_4_issue_fpu_seq_4_qs; - reg_rdata_next[5] = perf_counter_enable_4_issue_core_to_fpu_4_qs; - reg_rdata_next[6] = perf_counter_enable_4_retired_instr_4_qs; - reg_rdata_next[7] = perf_counter_enable_4_retired_load_4_qs; - reg_rdata_next[8] = perf_counter_enable_4_retired_i_4_qs; - reg_rdata_next[9] = perf_counter_enable_4_retired_acc_4_qs; - reg_rdata_next[10] = perf_counter_enable_4_dma_aw_stall_4_qs; - reg_rdata_next[11] = perf_counter_enable_4_dma_ar_stall_4_qs; - reg_rdata_next[12] = perf_counter_enable_4_dma_r_stall_4_qs; - reg_rdata_next[13] = perf_counter_enable_4_dma_w_stall_4_qs; - reg_rdata_next[14] = perf_counter_enable_4_dma_buf_w_stall_4_qs; - reg_rdata_next[15] = perf_counter_enable_4_dma_buf_r_stall_4_qs; - reg_rdata_next[16] = perf_counter_enable_4_dma_aw_done_4_qs; - reg_rdata_next[17] = perf_counter_enable_4_dma_aw_bw_4_qs; - reg_rdata_next[18] = perf_counter_enable_4_dma_ar_done_4_qs; - reg_rdata_next[19] = perf_counter_enable_4_dma_ar_bw_4_qs; - reg_rdata_next[20] = perf_counter_enable_4_dma_r_done_4_qs; - reg_rdata_next[21] = perf_counter_enable_4_dma_r_bw_4_qs; - reg_rdata_next[22] = perf_counter_enable_4_dma_w_done_4_qs; - reg_rdata_next[23] = perf_counter_enable_4_dma_w_bw_4_qs; - reg_rdata_next[24] = perf_counter_enable_4_dma_b_done_4_qs; - reg_rdata_next[25] = perf_counter_enable_4_dma_busy_4_qs; - reg_rdata_next[26] = perf_counter_enable_4_icache_miss_4_qs; - reg_rdata_next[27] = perf_counter_enable_4_icache_hit_4_qs; - reg_rdata_next[28] = perf_counter_enable_4_icache_prefetch_4_qs; - reg_rdata_next[29] = perf_counter_enable_4_icache_double_hit_4_qs; - reg_rdata_next[30] = perf_counter_enable_4_icache_stall_4_qs; + reg_rdata_next[0] = perf_cnt_en_4_qs; end addr_hit[5]: begin - reg_rdata_next[0] = perf_counter_enable_5_cycle_5_qs; - reg_rdata_next[1] = perf_counter_enable_5_tcdm_accessed_5_qs; - reg_rdata_next[2] = perf_counter_enable_5_tcdm_congested_5_qs; - reg_rdata_next[3] = perf_counter_enable_5_issue_fpu_5_qs; - reg_rdata_next[4] = perf_counter_enable_5_issue_fpu_seq_5_qs; - reg_rdata_next[5] = perf_counter_enable_5_issue_core_to_fpu_5_qs; - reg_rdata_next[6] = perf_counter_enable_5_retired_instr_5_qs; - reg_rdata_next[7] = perf_counter_enable_5_retired_load_5_qs; - reg_rdata_next[8] = perf_counter_enable_5_retired_i_5_qs; - reg_rdata_next[9] = perf_counter_enable_5_retired_acc_5_qs; - reg_rdata_next[10] = perf_counter_enable_5_dma_aw_stall_5_qs; - reg_rdata_next[11] = perf_counter_enable_5_dma_ar_stall_5_qs; - reg_rdata_next[12] = perf_counter_enable_5_dma_r_stall_5_qs; - reg_rdata_next[13] = perf_counter_enable_5_dma_w_stall_5_qs; - reg_rdata_next[14] = perf_counter_enable_5_dma_buf_w_stall_5_qs; - reg_rdata_next[15] = perf_counter_enable_5_dma_buf_r_stall_5_qs; - reg_rdata_next[16] = perf_counter_enable_5_dma_aw_done_5_qs; - reg_rdata_next[17] = perf_counter_enable_5_dma_aw_bw_5_qs; - reg_rdata_next[18] = perf_counter_enable_5_dma_ar_done_5_qs; - reg_rdata_next[19] = perf_counter_enable_5_dma_ar_bw_5_qs; - reg_rdata_next[20] = perf_counter_enable_5_dma_r_done_5_qs; - reg_rdata_next[21] = perf_counter_enable_5_dma_r_bw_5_qs; - reg_rdata_next[22] = perf_counter_enable_5_dma_w_done_5_qs; - reg_rdata_next[23] = perf_counter_enable_5_dma_w_bw_5_qs; - reg_rdata_next[24] = perf_counter_enable_5_dma_b_done_5_qs; - reg_rdata_next[25] = perf_counter_enable_5_dma_busy_5_qs; - reg_rdata_next[26] = perf_counter_enable_5_icache_miss_5_qs; - reg_rdata_next[27] = perf_counter_enable_5_icache_hit_5_qs; - reg_rdata_next[28] = perf_counter_enable_5_icache_prefetch_5_qs; - reg_rdata_next[29] = perf_counter_enable_5_icache_double_hit_5_qs; - reg_rdata_next[30] = perf_counter_enable_5_icache_stall_5_qs; + reg_rdata_next[0] = perf_cnt_en_5_qs; end addr_hit[6]: begin - reg_rdata_next[0] = perf_counter_enable_6_cycle_6_qs; - reg_rdata_next[1] = perf_counter_enable_6_tcdm_accessed_6_qs; - reg_rdata_next[2] = perf_counter_enable_6_tcdm_congested_6_qs; - reg_rdata_next[3] = perf_counter_enable_6_issue_fpu_6_qs; - reg_rdata_next[4] = perf_counter_enable_6_issue_fpu_seq_6_qs; - reg_rdata_next[5] = perf_counter_enable_6_issue_core_to_fpu_6_qs; - reg_rdata_next[6] = perf_counter_enable_6_retired_instr_6_qs; - reg_rdata_next[7] = perf_counter_enable_6_retired_load_6_qs; - reg_rdata_next[8] = perf_counter_enable_6_retired_i_6_qs; - reg_rdata_next[9] = perf_counter_enable_6_retired_acc_6_qs; - reg_rdata_next[10] = perf_counter_enable_6_dma_aw_stall_6_qs; - reg_rdata_next[11] = perf_counter_enable_6_dma_ar_stall_6_qs; - reg_rdata_next[12] = perf_counter_enable_6_dma_r_stall_6_qs; - reg_rdata_next[13] = perf_counter_enable_6_dma_w_stall_6_qs; - reg_rdata_next[14] = perf_counter_enable_6_dma_buf_w_stall_6_qs; - reg_rdata_next[15] = perf_counter_enable_6_dma_buf_r_stall_6_qs; - reg_rdata_next[16] = perf_counter_enable_6_dma_aw_done_6_qs; - reg_rdata_next[17] = perf_counter_enable_6_dma_aw_bw_6_qs; - reg_rdata_next[18] = perf_counter_enable_6_dma_ar_done_6_qs; - reg_rdata_next[19] = perf_counter_enable_6_dma_ar_bw_6_qs; - reg_rdata_next[20] = perf_counter_enable_6_dma_r_done_6_qs; - reg_rdata_next[21] = perf_counter_enable_6_dma_r_bw_6_qs; - reg_rdata_next[22] = perf_counter_enable_6_dma_w_done_6_qs; - reg_rdata_next[23] = perf_counter_enable_6_dma_w_bw_6_qs; - reg_rdata_next[24] = perf_counter_enable_6_dma_b_done_6_qs; - reg_rdata_next[25] = perf_counter_enable_6_dma_busy_6_qs; - reg_rdata_next[26] = perf_counter_enable_6_icache_miss_6_qs; - reg_rdata_next[27] = perf_counter_enable_6_icache_hit_6_qs; - reg_rdata_next[28] = perf_counter_enable_6_icache_prefetch_6_qs; - reg_rdata_next[29] = perf_counter_enable_6_icache_double_hit_6_qs; - reg_rdata_next[30] = perf_counter_enable_6_icache_stall_6_qs; + reg_rdata_next[0] = perf_cnt_en_6_qs; end addr_hit[7]: begin - reg_rdata_next[0] = perf_counter_enable_7_cycle_7_qs; - reg_rdata_next[1] = perf_counter_enable_7_tcdm_accessed_7_qs; - reg_rdata_next[2] = perf_counter_enable_7_tcdm_congested_7_qs; - reg_rdata_next[3] = perf_counter_enable_7_issue_fpu_7_qs; - reg_rdata_next[4] = perf_counter_enable_7_issue_fpu_seq_7_qs; - reg_rdata_next[5] = perf_counter_enable_7_issue_core_to_fpu_7_qs; - reg_rdata_next[6] = perf_counter_enable_7_retired_instr_7_qs; - reg_rdata_next[7] = perf_counter_enable_7_retired_load_7_qs; - reg_rdata_next[8] = perf_counter_enable_7_retired_i_7_qs; - reg_rdata_next[9] = perf_counter_enable_7_retired_acc_7_qs; - reg_rdata_next[10] = perf_counter_enable_7_dma_aw_stall_7_qs; - reg_rdata_next[11] = perf_counter_enable_7_dma_ar_stall_7_qs; - reg_rdata_next[12] = perf_counter_enable_7_dma_r_stall_7_qs; - reg_rdata_next[13] = perf_counter_enable_7_dma_w_stall_7_qs; - reg_rdata_next[14] = perf_counter_enable_7_dma_buf_w_stall_7_qs; - reg_rdata_next[15] = perf_counter_enable_7_dma_buf_r_stall_7_qs; - reg_rdata_next[16] = perf_counter_enable_7_dma_aw_done_7_qs; - reg_rdata_next[17] = perf_counter_enable_7_dma_aw_bw_7_qs; - reg_rdata_next[18] = perf_counter_enable_7_dma_ar_done_7_qs; - reg_rdata_next[19] = perf_counter_enable_7_dma_ar_bw_7_qs; - reg_rdata_next[20] = perf_counter_enable_7_dma_r_done_7_qs; - reg_rdata_next[21] = perf_counter_enable_7_dma_r_bw_7_qs; - reg_rdata_next[22] = perf_counter_enable_7_dma_w_done_7_qs; - reg_rdata_next[23] = perf_counter_enable_7_dma_w_bw_7_qs; - reg_rdata_next[24] = perf_counter_enable_7_dma_b_done_7_qs; - reg_rdata_next[25] = perf_counter_enable_7_dma_busy_7_qs; - reg_rdata_next[26] = perf_counter_enable_7_icache_miss_7_qs; - reg_rdata_next[27] = perf_counter_enable_7_icache_hit_7_qs; - reg_rdata_next[28] = perf_counter_enable_7_icache_prefetch_7_qs; - reg_rdata_next[29] = perf_counter_enable_7_icache_double_hit_7_qs; - reg_rdata_next[30] = perf_counter_enable_7_icache_stall_7_qs; + reg_rdata_next[0] = perf_cnt_en_7_qs; end addr_hit[8]: begin - reg_rdata_next[0] = perf_counter_enable_8_cycle_8_qs; - reg_rdata_next[1] = perf_counter_enable_8_tcdm_accessed_8_qs; - reg_rdata_next[2] = perf_counter_enable_8_tcdm_congested_8_qs; - reg_rdata_next[3] = perf_counter_enable_8_issue_fpu_8_qs; - reg_rdata_next[4] = perf_counter_enable_8_issue_fpu_seq_8_qs; - reg_rdata_next[5] = perf_counter_enable_8_issue_core_to_fpu_8_qs; - reg_rdata_next[6] = perf_counter_enable_8_retired_instr_8_qs; - reg_rdata_next[7] = perf_counter_enable_8_retired_load_8_qs; - reg_rdata_next[8] = perf_counter_enable_8_retired_i_8_qs; - reg_rdata_next[9] = perf_counter_enable_8_retired_acc_8_qs; - reg_rdata_next[10] = perf_counter_enable_8_dma_aw_stall_8_qs; - reg_rdata_next[11] = perf_counter_enable_8_dma_ar_stall_8_qs; - reg_rdata_next[12] = perf_counter_enable_8_dma_r_stall_8_qs; - reg_rdata_next[13] = perf_counter_enable_8_dma_w_stall_8_qs; - reg_rdata_next[14] = perf_counter_enable_8_dma_buf_w_stall_8_qs; - reg_rdata_next[15] = perf_counter_enable_8_dma_buf_r_stall_8_qs; - reg_rdata_next[16] = perf_counter_enable_8_dma_aw_done_8_qs; - reg_rdata_next[17] = perf_counter_enable_8_dma_aw_bw_8_qs; - reg_rdata_next[18] = perf_counter_enable_8_dma_ar_done_8_qs; - reg_rdata_next[19] = perf_counter_enable_8_dma_ar_bw_8_qs; - reg_rdata_next[20] = perf_counter_enable_8_dma_r_done_8_qs; - reg_rdata_next[21] = perf_counter_enable_8_dma_r_bw_8_qs; - reg_rdata_next[22] = perf_counter_enable_8_dma_w_done_8_qs; - reg_rdata_next[23] = perf_counter_enable_8_dma_w_bw_8_qs; - reg_rdata_next[24] = perf_counter_enable_8_dma_b_done_8_qs; - reg_rdata_next[25] = perf_counter_enable_8_dma_busy_8_qs; - reg_rdata_next[26] = perf_counter_enable_8_icache_miss_8_qs; - reg_rdata_next[27] = perf_counter_enable_8_icache_hit_8_qs; - reg_rdata_next[28] = perf_counter_enable_8_icache_prefetch_8_qs; - reg_rdata_next[29] = perf_counter_enable_8_icache_double_hit_8_qs; - reg_rdata_next[30] = perf_counter_enable_8_icache_stall_8_qs; + reg_rdata_next[0] = perf_cnt_en_8_qs; end addr_hit[9]: begin - reg_rdata_next[0] = perf_counter_enable_9_cycle_9_qs; - reg_rdata_next[1] = perf_counter_enable_9_tcdm_accessed_9_qs; - reg_rdata_next[2] = perf_counter_enable_9_tcdm_congested_9_qs; - reg_rdata_next[3] = perf_counter_enable_9_issue_fpu_9_qs; - reg_rdata_next[4] = perf_counter_enable_9_issue_fpu_seq_9_qs; - reg_rdata_next[5] = perf_counter_enable_9_issue_core_to_fpu_9_qs; - reg_rdata_next[6] = perf_counter_enable_9_retired_instr_9_qs; - reg_rdata_next[7] = perf_counter_enable_9_retired_load_9_qs; - reg_rdata_next[8] = perf_counter_enable_9_retired_i_9_qs; - reg_rdata_next[9] = perf_counter_enable_9_retired_acc_9_qs; - reg_rdata_next[10] = perf_counter_enable_9_dma_aw_stall_9_qs; - reg_rdata_next[11] = perf_counter_enable_9_dma_ar_stall_9_qs; - reg_rdata_next[12] = perf_counter_enable_9_dma_r_stall_9_qs; - reg_rdata_next[13] = perf_counter_enable_9_dma_w_stall_9_qs; - reg_rdata_next[14] = perf_counter_enable_9_dma_buf_w_stall_9_qs; - reg_rdata_next[15] = perf_counter_enable_9_dma_buf_r_stall_9_qs; - reg_rdata_next[16] = perf_counter_enable_9_dma_aw_done_9_qs; - reg_rdata_next[17] = perf_counter_enable_9_dma_aw_bw_9_qs; - reg_rdata_next[18] = perf_counter_enable_9_dma_ar_done_9_qs; - reg_rdata_next[19] = perf_counter_enable_9_dma_ar_bw_9_qs; - reg_rdata_next[20] = perf_counter_enable_9_dma_r_done_9_qs; - reg_rdata_next[21] = perf_counter_enable_9_dma_r_bw_9_qs; - reg_rdata_next[22] = perf_counter_enable_9_dma_w_done_9_qs; - reg_rdata_next[23] = perf_counter_enable_9_dma_w_bw_9_qs; - reg_rdata_next[24] = perf_counter_enable_9_dma_b_done_9_qs; - reg_rdata_next[25] = perf_counter_enable_9_dma_busy_9_qs; - reg_rdata_next[26] = perf_counter_enable_9_icache_miss_9_qs; - reg_rdata_next[27] = perf_counter_enable_9_icache_hit_9_qs; - reg_rdata_next[28] = perf_counter_enable_9_icache_prefetch_9_qs; - reg_rdata_next[29] = perf_counter_enable_9_icache_double_hit_9_qs; - reg_rdata_next[30] = perf_counter_enable_9_icache_stall_9_qs; + reg_rdata_next[0] = perf_cnt_en_9_qs; end addr_hit[10]: begin - reg_rdata_next[0] = perf_counter_enable_10_cycle_10_qs; - reg_rdata_next[1] = perf_counter_enable_10_tcdm_accessed_10_qs; - reg_rdata_next[2] = perf_counter_enable_10_tcdm_congested_10_qs; - reg_rdata_next[3] = perf_counter_enable_10_issue_fpu_10_qs; - reg_rdata_next[4] = perf_counter_enable_10_issue_fpu_seq_10_qs; - reg_rdata_next[5] = perf_counter_enable_10_issue_core_to_fpu_10_qs; - reg_rdata_next[6] = perf_counter_enable_10_retired_instr_10_qs; - reg_rdata_next[7] = perf_counter_enable_10_retired_load_10_qs; - reg_rdata_next[8] = perf_counter_enable_10_retired_i_10_qs; - reg_rdata_next[9] = perf_counter_enable_10_retired_acc_10_qs; - reg_rdata_next[10] = perf_counter_enable_10_dma_aw_stall_10_qs; - reg_rdata_next[11] = perf_counter_enable_10_dma_ar_stall_10_qs; - reg_rdata_next[12] = perf_counter_enable_10_dma_r_stall_10_qs; - reg_rdata_next[13] = perf_counter_enable_10_dma_w_stall_10_qs; - reg_rdata_next[14] = perf_counter_enable_10_dma_buf_w_stall_10_qs; - reg_rdata_next[15] = perf_counter_enable_10_dma_buf_r_stall_10_qs; - reg_rdata_next[16] = perf_counter_enable_10_dma_aw_done_10_qs; - reg_rdata_next[17] = perf_counter_enable_10_dma_aw_bw_10_qs; - reg_rdata_next[18] = perf_counter_enable_10_dma_ar_done_10_qs; - reg_rdata_next[19] = perf_counter_enable_10_dma_ar_bw_10_qs; - reg_rdata_next[20] = perf_counter_enable_10_dma_r_done_10_qs; - reg_rdata_next[21] = perf_counter_enable_10_dma_r_bw_10_qs; - reg_rdata_next[22] = perf_counter_enable_10_dma_w_done_10_qs; - reg_rdata_next[23] = perf_counter_enable_10_dma_w_bw_10_qs; - reg_rdata_next[24] = perf_counter_enable_10_dma_b_done_10_qs; - reg_rdata_next[25] = perf_counter_enable_10_dma_busy_10_qs; - reg_rdata_next[26] = perf_counter_enable_10_icache_miss_10_qs; - reg_rdata_next[27] = perf_counter_enable_10_icache_hit_10_qs; - reg_rdata_next[28] = perf_counter_enable_10_icache_prefetch_10_qs; - reg_rdata_next[29] = perf_counter_enable_10_icache_double_hit_10_qs; - reg_rdata_next[30] = perf_counter_enable_10_icache_stall_10_qs; + reg_rdata_next[0] = perf_cnt_en_10_qs; end addr_hit[11]: begin - reg_rdata_next[0] = perf_counter_enable_11_cycle_11_qs; - reg_rdata_next[1] = perf_counter_enable_11_tcdm_accessed_11_qs; - reg_rdata_next[2] = perf_counter_enable_11_tcdm_congested_11_qs; - reg_rdata_next[3] = perf_counter_enable_11_issue_fpu_11_qs; - reg_rdata_next[4] = perf_counter_enable_11_issue_fpu_seq_11_qs; - reg_rdata_next[5] = perf_counter_enable_11_issue_core_to_fpu_11_qs; - reg_rdata_next[6] = perf_counter_enable_11_retired_instr_11_qs; - reg_rdata_next[7] = perf_counter_enable_11_retired_load_11_qs; - reg_rdata_next[8] = perf_counter_enable_11_retired_i_11_qs; - reg_rdata_next[9] = perf_counter_enable_11_retired_acc_11_qs; - reg_rdata_next[10] = perf_counter_enable_11_dma_aw_stall_11_qs; - reg_rdata_next[11] = perf_counter_enable_11_dma_ar_stall_11_qs; - reg_rdata_next[12] = perf_counter_enable_11_dma_r_stall_11_qs; - reg_rdata_next[13] = perf_counter_enable_11_dma_w_stall_11_qs; - reg_rdata_next[14] = perf_counter_enable_11_dma_buf_w_stall_11_qs; - reg_rdata_next[15] = perf_counter_enable_11_dma_buf_r_stall_11_qs; - reg_rdata_next[16] = perf_counter_enable_11_dma_aw_done_11_qs; - reg_rdata_next[17] = perf_counter_enable_11_dma_aw_bw_11_qs; - reg_rdata_next[18] = perf_counter_enable_11_dma_ar_done_11_qs; - reg_rdata_next[19] = perf_counter_enable_11_dma_ar_bw_11_qs; - reg_rdata_next[20] = perf_counter_enable_11_dma_r_done_11_qs; - reg_rdata_next[21] = perf_counter_enable_11_dma_r_bw_11_qs; - reg_rdata_next[22] = perf_counter_enable_11_dma_w_done_11_qs; - reg_rdata_next[23] = perf_counter_enable_11_dma_w_bw_11_qs; - reg_rdata_next[24] = perf_counter_enable_11_dma_b_done_11_qs; - reg_rdata_next[25] = perf_counter_enable_11_dma_busy_11_qs; - reg_rdata_next[26] = perf_counter_enable_11_icache_miss_11_qs; - reg_rdata_next[27] = perf_counter_enable_11_icache_hit_11_qs; - reg_rdata_next[28] = perf_counter_enable_11_icache_prefetch_11_qs; - reg_rdata_next[29] = perf_counter_enable_11_icache_double_hit_11_qs; - reg_rdata_next[30] = perf_counter_enable_11_icache_stall_11_qs; + reg_rdata_next[0] = perf_cnt_en_11_qs; end addr_hit[12]: begin - reg_rdata_next[0] = perf_counter_enable_12_cycle_12_qs; - reg_rdata_next[1] = perf_counter_enable_12_tcdm_accessed_12_qs; - reg_rdata_next[2] = perf_counter_enable_12_tcdm_congested_12_qs; - reg_rdata_next[3] = perf_counter_enable_12_issue_fpu_12_qs; - reg_rdata_next[4] = perf_counter_enable_12_issue_fpu_seq_12_qs; - reg_rdata_next[5] = perf_counter_enable_12_issue_core_to_fpu_12_qs; - reg_rdata_next[6] = perf_counter_enable_12_retired_instr_12_qs; - reg_rdata_next[7] = perf_counter_enable_12_retired_load_12_qs; - reg_rdata_next[8] = perf_counter_enable_12_retired_i_12_qs; - reg_rdata_next[9] = perf_counter_enable_12_retired_acc_12_qs; - reg_rdata_next[10] = perf_counter_enable_12_dma_aw_stall_12_qs; - reg_rdata_next[11] = perf_counter_enable_12_dma_ar_stall_12_qs; - reg_rdata_next[12] = perf_counter_enable_12_dma_r_stall_12_qs; - reg_rdata_next[13] = perf_counter_enable_12_dma_w_stall_12_qs; - reg_rdata_next[14] = perf_counter_enable_12_dma_buf_w_stall_12_qs; - reg_rdata_next[15] = perf_counter_enable_12_dma_buf_r_stall_12_qs; - reg_rdata_next[16] = perf_counter_enable_12_dma_aw_done_12_qs; - reg_rdata_next[17] = perf_counter_enable_12_dma_aw_bw_12_qs; - reg_rdata_next[18] = perf_counter_enable_12_dma_ar_done_12_qs; - reg_rdata_next[19] = perf_counter_enable_12_dma_ar_bw_12_qs; - reg_rdata_next[20] = perf_counter_enable_12_dma_r_done_12_qs; - reg_rdata_next[21] = perf_counter_enable_12_dma_r_bw_12_qs; - reg_rdata_next[22] = perf_counter_enable_12_dma_w_done_12_qs; - reg_rdata_next[23] = perf_counter_enable_12_dma_w_bw_12_qs; - reg_rdata_next[24] = perf_counter_enable_12_dma_b_done_12_qs; - reg_rdata_next[25] = perf_counter_enable_12_dma_busy_12_qs; - reg_rdata_next[26] = perf_counter_enable_12_icache_miss_12_qs; - reg_rdata_next[27] = perf_counter_enable_12_icache_hit_12_qs; - reg_rdata_next[28] = perf_counter_enable_12_icache_prefetch_12_qs; - reg_rdata_next[29] = perf_counter_enable_12_icache_double_hit_12_qs; - reg_rdata_next[30] = perf_counter_enable_12_icache_stall_12_qs; + reg_rdata_next[0] = perf_cnt_en_12_qs; end addr_hit[13]: begin - reg_rdata_next[0] = perf_counter_enable_13_cycle_13_qs; - reg_rdata_next[1] = perf_counter_enable_13_tcdm_accessed_13_qs; - reg_rdata_next[2] = perf_counter_enable_13_tcdm_congested_13_qs; - reg_rdata_next[3] = perf_counter_enable_13_issue_fpu_13_qs; - reg_rdata_next[4] = perf_counter_enable_13_issue_fpu_seq_13_qs; - reg_rdata_next[5] = perf_counter_enable_13_issue_core_to_fpu_13_qs; - reg_rdata_next[6] = perf_counter_enable_13_retired_instr_13_qs; - reg_rdata_next[7] = perf_counter_enable_13_retired_load_13_qs; - reg_rdata_next[8] = perf_counter_enable_13_retired_i_13_qs; - reg_rdata_next[9] = perf_counter_enable_13_retired_acc_13_qs; - reg_rdata_next[10] = perf_counter_enable_13_dma_aw_stall_13_qs; - reg_rdata_next[11] = perf_counter_enable_13_dma_ar_stall_13_qs; - reg_rdata_next[12] = perf_counter_enable_13_dma_r_stall_13_qs; - reg_rdata_next[13] = perf_counter_enable_13_dma_w_stall_13_qs; - reg_rdata_next[14] = perf_counter_enable_13_dma_buf_w_stall_13_qs; - reg_rdata_next[15] = perf_counter_enable_13_dma_buf_r_stall_13_qs; - reg_rdata_next[16] = perf_counter_enable_13_dma_aw_done_13_qs; - reg_rdata_next[17] = perf_counter_enable_13_dma_aw_bw_13_qs; - reg_rdata_next[18] = perf_counter_enable_13_dma_ar_done_13_qs; - reg_rdata_next[19] = perf_counter_enable_13_dma_ar_bw_13_qs; - reg_rdata_next[20] = perf_counter_enable_13_dma_r_done_13_qs; - reg_rdata_next[21] = perf_counter_enable_13_dma_r_bw_13_qs; - reg_rdata_next[22] = perf_counter_enable_13_dma_w_done_13_qs; - reg_rdata_next[23] = perf_counter_enable_13_dma_w_bw_13_qs; - reg_rdata_next[24] = perf_counter_enable_13_dma_b_done_13_qs; - reg_rdata_next[25] = perf_counter_enable_13_dma_busy_13_qs; - reg_rdata_next[26] = perf_counter_enable_13_icache_miss_13_qs; - reg_rdata_next[27] = perf_counter_enable_13_icache_hit_13_qs; - reg_rdata_next[28] = perf_counter_enable_13_icache_prefetch_13_qs; - reg_rdata_next[29] = perf_counter_enable_13_icache_double_hit_13_qs; - reg_rdata_next[30] = perf_counter_enable_13_icache_stall_13_qs; + reg_rdata_next[0] = perf_cnt_en_13_qs; end addr_hit[14]: begin - reg_rdata_next[0] = perf_counter_enable_14_cycle_14_qs; - reg_rdata_next[1] = perf_counter_enable_14_tcdm_accessed_14_qs; - reg_rdata_next[2] = perf_counter_enable_14_tcdm_congested_14_qs; - reg_rdata_next[3] = perf_counter_enable_14_issue_fpu_14_qs; - reg_rdata_next[4] = perf_counter_enable_14_issue_fpu_seq_14_qs; - reg_rdata_next[5] = perf_counter_enable_14_issue_core_to_fpu_14_qs; - reg_rdata_next[6] = perf_counter_enable_14_retired_instr_14_qs; - reg_rdata_next[7] = perf_counter_enable_14_retired_load_14_qs; - reg_rdata_next[8] = perf_counter_enable_14_retired_i_14_qs; - reg_rdata_next[9] = perf_counter_enable_14_retired_acc_14_qs; - reg_rdata_next[10] = perf_counter_enable_14_dma_aw_stall_14_qs; - reg_rdata_next[11] = perf_counter_enable_14_dma_ar_stall_14_qs; - reg_rdata_next[12] = perf_counter_enable_14_dma_r_stall_14_qs; - reg_rdata_next[13] = perf_counter_enable_14_dma_w_stall_14_qs; - reg_rdata_next[14] = perf_counter_enable_14_dma_buf_w_stall_14_qs; - reg_rdata_next[15] = perf_counter_enable_14_dma_buf_r_stall_14_qs; - reg_rdata_next[16] = perf_counter_enable_14_dma_aw_done_14_qs; - reg_rdata_next[17] = perf_counter_enable_14_dma_aw_bw_14_qs; - reg_rdata_next[18] = perf_counter_enable_14_dma_ar_done_14_qs; - reg_rdata_next[19] = perf_counter_enable_14_dma_ar_bw_14_qs; - reg_rdata_next[20] = perf_counter_enable_14_dma_r_done_14_qs; - reg_rdata_next[21] = perf_counter_enable_14_dma_r_bw_14_qs; - reg_rdata_next[22] = perf_counter_enable_14_dma_w_done_14_qs; - reg_rdata_next[23] = perf_counter_enable_14_dma_w_bw_14_qs; - reg_rdata_next[24] = perf_counter_enable_14_dma_b_done_14_qs; - reg_rdata_next[25] = perf_counter_enable_14_dma_busy_14_qs; - reg_rdata_next[26] = perf_counter_enable_14_icache_miss_14_qs; - reg_rdata_next[27] = perf_counter_enable_14_icache_hit_14_qs; - reg_rdata_next[28] = perf_counter_enable_14_icache_prefetch_14_qs; - reg_rdata_next[29] = perf_counter_enable_14_icache_double_hit_14_qs; - reg_rdata_next[30] = perf_counter_enable_14_icache_stall_14_qs; + reg_rdata_next[0] = perf_cnt_en_14_qs; end addr_hit[15]: begin - reg_rdata_next[0] = perf_counter_enable_15_cycle_15_qs; - reg_rdata_next[1] = perf_counter_enable_15_tcdm_accessed_15_qs; - reg_rdata_next[2] = perf_counter_enable_15_tcdm_congested_15_qs; - reg_rdata_next[3] = perf_counter_enable_15_issue_fpu_15_qs; - reg_rdata_next[4] = perf_counter_enable_15_issue_fpu_seq_15_qs; - reg_rdata_next[5] = perf_counter_enable_15_issue_core_to_fpu_15_qs; - reg_rdata_next[6] = perf_counter_enable_15_retired_instr_15_qs; - reg_rdata_next[7] = perf_counter_enable_15_retired_load_15_qs; - reg_rdata_next[8] = perf_counter_enable_15_retired_i_15_qs; - reg_rdata_next[9] = perf_counter_enable_15_retired_acc_15_qs; - reg_rdata_next[10] = perf_counter_enable_15_dma_aw_stall_15_qs; - reg_rdata_next[11] = perf_counter_enable_15_dma_ar_stall_15_qs; - reg_rdata_next[12] = perf_counter_enable_15_dma_r_stall_15_qs; - reg_rdata_next[13] = perf_counter_enable_15_dma_w_stall_15_qs; - reg_rdata_next[14] = perf_counter_enable_15_dma_buf_w_stall_15_qs; - reg_rdata_next[15] = perf_counter_enable_15_dma_buf_r_stall_15_qs; - reg_rdata_next[16] = perf_counter_enable_15_dma_aw_done_15_qs; - reg_rdata_next[17] = perf_counter_enable_15_dma_aw_bw_15_qs; - reg_rdata_next[18] = perf_counter_enable_15_dma_ar_done_15_qs; - reg_rdata_next[19] = perf_counter_enable_15_dma_ar_bw_15_qs; - reg_rdata_next[20] = perf_counter_enable_15_dma_r_done_15_qs; - reg_rdata_next[21] = perf_counter_enable_15_dma_r_bw_15_qs; - reg_rdata_next[22] = perf_counter_enable_15_dma_w_done_15_qs; - reg_rdata_next[23] = perf_counter_enable_15_dma_w_bw_15_qs; - reg_rdata_next[24] = perf_counter_enable_15_dma_b_done_15_qs; - reg_rdata_next[25] = perf_counter_enable_15_dma_busy_15_qs; - reg_rdata_next[26] = perf_counter_enable_15_icache_miss_15_qs; - reg_rdata_next[27] = perf_counter_enable_15_icache_hit_15_qs; - reg_rdata_next[28] = perf_counter_enable_15_icache_prefetch_15_qs; - reg_rdata_next[29] = perf_counter_enable_15_icache_double_hit_15_qs; - reg_rdata_next[30] = perf_counter_enable_15_icache_stall_15_qs; + reg_rdata_next[0] = perf_cnt_en_15_qs; end addr_hit[16]: begin - reg_rdata_next[9:0] = hart_select_0_qs; + reg_rdata_next[15:0] = perf_cnt_sel_0_hart_0_qs; + reg_rdata_next[31:16] = perf_cnt_sel_0_metric_0_qs; end addr_hit[17]: begin - reg_rdata_next[9:0] = hart_select_1_qs; + reg_rdata_next[15:0] = perf_cnt_sel_1_hart_1_qs; + reg_rdata_next[31:16] = perf_cnt_sel_1_metric_1_qs; end addr_hit[18]: begin - reg_rdata_next[9:0] = hart_select_2_qs; + reg_rdata_next[15:0] = perf_cnt_sel_2_hart_2_qs; + reg_rdata_next[31:16] = perf_cnt_sel_2_metric_2_qs; end addr_hit[19]: begin - reg_rdata_next[9:0] = hart_select_3_qs; + reg_rdata_next[15:0] = perf_cnt_sel_3_hart_3_qs; + reg_rdata_next[31:16] = perf_cnt_sel_3_metric_3_qs; end addr_hit[20]: begin - reg_rdata_next[9:0] = hart_select_4_qs; + reg_rdata_next[15:0] = perf_cnt_sel_4_hart_4_qs; + reg_rdata_next[31:16] = perf_cnt_sel_4_metric_4_qs; end addr_hit[21]: begin - reg_rdata_next[9:0] = hart_select_5_qs; + reg_rdata_next[15:0] = perf_cnt_sel_5_hart_5_qs; + reg_rdata_next[31:16] = perf_cnt_sel_5_metric_5_qs; end addr_hit[22]: begin - reg_rdata_next[9:0] = hart_select_6_qs; + reg_rdata_next[15:0] = perf_cnt_sel_6_hart_6_qs; + reg_rdata_next[31:16] = perf_cnt_sel_6_metric_6_qs; end addr_hit[23]: begin - reg_rdata_next[9:0] = hart_select_7_qs; + reg_rdata_next[15:0] = perf_cnt_sel_7_hart_7_qs; + reg_rdata_next[31:16] = perf_cnt_sel_7_metric_7_qs; end addr_hit[24]: begin - reg_rdata_next[9:0] = hart_select_8_qs; + reg_rdata_next[15:0] = perf_cnt_sel_8_hart_8_qs; + reg_rdata_next[31:16] = perf_cnt_sel_8_metric_8_qs; end addr_hit[25]: begin - reg_rdata_next[9:0] = hart_select_9_qs; + reg_rdata_next[15:0] = perf_cnt_sel_9_hart_9_qs; + reg_rdata_next[31:16] = perf_cnt_sel_9_metric_9_qs; end addr_hit[26]: begin - reg_rdata_next[9:0] = hart_select_10_qs; + reg_rdata_next[15:0] = perf_cnt_sel_10_hart_10_qs; + reg_rdata_next[31:16] = perf_cnt_sel_10_metric_10_qs; end addr_hit[27]: begin - reg_rdata_next[9:0] = hart_select_11_qs; + reg_rdata_next[15:0] = perf_cnt_sel_11_hart_11_qs; + reg_rdata_next[31:16] = perf_cnt_sel_11_metric_11_qs; end addr_hit[28]: begin - reg_rdata_next[9:0] = hart_select_12_qs; + reg_rdata_next[15:0] = perf_cnt_sel_12_hart_12_qs; + reg_rdata_next[31:16] = perf_cnt_sel_12_metric_12_qs; end addr_hit[29]: begin - reg_rdata_next[9:0] = hart_select_13_qs; + reg_rdata_next[15:0] = perf_cnt_sel_13_hart_13_qs; + reg_rdata_next[31:16] = perf_cnt_sel_13_metric_13_qs; end addr_hit[30]: begin - reg_rdata_next[9:0] = hart_select_14_qs; + reg_rdata_next[15:0] = perf_cnt_sel_14_hart_14_qs; + reg_rdata_next[31:16] = perf_cnt_sel_14_metric_14_qs; end addr_hit[31]: begin - reg_rdata_next[9:0] = hart_select_15_qs; + reg_rdata_next[15:0] = perf_cnt_sel_15_hart_15_qs; + reg_rdata_next[31:16] = perf_cnt_sel_15_metric_15_qs; end addr_hit[32]: begin - reg_rdata_next[47:0] = perf_counter_0_qs; + reg_rdata_next[47:0] = perf_cnt_0_qs; end addr_hit[33]: begin - reg_rdata_next[47:0] = perf_counter_1_qs; + reg_rdata_next[47:0] = perf_cnt_1_qs; end addr_hit[34]: begin - reg_rdata_next[47:0] = perf_counter_2_qs; + reg_rdata_next[47:0] = perf_cnt_2_qs; end addr_hit[35]: begin - reg_rdata_next[47:0] = perf_counter_3_qs; + reg_rdata_next[47:0] = perf_cnt_3_qs; end addr_hit[36]: begin - reg_rdata_next[47:0] = perf_counter_4_qs; + reg_rdata_next[47:0] = perf_cnt_4_qs; end addr_hit[37]: begin - reg_rdata_next[47:0] = perf_counter_5_qs; + reg_rdata_next[47:0] = perf_cnt_5_qs; end addr_hit[38]: begin - reg_rdata_next[47:0] = perf_counter_6_qs; + reg_rdata_next[47:0] = perf_cnt_6_qs; end addr_hit[39]: begin - reg_rdata_next[47:0] = perf_counter_7_qs; + reg_rdata_next[47:0] = perf_cnt_7_qs; end addr_hit[40]: begin - reg_rdata_next[47:0] = perf_counter_8_qs; + reg_rdata_next[47:0] = perf_cnt_8_qs; end addr_hit[41]: begin - reg_rdata_next[47:0] = perf_counter_9_qs; + reg_rdata_next[47:0] = perf_cnt_9_qs; end addr_hit[42]: begin - reg_rdata_next[47:0] = perf_counter_10_qs; + reg_rdata_next[47:0] = perf_cnt_10_qs; end addr_hit[43]: begin - reg_rdata_next[47:0] = perf_counter_11_qs; + reg_rdata_next[47:0] = perf_cnt_11_qs; end addr_hit[44]: begin - reg_rdata_next[47:0] = perf_counter_12_qs; + reg_rdata_next[47:0] = perf_cnt_12_qs; end addr_hit[45]: begin - reg_rdata_next[47:0] = perf_counter_13_qs; + reg_rdata_next[47:0] = perf_cnt_13_qs; end addr_hit[46]: begin - reg_rdata_next[47:0] = perf_counter_14_qs; + reg_rdata_next[47:0] = perf_cnt_14_qs; end addr_hit[47]: begin - reg_rdata_next[47:0] = perf_counter_15_qs; + reg_rdata_next[47:0] = perf_cnt_15_qs; end addr_hit[48]: begin @@ -17804,10 +2182,6 @@ module snitch_cluster_peripheral_reg_top #( end addr_hit[50]: begin - reg_rdata_next[31:0] = hw_barrier_qs; - end - - addr_hit[51]: begin reg_rdata_next[0] = '0; end @@ -17830,3 +2204,55 @@ module snitch_cluster_peripheral_reg_top #( `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) endmodule + +module snitch_cluster_peripheral_reg_top_intf +#( + parameter int AW = 9, + localparam int DW = 64 +) ( + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output snitch_cluster_peripheral_reg_pkg::snitch_cluster_peripheral_reg2hw_t reg2hw, // Write + input snitch_cluster_peripheral_reg_pkg::snitch_cluster_peripheral_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + localparam int unsigned STRB_WIDTH = DW/8; + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + // Define structs for reg_bus + typedef logic [AW-1:0] addr_t; + typedef logic [DW-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) + + + + snitch_cluster_peripheral_reg_top #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) + ) i_regs ( + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i + ); + +endmodule + + diff --git a/sw/dnn/conv2d/src/main.c b/sw/dnn/conv2d/src/main.c index d49a391d34..c3e5978d51 100644 --- a/sw/dnn/conv2d/src/main.c +++ b/sw/dnn/conv2d/src/main.c @@ -21,26 +21,8 @@ int main() { const conv_layer l1_conv2d_l = layer; - uint32_t cycles, dma_busy; - - if (snrt_global_core_idx() == 0) { - snrt_reset_perf_counter(SNRT_PERF_CNT0); - snrt_reset_perf_counter(SNRT_PERF_CNT1); - snrt_start_perf_counter(SNRT_PERF_CNT0, SNRT_PERF_CNT_CYCLES, 0); - snrt_start_perf_counter(SNRT_PERF_CNT1, SNRT_PERF_CNT_DMA_BUSY, 0); - } - conv2d_layer(&l1_conv2d_l); - if (snrt_global_core_idx() == 0) { - snrt_stop_perf_counter(SNRT_PERF_CNT0); - snrt_stop_perf_counter(SNRT_PERF_CNT1); - - cycles = snrt_get_perf_counter(SNRT_PERF_CNT0); - dma_busy = snrt_get_perf_counter(SNRT_PERF_CNT1); - // printf("perf: %d/%d dma/total\n", dma_busy, cycles); - } - snrt_global_barrier(); return 0; diff --git a/sw/snRuntime/api/memory_decls.h b/sw/snRuntime/api/memory_decls.h index c4178cebda..b93125cbca 100644 --- a/sw/snRuntime/api/memory_decls.h +++ b/sw/snRuntime/api/memory_decls.h @@ -17,5 +17,3 @@ inline volatile uint32_t* __attribute__((const)) snrt_clint_msip_ptr(); inline volatile uint32_t* __attribute__((const)) snrt_cluster_clint_set_ptr(); inline volatile uint32_t* __attribute__((const)) snrt_cluster_clint_clr_ptr(); - -inline uint32_t __attribute__((const)) snrt_cluster_hw_barrier_addr(); diff --git a/sw/snRuntime/src/perf_cnt.c b/sw/snRuntime/src/perf_cnt.c new file mode 100644 index 0000000000..d1ebb90eb2 --- /dev/null +++ b/sw/snRuntime/src/perf_cnt.c @@ -0,0 +1,16 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +extern void perf_regs_t* snrt_perf_counters(); + +extern void snrt_cfg_perf_counter(uint32_t perf_cnt, uint16_t metric, + uint16_t hart); + +extern void snrt_start_perf_counter(uint32_t perf_cnt); + +extern void snrt_stop_perf_counter(uint32_t perf_cnt); + +extern void snrt_reset_perf_counter(uint32_t perf_cnt); + +extern uint32_t snrt_get_perf_counter(uint32_t perf_cnt); diff --git a/sw/snRuntime/src/perf_cnt.h b/sw/snRuntime/src/perf_cnt.h index f36504ca65..38d0794e1c 100644 --- a/sw/snRuntime/src/perf_cnt.h +++ b/sw/snRuntime/src/perf_cnt.h @@ -2,100 +2,84 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -#pragma once - -/// Different perf counters -// Must match with `snitch_cluster_peripheral` -enum snrt_perf_cnt { - SNRT_PERF_CNT0, - SNRT_PERF_CNT1, - SNRT_PERF_CNT2, - SNRT_PERF_CNT3, - SNRT_PERF_CNT4, - SNRT_PERF_CNT5, - SNRT_PERF_CNT6, - SNRT_PERF_CNT7, - SNRT_PERF_CNT8, - SNRT_PERF_CNT9, - SNRT_PERF_CNT10, - SNRT_PERF_CNT11, - SNRT_PERF_CNT12, - SNRT_PERF_CNT13, - SNRT_PERF_CNT14, - SNRT_PERF_CNT15, - SNRT_PERF_N_CNT, -}; - -/// Different types of performance counters -enum snrt_perf_cnt_type { - SNRT_PERF_CNT_CYCLES, - SNRT_PERF_CNT_TCDM_ACCESSED, - SNRT_PERF_CNT_TCDM_CONGESTED, - SNRT_PERF_CNT_ISSUE_FPU, - SNRT_PERF_CNT_ISSUE_FPU_SEQ, - SNRT_PERF_CNT_ISSUE_CORE_TO_FPU, - SNRT_PERF_CNT_RETIRED_INSTR, - SNRT_PERF_CNT_RETIRED_LOAD, - SNRT_PERF_CNT_RETIRED_I, - SNRT_PERF_CNT_RETIRED_ACC, - SNRT_PERF_CNT_DMA_AW_STALL, - SNRT_PERF_CNT_DMA_AR_STALL, - SNRT_PERF_CNT_DMA_R_STALL, - SNRT_PERF_CNT_DMA_W_STALL, - SNRT_PERF_CNT_DMA_BUF_W_STALL, - SNRT_PERF_CNT_DMA_BUF_R_STALL, - SNRT_PERF_CNT_DMA_AW_DONE, - SNRT_PERF_CNT_DMA_AW_BW, - SNRT_PERF_CNT_DMA_AR_DONE, - SNRT_PERF_CNT_DMA_AR_BW, - SNRT_PERF_CNT_DMA_R_DONE, - SNRT_PERF_CNT_DMA_R_BW, - SNRT_PERF_CNT_DMA_W_DONE, - SNRT_PERF_CNT_DMA_W_BW, - SNRT_PERF_CNT_DMA_B_DONE, - SNRT_PERF_CNT_DMA_BUSY, - SNRT_PERF_CNT_ICACHE_MISS, - SNRT_PERF_CNT_ICACHE_HIT, - SNRT_PERF_CNT_ICACHE_PREFETCH, - SNRT_PERF_CNT_ICACHE_DOUBLE_HIT, - SNRT_PERF_CNT_ICACHE_STALL, -}; +#define SNRT_NUM_PERF_CNTS SNITCH_CLUSTER_PERIPHERAL_PARAM_NUM_PERF_COUNTERS +/** + * @brief Union representing a 32-bit performance counter register, with 8-byte + * alignment. + */ typedef union { uint32_t value __attribute__((aligned(8))); } perf_reg32_t; +/** + * @brief Structure representing the performance counters. + * + * This structure defines the memory layout of the performance counters + * configuration register, as they are defined in + * `snitch_cluster_peripheral.hjson`. + */ typedef struct { - volatile perf_reg32_t enable[SNRT_PERF_N_CNT]; - volatile perf_reg32_t hart_select[SNRT_PERF_N_CNT]; - volatile perf_reg32_t perf_counter[SNRT_PERF_N_CNT]; + volatile perf_reg32_t enable[SNRT_NUM_PERF_CNTS]; + volatile perf_reg32_t select[SNRT_NUM_PERF_CNTS]; + volatile perf_reg32_t perf_counter[SNRT_NUM_PERF_CNTS]; } perf_regs_t; +/** + * @brief Get the pointer to the performance counter registers + * + * @return perf_regs_t* Pointer to the performance counter registers + */ inline perf_regs_t* snrt_perf_counters() { return (perf_regs_t*)snrt_cluster_perf_counters_addr(); } -// Enable a specific perf_counter -inline void snrt_start_perf_counter(enum snrt_perf_cnt perf_cnt, - enum snrt_perf_cnt_type perf_cnt_type, - uint32_t hart_id) { - snrt_perf_counters()->hart_select[perf_cnt].value |= hart_id; - snrt_perf_counters()->enable[perf_cnt].value = (0x1 << perf_cnt_type); +/** + * @brief Configures the performance counter for a specific metric and hart. + * + * @param perf_cnt The index of the performance counter to configure. + * @param metric The metric value to set for the performance counter. + * @param hart The hart value to set for the performance counter. + */ +inline void snrt_cfg_perf_counter(uint32_t perf_cnt, uint16_t metric, + uint16_t hart) { + snrt_perf_counters()->select[perf_cnt].value = (metric << 16) | hart; } -// Stops the counter but does not reset it -inline void snrt_stop_perf_counter(enum snrt_perf_cnt perf_cnt) { - snrt_perf_counters()->enable[perf_cnt].value = 0x0; +/** + * @brief Starts a performance counter. + * + * @param perf_cnt The index of the performance counter to start. + */ +inline void snrt_start_perf_counter(uint32_t perf_cnt) { + snrt_perf_counters()->enable[perf_cnt].value = 0x1; } -// Resets the counter completely -inline void snrt_reset_perf_counter(enum snrt_perf_cnt perf_cnt) { +/** + * @brief Stops a performance counter. + * + * @param perf_cnt The index of the performance counter to stop. + */ +inline void snrt_stop_perf_counter(uint32_t perf_cnt) { snrt_perf_counters()->enable[perf_cnt].value = 0x0; - snrt_perf_counters()->hart_select[perf_cnt].value = 0x0; +} + +/** + * @brief Reset the value of a performance counter. + * + * @param perf_cnt The index of the performance counter to reset. + */ +inline void snrt_reset_perf_counter(uint32_t perf_cnt) { snrt_perf_counters()->perf_counter[perf_cnt].value = 0x0; } -// Get counter of specified perf_counter -inline uint32_t snrt_get_perf_counter(enum snrt_perf_cnt perf_cnt) { - return (uint32_t)(snrt_perf_counters()->perf_counter[perf_cnt].value); +/** + * @brief Retrieves the value of a performance counter. + * + * @param perf_cnt The index of the performance counter to retrieve the value + * from. + * @return The value of the specified performance counter. + */ +inline uint32_t snrt_get_perf_counter(uint32_t perf_cnt) { + return snrt_perf_counters()->perf_counter[perf_cnt].value; } diff --git a/sw/tests/perf_cnt.c b/sw/tests/perf_cnt.c index 907d8281a0..2b5e5febdc 100644 --- a/sw/tests/perf_cnt.c +++ b/sw/tests/perf_cnt.c @@ -5,110 +5,134 @@ #include "printf.h" #include "snrt.h" +#define WIDE_WORD_SIZE 64 + int main() { + uint32_t errors = 0; uint32_t core_idx = snrt_cluster_core_idx(); + // Test 1: Check that the performance counters immediately + // starts tracking `Cycle` and `RetiredInstr` if (core_idx == 0) { - uint32_t counter; + errors += (snrt_get_perf_counter(0) == 0); + errors += (snrt_get_perf_counter(1) == 0); + } - printf("Measuring cycles\n"); - counter = snrt_get_perf_counter(SNRT_PERF_CNT0); - printf("Start: %d cycles\n", counter); + // Test 2: Check that all performance counters can be reset + if (core_idx == 0) { + for (int i = 0; i < SNRT_NUM_PERF_CNTS; i++) { + // Stop and reset the performance counter + snrt_stop_perf_counter(i); + snrt_reset_perf_counter(i); - // Start performance counter - snrt_start_perf_counter(SNRT_PERF_CNT0, SNRT_PERF_CNT_CYCLES, 0); + // Check that the performance counter is reset + errors += (snrt_get_perf_counter(i) != 0); + } + } + + // Test 3: Check that the performance counters can be configured and started + if (core_idx == 0) { + for (int i = 0; i < SNRT_NUM_PERF_CNTS; i++) { + // Configure and start the performance counter + snrt_cfg_perf_counter( + i, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_CYCLE, + 0); + snrt_start_perf_counter(i); + } // Wait for some cycles for (int i = 0; i < 100; i++) { asm volatile("nop"); } - // Stop performance counter - snrt_stop_perf_counter(SNRT_PERF_CNT0); + for (int i = 0; i < SNRT_NUM_PERF_CNTS; i++) { + // Stop the performance counter + snrt_stop_perf_counter(i); - // Get performance counters - counter = snrt_get_perf_counter(SNRT_PERF_CNT0); - printf("End: %d cycles\n", counter); + // Check that the performance counter is started + errors += (snrt_get_perf_counter(i) < 100); - // Reset counter - snrt_reset_perf_counter(SNRT_PERF_CNT0); + // Reset the performance counter again + snrt_reset_perf_counter(i); + } } snrt_cluster_hw_barrier(); + // Test 4: Check DMA performance with simple 1D test if (snrt_is_dm_core()) { - uint32_t read_bytes, write_bytes; - - printf("Measuring DMA perf\n"); - read_bytes = snrt_get_perf_counter(SNRT_PERF_CNT0); - write_bytes = snrt_get_perf_counter(SNRT_PERF_CNT1); - printf("Start: %d/%d bytes read, written\n", read_bytes, write_bytes); - - // Start performance counter - snrt_start_perf_counter(SNRT_PERF_CNT0, SNRT_PERF_CNT_DMA_AR_BW, 0); - snrt_start_perf_counter(SNRT_PERF_CNT1, SNRT_PERF_CNT_DMA_AW_BW, 0); + // Configure performance counters to track DMA read and writes + snrt_cfg_perf_counter( + 0, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_DMA_AW_DONE, + 0); + snrt_cfg_perf_counter( + 1, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_DMA_AR_DONE, + 0); // Transfer around some data - uint32_t *dst = (void *)snrt_l1_next(); + uint32_t *dst = + (void *)ALIGN_UP((uintptr_t)snrt_l1_next(), WIDE_WORD_SIZE); uint32_t *src = - (void *)snrt_l3_next() + 0x4; // Induce misaligned access - printf("Transfering from %p to %p\n", src, dst); - snrt_dma_txid_t txid_1d = snrt_dma_start_1d(dst, src, 128); - snrt_dma_txid_t txid_2d = snrt_dma_start_2d(dst, src, 128, 128, 0, 4); + (void *)ALIGN_UP((uintptr_t)snrt_l3_next(), WIDE_WORD_SIZE); + + // Start performance counters + snrt_start_perf_counter(0); + snrt_start_perf_counter(1); - // Wait until completion + // Start DMA transfer and wait for completion + snrt_dma_txid_t txid_1d = snrt_dma_start_1d(dst, src, WIDE_WORD_SIZE); snrt_dma_wait_all(); // Stop performance counter - snrt_stop_perf_counter(SNRT_PERF_CNT0); - snrt_stop_perf_counter(SNRT_PERF_CNT1); + snrt_stop_perf_counter(0); + snrt_stop_perf_counter(1); - // Get performance counters - read_bytes = snrt_get_perf_counter(SNRT_PERF_CNT0); - write_bytes = snrt_get_perf_counter(SNRT_PERF_CNT1); - printf("End: %d/%d bytes read, written\n", read_bytes, write_bytes); + // There should be one AR and one AW + errors += (snrt_get_perf_counter(0) != 1); + errors += (snrt_get_perf_counter(1) != 1); // Reset counter - snrt_reset_perf_counter(SNRT_PERF_CNT0); - snrt_reset_perf_counter(SNRT_PERF_CNT1); + snrt_reset_perf_counter(0); + snrt_reset_perf_counter(1); } + // Test 5: Check DMA performance with misaligned 1D test + if (snrt_is_dm_core()) { + // Configure performance counters to track DMA read and write beats + snrt_cfg_perf_counter( + 0, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_DMA_W_DONE, + 0); + snrt_cfg_perf_counter( + 1, + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_METRIC_0_VALUE_DMA_R_DONE, + 0); - snrt_cluster_hw_barrier(); - - uint32_t tcdm_accesses, tcdm_congestion; - - if (core_idx == 0) { - printf("Measuring TCDM congestion\n"); - tcdm_accesses = snrt_get_perf_counter(SNRT_PERF_CNT0); - tcdm_congestion = snrt_get_perf_counter(SNRT_PERF_CNT1); - printf("Start: %d/%d Congestion/Accesses\n", tcdm_congestion, - tcdm_accesses); + // Transfer around some data + uint32_t *dst = + (void *)ALIGN_UP((uintptr_t)snrt_l1_next(), WIDE_WORD_SIZE); + uint32_t *src_misaligned = + (void *)ALIGN_UP((uintptr_t)snrt_l3_next(), WIDE_WORD_SIZE) + 0x8; // Start performance counters - snrt_start_perf_counter(SNRT_PERF_CNT0, SNRT_PERF_CNT_TCDM_ACCESSED, 0); - snrt_start_perf_counter(SNRT_PERF_CNT1, SNRT_PERF_CNT_TCDM_CONGESTED, - 0); - } - - snrt_cluster_hw_barrier(); + snrt_start_perf_counter(0); + snrt_start_perf_counter(1); - // Keep TCDM busy - volatile uint32_t *ptr = (void *)snrt_l1_next(); - for (uint32_t i = 0; i < 100; i++) { - *ptr = 0xdeadbeef; - } + // Start misaligned DMA transfer and wait for completion + snrt_dma_txid_t txid_1d_misaligned = + snrt_dma_start_1d(dst, src_misaligned, WIDE_WORD_SIZE); + snrt_dma_wait_all(); - if (core_idx == 0) { // Stop performance counter - snrt_stop_perf_counter(SNRT_PERF_CNT0); - snrt_stop_perf_counter(SNRT_PERF_CNT1); - - // Get performance counters - tcdm_accesses = snrt_get_perf_counter(SNRT_PERF_CNT0); - tcdm_congestion = snrt_get_perf_counter(SNRT_PERF_CNT1); - printf("End: %d/%d Congestion/Accesses\n", tcdm_congestion, - tcdm_accesses); + snrt_stop_perf_counter(0); + snrt_stop_perf_counter(1); + + // There should be two R and one W beat from the DMA + errors += (snrt_get_perf_counter(0) != 1); + errors += (snrt_get_perf_counter(1) != 2); } - return 0; + return errors; } diff --git a/target/snitch_cluster/Makefile b/target/snitch_cluster/Makefile index bb4f837c66..60c49d8dc4 100644 --- a/target/snitch_cluster/Makefile +++ b/target/snitch_cluster/Makefile @@ -18,7 +18,8 @@ SELECT_RUNTIME ?= rtl .DEFAULT_GOAL := help .PHONY: all clean -clean: clean-work clean-vcs clean-logs clean-bender clean-generated +all: rtl sw +clean: clean-rtl clean-work clean-vcs clean-logs clean-bender clean-generated ########## # Common # @@ -47,6 +48,7 @@ CLUSTER_GEN_SRC ?= $(wildcard $(ROOT)/util/clustergen/*.py) BIN_DIR ?= bin GENERATED_DIR ?= $(MKFILE_DIR)generated +PERIPH_DIR ?= $(ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral # If the configuration file is overriden on the command-line (through # CFG_OVERRIDE) and this file differs from the least recently used @@ -149,6 +151,17 @@ include $(ROOT)/target/snitch_cluster/sw.mk # RTL # ####### +GENERATED_RTL_SOURCES = $(PERIPH_DIR)/snitch_cluster_peripheral_reg_top.sv +GENERATED_RTL_SOURCES += $(PERIPH_DIR)/snitch_cluster_peripheral_reg_pkg.sv +GENERATED_RTL_SOURCES += $(GENERATED_DIR)/snitch_cluster_wrapper.sv + +.PHONY: rtl clean-rtl + +rtl: $(GENERATED_RTL_SOURCES) + +clean-rtl: + rm -f $(GENERATED_RTL_SOURCES) + $(GENERATED_DIR): mkdir -p $@ @@ -164,6 +177,12 @@ $(GENERATED_DIR)/memories.json: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR) $(GENERATED_DIR)/bootdata.cc: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR) $(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --bootdata +# REGGEN regfile +$(PERIPH_DIR)/snitch_cluster_peripheral_reg_pkg.sv: $(PERIPH_DIR)/snitch_cluster_peripheral_reg_top.sv +$(PERIPH_DIR)/snitch_cluster_peripheral_reg_top.sv: $(PERIPH_DIR)/snitch_cluster_peripheral_reg.hjson + @echo "[REGGEN] Generating peripheral regfile" + $(REGGEN) -r -t $(PERIPH_DIR) $< + ############# # Verilator # ############# @@ -228,9 +247,11 @@ help: @echo -e "${Blue}$(BIN_DIR)/$(TARGET).vsim ${Black}Build compilation script and compile all sources for Questasim simulation." @echo -e "" @echo -e "${Blue}sw ${Black}Build all software." + @echo -e "${Blue}rtl ${Black}Build all RTL." @echo -e "" @echo -e "${Blue}clean ${Black}Clean everything except traces in logs directory." @echo -e "${Blue}clean-bender ${Black}Clean Bender dependencies." + @echo -e "${Blue}clean-rtl ${Black}Clean all generated RTL sources." @echo -e "${Blue}clean-sw ${Black}Clean all software." @echo -e "${Blue}clean-generated ${Black}Delete all generated files in the generated directory." @echo -e "${Blue}clean-logs ${Black}Delete all traces in logs directory." diff --git a/target/snitch_cluster/sw/run.yaml b/target/snitch_cluster/sw/run.yaml index 01428a0d4a..7a5a55a4cf 100644 --- a/target/snitch_cluster/sw/run.yaml +++ b/target/snitch_cluster/sw/run.yaml @@ -61,6 +61,7 @@ runs: - elf: tests/build/openmp_for_static_schedule.elf - elf: tests/build/openmp_double_buffering.elf - elf: tests/build/perf_cnt.elf + simulators: [vsim, vcs, verilator] # banshee does not have HW performance counters - elf: tests/build/printf_simple.elf - elf: tests/build/printf_fmtint.elf - elf: tests/build/simple.elf diff --git a/target/snitch_cluster/sw/runtime/common/snitch_cluster_cfg.h.tpl b/target/snitch_cluster/sw/runtime/common/snitch_cluster_cfg.h.tpl index e434e6c88b..2daf9bc986 100644 --- a/target/snitch_cluster/sw/runtime/common/snitch_cluster_cfg.h.tpl +++ b/target/snitch_cluster/sw/runtime/common/snitch_cluster_cfg.h.tpl @@ -11,8 +11,6 @@ #define SNRT_TCDM_START_ADDR CLUSTER_TCDM_BASE_ADDR #define SNRT_TCDM_SIZE (CLUSTER_PERIPH_BASE_ADDR - CLUSTER_TCDM_BASE_ADDR) #define SNRT_CLUSTER_OFFSET ${cfg['cluster']['cluster_base_offset']} -#define SNRT_CLUSTER_HW_BARRIER_ADDR \ - (CLUSTER_PERIPH_BASE_ADDR + SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_REG_OFFSET) // Software configuration #define SNRT_LOG2_STACK_SIZE 10 diff --git a/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.c b/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.c index 48c08faa38..62826f6bf9 100644 --- a/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.c +++ b/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.c @@ -10,6 +10,4 @@ extern volatile uint32_t* snrt_cluster_clint_set_ptr(); extern volatile uint32_t* snrt_cluster_clint_clr_ptr(); -extern uint32_t snrt_cluster_hw_barrier_addr(); - extern volatile uint32_t* snrt_zero_memory_ptr(); diff --git a/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.h b/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.h index 086eb60508..dc60c47970 100644 --- a/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.h +++ b/target/snitch_cluster/sw/runtime/common/snitch_cluster_memory.h @@ -15,12 +15,9 @@ (CLUSTER_PERIPH_BASE_ADDR + \ SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_REG_OFFSET) -#define CLUSTER_HW_BARRIER_ADDR \ - (CLUSTER_PERIPH_BASE_ADDR + SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_REG_OFFSET) - #define CLUSTER_PERF_COUNTER_ADDR \ (CLUSTER_PERIPH_BASE_ADDR + \ - SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_REG_OFFSET) + SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_REG_OFFSET) #define CLUSTER_TCDM_START_ADDR CLUSTER_TCDM_BASE_ADDR @@ -50,10 +47,6 @@ inline volatile uint32_t* snrt_cluster_clint_clr_ptr() { return (uint32_t*)(CLUSTER_CLINT_CLR_ADDR + cluster_base_offset()); } -inline uint32_t snrt_cluster_hw_barrier_addr() { - return CLUSTER_HW_BARRIER_ADDR + cluster_base_offset(); -} - inline uint32_t snrt_cluster_perf_counters_addr() { return CLUSTER_PERF_COUNTER_ADDR + cluster_base_offset(); } diff --git a/util/lint/waiver.verible b/util/lint/waiver.verible index f25deaded5..5413ede541 100644 --- a/util/lint/waiver.verible +++ b/util/lint/waiver.verible @@ -2,14 +2,8 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Sources in the future folder -waive --rule=always-ff-non-blocking --location="hw/future/src/dma/axi_dma_backend.sv" -waive --rule=explicit-parameter-storage-type --location="hw/future/test/fixture_axi_dma_backend.sv" -waive --rule=explicit-task-lifetime --location="hw/future/test/fixture_axi_dma_backend.sv" -waive --rule=explicit-function-task-parameter-type --location="hw/future/test/fixture_axi_dma_backend.sv" -waive --rule=line-length --location="hw/future/test/fixture_axi_dma_backend.sv" -waive --rule=parameter-name-style --location="hw/future/src/axi_interleaved_xbar.sv" -waive --rule=unpacked-dimensions-range-ordering --location="hw/future/src/axi_interleaved_xbar.sv" # Auto-generated configuration registers are waived waive --rule=typedef-structs-unions --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" waive --rule=line-length --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv" +waive --rule=parameter-name-style --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv" +waive --rule=no-trailing-spaces --location="hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv"