diff --git a/target/common/common.mk b/target/common/common.mk
index 77d0e79d3..48995aa61 100644
--- a/target/common/common.mk
+++ b/target/common/common.mk
@@ -54,6 +54,8 @@ SED_SRCS  := sed -e ${MATCH_END} -e ${MATCH_BGN} -e ${MATCH_DEF}
 
 COMMON_BENDER_FLAGS += -t rtl
 
+GVSOC_BUILDDIR ?= work-gvsoc
+
 VSIM_BENDER   += $(COMMON_BENDER_FLAGS) -t test -t simulation -t vsim
 VSIM_SOURCES   = $(shell ${BENDER} script flist-plus ${VSIM_BENDER} | ${SED_SRCS})
 VSIM_BUILDDIR ?= work-vsim
diff --git a/target/common/gvsoc.mk b/target/common/gvsoc.mk
new file mode 100644
index 000000000..d9e82ba4d
--- /dev/null
+++ b/target/common/gvsoc.mk
@@ -0,0 +1,17 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+$(BIN_DIR)/$(TARGET).gvsoc:
+	@echo "#!/bin/bash" > $@
+	@echo 'binary=$$(realpath $$1)' >> $@
+	@echo 'echo $$binary > .rtlbinary' >> $@
+	@echo 'gvsoc --target=snitch --binary $$binary \
+	   --control-script=$(GVSOC_BUILDDIR)/pulp/pulp/snitch/utils/gvcontrol.py $$2 run' >> $@
+	@chmod +x $@
+
+.PHONY: clean-gvsoc
+clean-gvsoc:
+	rm -rf $(BIN_DIR)/$(TARGET).gvsoc $(GVSOC_BUILDDIR)
+
+clean: clean-gvsoc
diff --git a/target/snitch_cluster/Makefile b/target/snitch_cluster/Makefile
index 1a5ab2388..ff01611a4 100644
--- a/target/snitch_cluster/Makefile
+++ b/target/snitch_cluster/Makefile
@@ -215,6 +215,12 @@ $(BIN_DIR)/$(TARGET).vcs: ${VCS_SOURCES} ${TB_SRCS} $(TB_CC_SOURCES) $(RTL_CC_SO
 		-assert disable_cover -override_timescale=1ns/1ps -full64 tb_bin $(TB_CC_SOURCES) $(RTL_CC_SOURCES) \
 		-CFLAGS "$(TB_CC_FLAGS)" -LDFLAGS "-L${FESVR}/lib" -lfesvr
 
+#########
+# GVSOC #
+#########
+
+include $(ROOT)/target/common/gvsoc.mk
+
 ########
 # Util #
 ########
diff --git a/target/snitch_cluster/util/run.py b/target/snitch_cluster/util/run.py
index ee7a7d0fb..5c95701ff 100755
--- a/target/snitch_cluster/util/run.py
+++ b/target/snitch_cluster/util/run.py
@@ -24,7 +24,7 @@
     'vcs': VCSSimulator(Path(__file__).parent.resolve() / '../bin/snitch_cluster.vcs'),
     'verilator': VerilatorSimulator(Path(__file__).parent.resolve() / '../bin/snitch_cluster.vlt'),
     'banshee': BansheeSimulator(Path(__file__).parent.resolve() / '../src/banshee.yaml'),
-    'gvsoc': GvsocSimulator(Path(__file__).parent.resolve())
+    'gvsoc': GvsocSimulator(Path(__file__).parent.resolve() / '../bin/snitch_cluster.gvsoc')
 }
 
 
diff --git a/util/sim/Simulation.py b/util/sim/Simulation.py
index 9610883ba..caa98e0e6 100644
--- a/util/sim/Simulation.py
+++ b/util/sim/Simulation.py
@@ -273,8 +273,17 @@ class GvsocSimulation(Simulation):
     def __init__(self, sim_bin=None, cmd=None, **kwargs):
         super().__init__(**kwargs)
 
-        self.cmd = ['gvsoc', '--target', os.environ.get('GVSOC_TARGET'), '--binary',
-                    str(self.elf), 'run']
+        if cmd is None:
+            self.cmd = ['gvsoc', '--target', os.environ.get('GVSOC_TARGET'), '--binary',
+                        str(self.elf), 'run']
+        else:
+            self.dynamic_args = {
+                'sim_bin': str(sim_bin),
+                'elf': str(self.elf),
+                'run_dir': str(self.run_dir)
+            }
+            self.cmd = [Template(arg).render(**self.dynamic_args) for arg in cmd]
+            self.cmd.append('--simulator=gvsoc')
 
     def successful(self):
         """Return whether the simulation was successful."""
diff --git a/util/sim/SnitchSim.py b/util/sim/SnitchSim.py
index d98c1ec14..4eddd8b43 100755
--- a/util/sim/SnitchSim.py
+++ b/util/sim/SnitchSim.py
@@ -25,11 +25,12 @@
 
 class SnitchSim:
 
-    def __init__(self, sim_bin: str, snitch_bin: str, log: str = None):
+    def __init__(self, sim_bin: str, snitch_bin: str, simulator: str = None, log: str = None):
         self.sim_bin = sim_bin
         self.snitch_bin = snitch_bin
         self.sim = None
         self.tmpdir = None
+        self.simulator = simulator
         self.log = open(log, 'w+') if log else log
 
     def start(self):
@@ -40,10 +41,15 @@ def start(self):
         rx_fd = os.path.join(self.tmpdir.name, 'rx')
         os.mkfifo(rx_fd)
         # Start simulator process
-        ipc_arg = f'--ipc,{tx_fd},{rx_fd}'
+        if self.simulator == 'gvsoc':
+            ipc_arg = f'--ipc {tx_fd},{rx_fd}'
+        else:
+            ipc_arg = f'--ipc,{tx_fd},{rx_fd}'
+
         self.sim = subprocess.Popen([self.sim_bin, self.snitch_bin, ipc_arg], stdout=self.log)
         # Open FIFOs
         self.tx = open(tx_fd, 'wb', buffering=0)  # Unbuffered
+
         self.rx = open(rx_fd, 'rb')
         # Create thread to monitor simulation
         self.stop_sim_monitor = threading.Event()
diff --git a/util/sim/verif_utils.py b/util/sim/verif_utils.py
index ef0caf8c7..0e257c821 100644
--- a/util/sim/verif_utils.py
+++ b/util/sim/verif_utils.py
@@ -97,6 +97,9 @@ def parser(self):
         parser.add_argument(
             '--log',
             help='Redirect simulation output to this log file')
+        parser.add_argument(
+            '--simulator',
+            help='Specifies simulator')
         parser.add_argument(
             '--dump-results',
             action='store_true',
@@ -144,7 +147,8 @@ def simulate(self):
         elf = Elf(self.args.snitch_bin)
 
         # Start simulation
-        sim = SnitchSim(self.args.sim_bin, self.args.snitch_bin, log=self.args.log)
+        sim = SnitchSim(self.args.sim_bin, self.args.snitch_bin, simulator=self.args.simulator,
+            log=self.args.log)
         sim.start()
 
         # Wait for kernel execution to be over