Skip to content

Remove C encoding instructions again #2074

Remove C encoding instructions again

Remove C encoding instructions again #2074

GitHub Actions / verible-verilog-lint failed Jul 25, 2024 in 0s

reviewdog [verible-verilog-lint] report

reported by reviewdog 🐶

Findings (5)

hw/snitch/src/snitch.sv|1610 col 38| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/snitch_cluster/src/snitch_fp_ss.sv|262 col 75| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/snitch_cluster/src/snitch_fp_ss.sv|559 col 10| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/snitch_cluster/src/snitch_fp_ss.sv|2515 col 9| Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default]
hw/snitch_cluster/src/snitch_fp_ss.sv|2555 col 12| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Filtered Findings (0)

Annotations

Check warning on line 1610 in hw/snitch/src/snitch.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/snitch/src/snitch.sv#L1610

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch/src/snitch.sv" range:{start:{line:1610 column:38}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1610 column:38} end:{line:1611}} text:"          acc_qvalid_o = valid_instr;\n"}

Check warning on line 262 in hw/snitch_cluster/src/snitch_fp_ss.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L262

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:262 column:75}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:262 column:75} end:{line:263}} text:"  assign shfl_in_ready = (!(acc_req_valid_q && result_select == ResAccBus)\n"}

Check warning on line 559 in hw/snitch_cluster/src/snitch_fp_ss.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L559

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:559 column:10}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:559 column:10} end:{line:560}} text:"      end\n"}

Check warning on line 2515 in hw/snitch_cluster/src/snitch_fp_ss.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2515

Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default]
Raw output
message:"Explicitly define a default case for every case statement. [Style: case-statements] [case-missing-default]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:2515 column:9}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

Check warning on line 2555 in hw/snitch_cluster/src/snitch_fp_ss.sv

See this annotation in the file changed.

@github-actions github-actions / verible-verilog-lint

[verible-verilog-lint] hw/snitch_cluster/src/snitch_fp_ss.sv#L2555

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./hw/snitch_cluster/src/snitch_fp_ss.sv" range:{start:{line:2555 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:2555 column:12} end:{line:2556}} text:"        end\n"}