diff --git a/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc b/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc
index e1a1e9c8..87a7d3b8 100644
--- a/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc
+++ b/target/fpga/pulpissimo-zyboz7/constraints/zyboz7.xdc
@@ -67,8 +67,13 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
-# waive DRCs related to emulated clock gating cells
-create_waiver -of_objects [get_methodology_violations -name xilinx_pulpissimo_methodology_drc_routed.rpx {TIMING-14#1}] -user fconti -description {emulated clock gating cells}
+# Create asynchronous clock group between JTAG TCK and per clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
+
+# Create asynchronous clock group between slow clock and JTAG TCK.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]]
 
 #############################################################
 #  _____ ____         _____      _   _   _                  #
diff --git a/target/fpga/pulpissimo-zyboz7/fpga-settings.mk b/target/fpga/pulpissimo-zyboz7/fpga-settings.mk
index 892e8851..3e8d6c2a 100644
--- a/target/fpga/pulpissimo-zyboz7/fpga-settings.mk
+++ b/target/fpga/pulpissimo-zyboz7/fpga-settings.mk
@@ -1,6 +1,6 @@
 export BOARD=zyboz7
 export XILINX_PART=xc7z020clg400-1
-export XILINX_BOARD=digilentinc.com:zybo-z7-20:part0:1.1
+export XILINX_BOARD=digilentinc.com:zybo-z7-20:part0:1.0
 export FC_CLK_PERIOD_NS=62.5
 export PER_CLK_PERIOD_NS=100
 export SLOW_CLK_PERIOD_NS=30517
diff --git a/target/fpga/pulpissimo-zyboz7/tcl/common.tcl b/target/fpga/pulpissimo-zyboz7/tcl/common.tcl
index f86dcbd0..c90d8f6b 100644
--- a/target/fpga/pulpissimo-zyboz7/tcl/common.tcl
+++ b/target/fpga/pulpissimo-zyboz7/tcl/common.tcl
@@ -10,8 +10,6 @@ if [info exists ::env(XILINX_BOARD)] {
 }
 set partNumber $::env(XILINX_PART)
 
-set_param board.repoPaths /home/michaero/.Xilinx/Vivado/2023.2/xhub/board_store/xilinx_board_store
-
 # sets up Vivado messages in a more sensible way
 set_msg_config -id {[Synth 8-3352]}         -new_severity "critical warning"
 set_msg_config -id {[Synth 8-350]}          -new_severity "critical warning"