From 9b2fa6bceb804bd27906e8f2c795a27f500e795e Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Tue, 5 Mar 2024 16:12:28 +0100 Subject: [PATCH 01/14] [hardware] Add generated control registers --- .clang-format-ignore | 1 + .github/workflows/ci.yml | 14 + .gitlab/.gitlab-ci.yml | 7 + Bender.yml | 2 + CHANGELOG.md | 1 + .../deps/patches/register_interface.patch | 98 ++ hardware/src/control_registers/Makefile | 32 + .../control_registers/control_registers.hjson | 126 +++ .../control_registers_reg_pkg.sv | 193 ++++ .../control_registers_reg_top.sv | 972 ++++++++++++++++++ hardware/src/ctrl_registers.sv | 285 +++-- hardware/src/mempool_system.sv | 10 +- hardware/tb/verilator/waiver.vlt | 3 + scripts/license-checker.hjson | 1 + scripts/lint.sh | 2 + software/runtime/addrmap.h | 14 + software/runtime/arch.ld.c | 27 - software/runtime/control_registers.h | 116 +++ software/runtime/crt0.S | 6 +- software/runtime/riscv_test.h | 3 +- software/runtime/runtime.h | 66 +- 21 files changed, 1753 insertions(+), 226 deletions(-) create mode 100644 hardware/deps/patches/register_interface.patch create mode 100644 hardware/src/control_registers/Makefile create mode 100644 hardware/src/control_registers/control_registers.hjson create mode 100644 hardware/src/control_registers/control_registers_reg_pkg.sv create mode 100644 hardware/src/control_registers/control_registers_reg_top.sv create mode 100644 software/runtime/addrmap.h create mode 100644 software/runtime/control_registers.h diff --git a/.clang-format-ignore b/.clang-format-ignore index b09ee4eaf..0bfe35ead 100644 --- a/.clang-format-ignore +++ b/.clang-format-ignore @@ -4,6 +4,7 @@ # Exclude files from formatting requirement # External dependencies +*/software/runtime/control_registers.h */software/runtime/encoding.h */software/riscv-tests */toolchain diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 457df0654..fd0be25b8 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -239,6 +239,20 @@ jobs: make -C hardware src/bootrom.sv git diff --exit-code + check-control-registers: + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v4 + - name: Install Python requirements + run: pip install -r python-requirements.txt + - name: Build Control Registers + run: | + git submodule update --init --recursive -- hardware/deps/register_interface + git apply hardware/deps/patches/register_interface.patch + make -C hardware/src/control_registers clean + make -C hardware/src/control_registers all + git diff --ignore-submodules=dirty --exit-code + check-opcodes: runs-on: ubuntu-20.04 steps: diff --git a/.gitlab/.gitlab-ci.yml b/.gitlab/.gitlab-ci.yml index 1bb6e54e2..a49145bc6 100644 --- a/.gitlab/.gitlab-ci.yml +++ b/.gitlab/.gitlab-ci.yml @@ -128,6 +128,13 @@ check-bootrom: - make -C hardware src/bootrom.sv - git diff --exit-code +check-control-registers: + stage: test + script: + - make -C hardware/src/control_registers clean + - make -C hardware/src/control_registers all + - git diff --exit-code + check-opcodes: stage: test script: diff --git a/Bender.yml b/Bender.yml index 438492b87..8d6913a8e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -35,6 +35,8 @@ sources: - hardware/src/address_scrambler.sv - hardware/src/axi2mem.sv - hardware/src/bootrom.sv + - hardware/src/control_registers/control_registers_reg_pkg.sv + - hardware/src/control_registers/control_registers_reg_top.sv # Level 1 - hardware/src/mempool_tile.sv # Level 2 diff --git a/CHANGELOG.md b/CHANGELOG.md index 4d4f0945b..76793e524 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -34,6 +34,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Update `register_interface` to 0.4.3 - Updated Halide to version 15 - Move instruction cache into its own dependency +- Use automatically generated control registers ### Fixed - Fix type issue in `snitch_addr_demux` diff --git a/hardware/deps/patches/register_interface.patch b/hardware/deps/patches/register_interface.patch new file mode 100644 index 000000000..04bea1d5f --- /dev/null +++ b/hardware/deps/patches/register_interface.patch @@ -0,0 +1,98 @@ +diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl +index 1c5520a..77619d9 100644 +--- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl ++++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl +@@ -1,6 +1,6 @@ +-// Copyright lowRISC contributors. +-// Licensed under the Apache License, Version 2.0, see LICENSE for details. +-// SPDX-License-Identifier: Apache-2.0 ++// Copyright 2024 ETH Zurich and University of Bologna. ++// Solderpad Hardware License, Version 0.51, see LICENSE for details. ++// SPDX-License-Identifier: SHL-0.51 + // + // Register Package auto-generated by `reggen` containing data structure + <% +@@ -344,4 +344,3 @@ ${reg_data_for_iface(iface_name, iface_desc, for_iface, rb)}\ + % endfor + + endpackage +- +diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl +index bfab87f..2b2764e 100644 +--- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl ++++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl +@@ -1,6 +1,6 @@ +-// Copyright lowRISC contributors. +-// Licensed under the Apache License, Version 2.0, see LICENSE for details. +-// SPDX-License-Identifier: Apache-2.0 ++// Copyright 2024 ETH Zurich and University of Bologna. ++// Solderpad Hardware License, Version 0.51, see LICENSE for details. ++// SPDX-License-Identifier: SHL-0.51 + // + // Register Top module auto-generated by `reggen` + <% +@@ -534,6 +534,7 @@ ${rdata_gen(f, r.name.lower() + "_" + f.name.lower())}\ + endmodule + + % if use_reg_iface: ++/* verilator lint_off DECLFILENAME */ + module ${mod_name}_intf + #( + parameter int AW = ${addr_width}, +@@ -568,7 +569,7 @@ module ${mod_name}_intf + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; +- ++ + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) +@@ -580,9 +581,9 @@ module ${mod_name}_intf + `REG_BUS_ASSIGN_TO_REQ(s_reg_win_req[i], regbus_win_mst[i]) + `REG_BUS_ASSIGN_FROM_RSP(regbus_win_mst[i], s_reg_win_rsp[i]) + end +- ++ + % endif +- ++ + + ${mod_name} #( + .reg_req_t(reg_bus_req_t), +@@ -605,11 +606,10 @@ module ${mod_name}_intf + % endif + .devmode_i + ); +- +-endmodule + ++endmodule ++/* verilator lint_on DECLFILENAME */ + % endif +- + <%def name="str_bits_sv(bits)">\ + % if bits.msb != bits.lsb: + ${bits.msb}:${bits.lsb}\ +diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py +index f7e117a..767c839 100755 +--- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py ++++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py +@@ -210,7 +210,7 @@ def main(): + found_lunder = None + copy = re.compile(r'.*(copyright.*)|(.*\(c\).*)', re.IGNORECASE) + spdx = re.compile(r'.*(SPDX-License-Identifier:.+)') +- lunder = re.compile(r'.*(Licensed under.+)', re.IGNORECASE) ++ lunder = re.compile(r'.*(Solderpad.*)|(Apache.*)', re.IGNORECASE) + for line in srcfull.splitlines(): + mat = copy.match(line) + if mat is not None: +@@ -225,7 +225,7 @@ def main(): + src_lic = found_lunder + if found_spdx: + if src_lic is None: +- src_lic = '\n' + found_spdx ++ src_lic = found_spdx + else: + src_lic += '\n' + found_spdx + diff --git a/hardware/src/control_registers/Makefile b/hardware/src/control_registers/Makefile new file mode 100644 index 000000000..84d1d6319 --- /dev/null +++ b/hardware/src/control_registers/Makefile @@ -0,0 +1,32 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Samuel Riedel + +SHELL = /usr/bin/env bash +ROOT_DIR := $(patsubst %/,%, $(dir $(abspath $(lastword $(MAKEFILE_LIST))))) +RUNTIME_DIR := $(abspath $(ROOT_DIR)/../../../software/runtime) + +regtool ?= $(abspath $(ROOT_DIR)/../../deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py) + +RTL := $(patsubst $(ROOT_DIR)/%.hjson,%,$(shell find $(ROOT_DIR) -name "*.hjson")) + +all: $(RTL)_reg_top.sv $(RUNTIME_DIR)/$(RTL).h + +$(RTL)_reg_top.sv: %_reg_top.sv: %.hjson + $(regtool) $^ -r -t $(ROOT_DIR) + +$(RUNTIME_DIR)/$(RTL).h: $(RUNTIME_DIR)/%.h: %.hjson + $(regtool) $^ -D -o $@ + +$(RTL).html: %.html: %.hjson + $(regtool) $^ -d -o $@ + +clean: + @rm -fv $(RTL)_reg_pkg.sv + @rm -fv $(RTL)_reg_top.sv + @rm -fv $(RTL).html + @rm -fv $(RUNTIME_DIR)/$(RTL).h + +.EXTRA_PREREQS:= $(abspath $(lastword $(MAKEFILE_LIST))) diff --git a/hardware/src/control_registers/control_registers.hjson b/hardware/src/control_registers/control_registers.hjson new file mode 100644 index 000000000..dc1aebe42 --- /dev/null +++ b/hardware/src/control_registers/control_registers.hjson @@ -0,0 +1,126 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +{ + name: "control_registers" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface" + direction: "device" + } + ] + param_list: [ + { name: "ROCacheNumAddrRules", + desc: "Number of programmable address regions for the read-only cache", + type: "int", + default: "4" + }, + { name: "MAX_NumGroups", + desc: "Maximum number of groups that we support in any configuration", + type: "int", + default: "8" + } + ], + regwidth: 32 + registers: [ + { name: "eoc" + desc: "End-of-Computation Register" + swaccess: "rw" + hwaccess: "hro" + fields: [{ bits: "31:0" }] + }, + { name: "wake_up" + desc: "Wake Up Register" + swaccess: "wo" + hwaccess: "hro" + hwqe: "true" + fields: [{ bits: "31:0" }] + }, + { multireg: + { + name: "wake_up_tile" + desc: "Wake Up Tile Register" + swaccess: "wo" + hwaccess: "hro" + hwqe: "true" + count: "MAX_NumGroups" + cname: "wake_up_tile" + fields: [{ bits: "31:0" }] + }, + }, + { name: "wake_up_group" + desc: "Wake Up Group Register" + swaccess: "wo" + hwaccess: "hro" + hwqe: "true" + fields: [{ bits: "31:0" }] + }, + { name: "tcdm_start_address" + desc: "TCDM Start Address Register" + swaccess: "ro" + hwaccess: "hwo" + // External because we want to define the reset from a parameter + hwext: "true" + fields: [{ bits: "31:0" }] + }, + { name: "tcdm_end_address" + desc: "TCDM End Address Register" + swaccess: "ro" + hwaccess: "hwo" + // External because we want to define the reset from a parameter + hwext: "true" + fields: [{ bits: "31:0" }] + }, + { name: "nr_cores_reg" + desc: "Number of Cores Register" + swaccess: "ro" + hwaccess: "hwo" + // External because we want to define the reset from a parameter + hwext: "true" + fields: [{ bits: "31:0" }] + }, + { name: "ro_cache_enable" + desc: "Read-only cache Enable" + swaccess: "rw" + hwaccess: "hro" + resval: "1" + fields: [{ bits: "31:0" }] + }, + { name: "ro_cache_flush" + desc: "Read-only cache Flush" + swaccess: "rw" + hwaccess: "hro" + fields: [{ bits: "31:0" }] + }, + { multireg: + { + name: "ro_cache_start" + desc: "Read-only cache Region Start" + swaccess: "rw" + hwaccess: "hrw" + hwqe: "true" + // External because we want to define the reset from a parameter + hwext: "true" + count: "ROCacheNumAddrRules" + cname: "ro_cache_start" + fields: [{ bits: "31:0" }] + }, + }, + { multireg: + { + name: "ro_cache_end" + desc: "Read-only cache Region End" + swaccess: "rw" + hwaccess: "hrw" + hwqe: "true" + // External because we want to define the reset from a parameter + hwext: "true" + count: "ROCacheNumAddrRules" + cname: "ro_cache_end" + fields: [{ bits: "31:0" }] + } + } + ] +} diff --git a/hardware/src/control_registers/control_registers_reg_pkg.sv b/hardware/src/control_registers/control_registers_reg_pkg.sv new file mode 100644 index 000000000..3a44033a3 --- /dev/null +++ b/hardware/src/control_registers/control_registers_reg_pkg.sv @@ -0,0 +1,193 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Register Package auto-generated by `reggen` containing data structure + +package control_registers_reg_pkg; + + // Param list + parameter int ROCacheNumAddrRules = 4; + parameter int MAX_NumGroups = 8; + + // Address widths within the block + parameter int BlockAw = 7; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic [31:0] q; + } control_registers_reg2hw_eoc_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } control_registers_reg2hw_wake_up_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } control_registers_reg2hw_wake_up_tile_mreg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } control_registers_reg2hw_wake_up_group_reg_t; + + typedef struct packed { + logic [31:0] q; + } control_registers_reg2hw_ro_cache_enable_reg_t; + + typedef struct packed { + logic [31:0] q; + } control_registers_reg2hw_ro_cache_flush_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } control_registers_reg2hw_ro_cache_start_mreg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } control_registers_reg2hw_ro_cache_end_mreg_t; + + typedef struct packed { + logic [31:0] d; + } control_registers_hw2reg_tcdm_start_address_reg_t; + + typedef struct packed { + logic [31:0] d; + } control_registers_hw2reg_tcdm_end_address_reg_t; + + typedef struct packed { + logic [31:0] d; + } control_registers_hw2reg_nr_cores_reg_reg_t; + + typedef struct packed { + logic [31:0] d; + } control_registers_hw2reg_ro_cache_start_mreg_t; + + typedef struct packed { + logic [31:0] d; + } control_registers_hw2reg_ro_cache_end_mreg_t; + + // Register -> HW type + typedef struct packed { + control_registers_reg2hw_eoc_reg_t eoc; // [689:658] + control_registers_reg2hw_wake_up_reg_t wake_up; // [657:625] + control_registers_reg2hw_wake_up_tile_mreg_t [7:0] wake_up_tile; // [624:361] + control_registers_reg2hw_wake_up_group_reg_t wake_up_group; // [360:328] + control_registers_reg2hw_ro_cache_enable_reg_t ro_cache_enable; // [327:296] + control_registers_reg2hw_ro_cache_flush_reg_t ro_cache_flush; // [295:264] + control_registers_reg2hw_ro_cache_start_mreg_t [3:0] ro_cache_start; // [263:132] + control_registers_reg2hw_ro_cache_end_mreg_t [3:0] ro_cache_end; // [131:0] + } control_registers_reg2hw_t; + + // HW -> register type + typedef struct packed { + control_registers_hw2reg_tcdm_start_address_reg_t tcdm_start_address; // [351:320] + control_registers_hw2reg_tcdm_end_address_reg_t tcdm_end_address; // [319:288] + control_registers_hw2reg_nr_cores_reg_reg_t nr_cores_reg; // [287:256] + control_registers_hw2reg_ro_cache_start_mreg_t [3:0] ro_cache_start; // [255:128] + control_registers_hw2reg_ro_cache_end_mreg_t [3:0] ro_cache_end; // [127:0] + } control_registers_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_EOC_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_0_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_1_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_2_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_3_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_4_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_5_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_6_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_7_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_GROUP_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_TCDM_START_ADDRESS_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_TCDM_END_ADDRESS_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_NR_CORES_REG_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_ENABLE_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_FLUSH_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_0_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_1_OFFSET = 7'h 44; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_2_OFFSET = 7'h 48; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_3_OFFSET = 7'h 4c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_0_OFFSET = 7'h 50; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_1_OFFSET = 7'h 54; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_2_OFFSET = 7'h 58; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_3_OFFSET = 7'h 5c; + + // Reset values for hwext registers and their fields + parameter logic [31:0] CONTROL_REGISTERS_TCDM_START_ADDRESS_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_TCDM_END_ADDRESS_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_NR_CORES_REG_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_RO_CACHE_START_0_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_RO_CACHE_START_1_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_RO_CACHE_START_2_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_RO_CACHE_START_3_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_RO_CACHE_END_0_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_RO_CACHE_END_1_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_RO_CACHE_END_2_RESVAL = 32'h 0; + parameter logic [31:0] CONTROL_REGISTERS_RO_CACHE_END_3_RESVAL = 32'h 0; + + // Register index + typedef enum int { + CONTROL_REGISTERS_EOC, + CONTROL_REGISTERS_WAKE_UP, + CONTROL_REGISTERS_WAKE_UP_TILE_0, + CONTROL_REGISTERS_WAKE_UP_TILE_1, + CONTROL_REGISTERS_WAKE_UP_TILE_2, + CONTROL_REGISTERS_WAKE_UP_TILE_3, + CONTROL_REGISTERS_WAKE_UP_TILE_4, + CONTROL_REGISTERS_WAKE_UP_TILE_5, + CONTROL_REGISTERS_WAKE_UP_TILE_6, + CONTROL_REGISTERS_WAKE_UP_TILE_7, + CONTROL_REGISTERS_WAKE_UP_GROUP, + CONTROL_REGISTERS_TCDM_START_ADDRESS, + CONTROL_REGISTERS_TCDM_END_ADDRESS, + CONTROL_REGISTERS_NR_CORES_REG, + CONTROL_REGISTERS_RO_CACHE_ENABLE, + CONTROL_REGISTERS_RO_CACHE_FLUSH, + CONTROL_REGISTERS_RO_CACHE_START_0, + CONTROL_REGISTERS_RO_CACHE_START_1, + CONTROL_REGISTERS_RO_CACHE_START_2, + CONTROL_REGISTERS_RO_CACHE_START_3, + CONTROL_REGISTERS_RO_CACHE_END_0, + CONTROL_REGISTERS_RO_CACHE_END_1, + CONTROL_REGISTERS_RO_CACHE_END_2, + CONTROL_REGISTERS_RO_CACHE_END_3 + } control_registers_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] CONTROL_REGISTERS_PERMIT [24] = '{ + 4'b 1111, // index[ 0] CONTROL_REGISTERS_EOC + 4'b 1111, // index[ 1] CONTROL_REGISTERS_WAKE_UP + 4'b 1111, // index[ 2] CONTROL_REGISTERS_WAKE_UP_TILE_0 + 4'b 1111, // index[ 3] CONTROL_REGISTERS_WAKE_UP_TILE_1 + 4'b 1111, // index[ 4] CONTROL_REGISTERS_WAKE_UP_TILE_2 + 4'b 1111, // index[ 5] CONTROL_REGISTERS_WAKE_UP_TILE_3 + 4'b 1111, // index[ 6] CONTROL_REGISTERS_WAKE_UP_TILE_4 + 4'b 1111, // index[ 7] CONTROL_REGISTERS_WAKE_UP_TILE_5 + 4'b 1111, // index[ 8] CONTROL_REGISTERS_WAKE_UP_TILE_6 + 4'b 1111, // index[ 9] CONTROL_REGISTERS_WAKE_UP_TILE_7 + 4'b 1111, // index[10] CONTROL_REGISTERS_WAKE_UP_GROUP + 4'b 1111, // index[11] CONTROL_REGISTERS_TCDM_START_ADDRESS + 4'b 1111, // index[12] CONTROL_REGISTERS_TCDM_END_ADDRESS + 4'b 1111, // index[13] CONTROL_REGISTERS_NR_CORES_REG + 4'b 1111, // index[14] CONTROL_REGISTERS_RO_CACHE_ENABLE + 4'b 1111, // index[15] CONTROL_REGISTERS_RO_CACHE_FLUSH + 4'b 1111, // index[16] CONTROL_REGISTERS_RO_CACHE_START_0 + 4'b 1111, // index[17] CONTROL_REGISTERS_RO_CACHE_START_1 + 4'b 1111, // index[18] CONTROL_REGISTERS_RO_CACHE_START_2 + 4'b 1111, // index[19] CONTROL_REGISTERS_RO_CACHE_START_3 + 4'b 1111, // index[20] CONTROL_REGISTERS_RO_CACHE_END_0 + 4'b 1111, // index[21] CONTROL_REGISTERS_RO_CACHE_END_1 + 4'b 1111, // index[22] CONTROL_REGISTERS_RO_CACHE_END_2 + 4'b 1111 // index[23] CONTROL_REGISTERS_RO_CACHE_END_3 + }; + +endpackage diff --git a/hardware/src/control_registers/control_registers_reg_top.sv b/hardware/src/control_registers/control_registers_reg_top.sv new file mode 100644 index 000000000..76e9e07cb --- /dev/null +++ b/hardware/src/control_registers/control_registers_reg_top.sv @@ -0,0 +1,972 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module control_registers_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 7 +) ( + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output control_registers_reg_pkg::control_registers_reg2hw_t reg2hw, // Write + input control_registers_reg_pkg::control_registers_hw2reg_t hw2reg, // Read + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import control_registers_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [BlockAw-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [31:0] eoc_qs; + logic [31:0] eoc_wd; + logic eoc_we; + logic [31:0] wake_up_wd; + logic wake_up_we; + logic [31:0] wake_up_tile_0_wd; + logic wake_up_tile_0_we; + logic [31:0] wake_up_tile_1_wd; + logic wake_up_tile_1_we; + logic [31:0] wake_up_tile_2_wd; + logic wake_up_tile_2_we; + logic [31:0] wake_up_tile_3_wd; + logic wake_up_tile_3_we; + logic [31:0] wake_up_tile_4_wd; + logic wake_up_tile_4_we; + logic [31:0] wake_up_tile_5_wd; + logic wake_up_tile_5_we; + logic [31:0] wake_up_tile_6_wd; + logic wake_up_tile_6_we; + logic [31:0] wake_up_tile_7_wd; + logic wake_up_tile_7_we; + logic [31:0] wake_up_group_wd; + logic wake_up_group_we; + logic [31:0] tcdm_start_address_qs; + logic tcdm_start_address_re; + logic [31:0] tcdm_end_address_qs; + logic tcdm_end_address_re; + logic [31:0] nr_cores_reg_qs; + logic nr_cores_reg_re; + logic [31:0] ro_cache_enable_qs; + logic [31:0] ro_cache_enable_wd; + logic ro_cache_enable_we; + logic [31:0] ro_cache_flush_qs; + logic [31:0] ro_cache_flush_wd; + logic ro_cache_flush_we; + logic [31:0] ro_cache_start_0_qs; + logic [31:0] ro_cache_start_0_wd; + logic ro_cache_start_0_we; + logic ro_cache_start_0_re; + logic [31:0] ro_cache_start_1_qs; + logic [31:0] ro_cache_start_1_wd; + logic ro_cache_start_1_we; + logic ro_cache_start_1_re; + logic [31:0] ro_cache_start_2_qs; + logic [31:0] ro_cache_start_2_wd; + logic ro_cache_start_2_we; + logic ro_cache_start_2_re; + logic [31:0] ro_cache_start_3_qs; + logic [31:0] ro_cache_start_3_wd; + logic ro_cache_start_3_we; + logic ro_cache_start_3_re; + logic [31:0] ro_cache_end_0_qs; + logic [31:0] ro_cache_end_0_wd; + logic ro_cache_end_0_we; + logic ro_cache_end_0_re; + logic [31:0] ro_cache_end_1_qs; + logic [31:0] ro_cache_end_1_wd; + logic ro_cache_end_1_we; + logic ro_cache_end_1_re; + logic [31:0] ro_cache_end_2_qs; + logic [31:0] ro_cache_end_2_wd; + logic ro_cache_end_2_we; + logic ro_cache_end_2_re; + logic [31:0] ro_cache_end_3_qs; + logic [31:0] ro_cache_end_3_wd; + logic ro_cache_end_3_we; + logic ro_cache_end_3_re; + + // Register instances + // R[eoc]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_eoc ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (eoc_we), + .wd (eoc_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.eoc.q ), + + // to register interface (read) + .qs (eoc_qs) + ); + + + // R[wake_up]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_we), + .wd (wake_up_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up.qe), + .q (reg2hw.wake_up.q ), + + .qs () + ); + + + + // Subregister 0 of Multireg wake_up_tile + // R[wake_up_tile_0]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_0_we), + .wd (wake_up_tile_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[0].qe), + .q (reg2hw.wake_up_tile[0].q ), + + .qs () + ); + + // Subregister 1 of Multireg wake_up_tile + // R[wake_up_tile_1]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_1_we), + .wd (wake_up_tile_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[1].qe), + .q (reg2hw.wake_up_tile[1].q ), + + .qs () + ); + + // Subregister 2 of Multireg wake_up_tile + // R[wake_up_tile_2]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_2_we), + .wd (wake_up_tile_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[2].qe), + .q (reg2hw.wake_up_tile[2].q ), + + .qs () + ); + + // Subregister 3 of Multireg wake_up_tile + // R[wake_up_tile_3]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_3_we), + .wd (wake_up_tile_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[3].qe), + .q (reg2hw.wake_up_tile[3].q ), + + .qs () + ); + + // Subregister 4 of Multireg wake_up_tile + // R[wake_up_tile_4]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_4_we), + .wd (wake_up_tile_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[4].qe), + .q (reg2hw.wake_up_tile[4].q ), + + .qs () + ); + + // Subregister 5 of Multireg wake_up_tile + // R[wake_up_tile_5]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_5_we), + .wd (wake_up_tile_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[5].qe), + .q (reg2hw.wake_up_tile[5].q ), + + .qs () + ); + + // Subregister 6 of Multireg wake_up_tile + // R[wake_up_tile_6]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_6_we), + .wd (wake_up_tile_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[6].qe), + .q (reg2hw.wake_up_tile[6].q ), + + .qs () + ); + + // Subregister 7 of Multireg wake_up_tile + // R[wake_up_tile_7]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_7_we), + .wd (wake_up_tile_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[7].qe), + .q (reg2hw.wake_up_tile[7].q ), + + .qs () + ); + + + // R[wake_up_group]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_group ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_group_we), + .wd (wake_up_group_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_group.qe), + .q (reg2hw.wake_up_group.q ), + + .qs () + ); + + + // R[tcdm_start_address]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_tcdm_start_address ( + .re (tcdm_start_address_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.tcdm_start_address.d), + .qre (), + .qe (), + .q (), + .qs (tcdm_start_address_qs) + ); + + + // R[tcdm_end_address]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_tcdm_end_address ( + .re (tcdm_end_address_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.tcdm_end_address.d), + .qre (), + .qe (), + .q (), + .qs (tcdm_end_address_qs) + ); + + + // R[nr_cores_reg]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_nr_cores_reg ( + .re (nr_cores_reg_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.nr_cores_reg.d), + .qre (), + .qe (), + .q (), + .qs (nr_cores_reg_qs) + ); + + + // R[ro_cache_enable]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h1) + ) u_ro_cache_enable ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ro_cache_enable_we), + .wd (ro_cache_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ro_cache_enable.q ), + + // to register interface (read) + .qs (ro_cache_enable_qs) + ); + + + // R[ro_cache_flush]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_ro_cache_flush ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (ro_cache_flush_we), + .wd (ro_cache_flush_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ro_cache_flush.q ), + + // to register interface (read) + .qs (ro_cache_flush_qs) + ); + + + + // Subregister 0 of Multireg ro_cache_start + // R[ro_cache_start_0]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_ro_cache_start_0 ( + .re (ro_cache_start_0_re), + .we (ro_cache_start_0_we), + .wd (ro_cache_start_0_wd), + .d (hw2reg.ro_cache_start[0].d), + .qre (), + .qe (reg2hw.ro_cache_start[0].qe), + .q (reg2hw.ro_cache_start[0].q ), + .qs (ro_cache_start_0_qs) + ); + + // Subregister 1 of Multireg ro_cache_start + // R[ro_cache_start_1]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_ro_cache_start_1 ( + .re (ro_cache_start_1_re), + .we (ro_cache_start_1_we), + .wd (ro_cache_start_1_wd), + .d (hw2reg.ro_cache_start[1].d), + .qre (), + .qe (reg2hw.ro_cache_start[1].qe), + .q (reg2hw.ro_cache_start[1].q ), + .qs (ro_cache_start_1_qs) + ); + + // Subregister 2 of Multireg ro_cache_start + // R[ro_cache_start_2]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_ro_cache_start_2 ( + .re (ro_cache_start_2_re), + .we (ro_cache_start_2_we), + .wd (ro_cache_start_2_wd), + .d (hw2reg.ro_cache_start[2].d), + .qre (), + .qe (reg2hw.ro_cache_start[2].qe), + .q (reg2hw.ro_cache_start[2].q ), + .qs (ro_cache_start_2_qs) + ); + + // Subregister 3 of Multireg ro_cache_start + // R[ro_cache_start_3]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_ro_cache_start_3 ( + .re (ro_cache_start_3_re), + .we (ro_cache_start_3_we), + .wd (ro_cache_start_3_wd), + .d (hw2reg.ro_cache_start[3].d), + .qre (), + .qe (reg2hw.ro_cache_start[3].qe), + .q (reg2hw.ro_cache_start[3].q ), + .qs (ro_cache_start_3_qs) + ); + + + + // Subregister 0 of Multireg ro_cache_end + // R[ro_cache_end_0]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_ro_cache_end_0 ( + .re (ro_cache_end_0_re), + .we (ro_cache_end_0_we), + .wd (ro_cache_end_0_wd), + .d (hw2reg.ro_cache_end[0].d), + .qre (), + .qe (reg2hw.ro_cache_end[0].qe), + .q (reg2hw.ro_cache_end[0].q ), + .qs (ro_cache_end_0_qs) + ); + + // Subregister 1 of Multireg ro_cache_end + // R[ro_cache_end_1]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_ro_cache_end_1 ( + .re (ro_cache_end_1_re), + .we (ro_cache_end_1_we), + .wd (ro_cache_end_1_wd), + .d (hw2reg.ro_cache_end[1].d), + .qre (), + .qe (reg2hw.ro_cache_end[1].qe), + .q (reg2hw.ro_cache_end[1].q ), + .qs (ro_cache_end_1_qs) + ); + + // Subregister 2 of Multireg ro_cache_end + // R[ro_cache_end_2]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_ro_cache_end_2 ( + .re (ro_cache_end_2_re), + .we (ro_cache_end_2_we), + .wd (ro_cache_end_2_wd), + .d (hw2reg.ro_cache_end[2].d), + .qre (), + .qe (reg2hw.ro_cache_end[2].qe), + .q (reg2hw.ro_cache_end[2].q ), + .qs (ro_cache_end_2_qs) + ); + + // Subregister 3 of Multireg ro_cache_end + // R[ro_cache_end_3]: V(True) + + prim_subreg_ext #( + .DW (32) + ) u_ro_cache_end_3 ( + .re (ro_cache_end_3_re), + .we (ro_cache_end_3_we), + .wd (ro_cache_end_3_wd), + .d (hw2reg.ro_cache_end[3].d), + .qre (), + .qe (reg2hw.ro_cache_end[3].qe), + .q (reg2hw.ro_cache_end[3].q ), + .qs (ro_cache_end_3_qs) + ); + + + + + logic [23:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == CONTROL_REGISTERS_EOC_OFFSET); + addr_hit[ 1] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_OFFSET); + addr_hit[ 2] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_0_OFFSET); + addr_hit[ 3] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_1_OFFSET); + addr_hit[ 4] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_2_OFFSET); + addr_hit[ 5] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_3_OFFSET); + addr_hit[ 6] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_4_OFFSET); + addr_hit[ 7] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_5_OFFSET); + addr_hit[ 8] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_6_OFFSET); + addr_hit[ 9] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_7_OFFSET); + addr_hit[10] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_GROUP_OFFSET); + addr_hit[11] = (reg_addr == CONTROL_REGISTERS_TCDM_START_ADDRESS_OFFSET); + addr_hit[12] = (reg_addr == CONTROL_REGISTERS_TCDM_END_ADDRESS_OFFSET); + addr_hit[13] = (reg_addr == CONTROL_REGISTERS_NR_CORES_REG_OFFSET); + addr_hit[14] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_ENABLE_OFFSET); + addr_hit[15] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_FLUSH_OFFSET); + addr_hit[16] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_0_OFFSET); + addr_hit[17] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_1_OFFSET); + addr_hit[18] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_2_OFFSET); + addr_hit[19] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_3_OFFSET); + addr_hit[20] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_0_OFFSET); + addr_hit[21] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_1_OFFSET); + addr_hit[22] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_2_OFFSET); + addr_hit[23] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_3_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(CONTROL_REGISTERS_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(CONTROL_REGISTERS_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(CONTROL_REGISTERS_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(CONTROL_REGISTERS_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(CONTROL_REGISTERS_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(CONTROL_REGISTERS_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(CONTROL_REGISTERS_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(CONTROL_REGISTERS_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(CONTROL_REGISTERS_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(CONTROL_REGISTERS_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(CONTROL_REGISTERS_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(CONTROL_REGISTERS_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(CONTROL_REGISTERS_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(CONTROL_REGISTERS_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(CONTROL_REGISTERS_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(CONTROL_REGISTERS_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(CONTROL_REGISTERS_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(CONTROL_REGISTERS_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(CONTROL_REGISTERS_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(CONTROL_REGISTERS_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(CONTROL_REGISTERS_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(CONTROL_REGISTERS_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(CONTROL_REGISTERS_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(CONTROL_REGISTERS_PERMIT[23] & ~reg_be))))); + end + + assign eoc_we = addr_hit[0] & reg_we & !reg_error; + assign eoc_wd = reg_wdata[31:0]; + + assign wake_up_we = addr_hit[1] & reg_we & !reg_error; + assign wake_up_wd = reg_wdata[31:0]; + + assign wake_up_tile_0_we = addr_hit[2] & reg_we & !reg_error; + assign wake_up_tile_0_wd = reg_wdata[31:0]; + + assign wake_up_tile_1_we = addr_hit[3] & reg_we & !reg_error; + assign wake_up_tile_1_wd = reg_wdata[31:0]; + + assign wake_up_tile_2_we = addr_hit[4] & reg_we & !reg_error; + assign wake_up_tile_2_wd = reg_wdata[31:0]; + + assign wake_up_tile_3_we = addr_hit[5] & reg_we & !reg_error; + assign wake_up_tile_3_wd = reg_wdata[31:0]; + + assign wake_up_tile_4_we = addr_hit[6] & reg_we & !reg_error; + assign wake_up_tile_4_wd = reg_wdata[31:0]; + + assign wake_up_tile_5_we = addr_hit[7] & reg_we & !reg_error; + assign wake_up_tile_5_wd = reg_wdata[31:0]; + + assign wake_up_tile_6_we = addr_hit[8] & reg_we & !reg_error; + assign wake_up_tile_6_wd = reg_wdata[31:0]; + + assign wake_up_tile_7_we = addr_hit[9] & reg_we & !reg_error; + assign wake_up_tile_7_wd = reg_wdata[31:0]; + + assign wake_up_group_we = addr_hit[10] & reg_we & !reg_error; + assign wake_up_group_wd = reg_wdata[31:0]; + + assign tcdm_start_address_re = addr_hit[11] & reg_re & !reg_error; + + assign tcdm_end_address_re = addr_hit[12] & reg_re & !reg_error; + + assign nr_cores_reg_re = addr_hit[13] & reg_re & !reg_error; + + assign ro_cache_enable_we = addr_hit[14] & reg_we & !reg_error; + assign ro_cache_enable_wd = reg_wdata[31:0]; + + assign ro_cache_flush_we = addr_hit[15] & reg_we & !reg_error; + assign ro_cache_flush_wd = reg_wdata[31:0]; + + assign ro_cache_start_0_we = addr_hit[16] & reg_we & !reg_error; + assign ro_cache_start_0_wd = reg_wdata[31:0]; + assign ro_cache_start_0_re = addr_hit[16] & reg_re & !reg_error; + + assign ro_cache_start_1_we = addr_hit[17] & reg_we & !reg_error; + assign ro_cache_start_1_wd = reg_wdata[31:0]; + assign ro_cache_start_1_re = addr_hit[17] & reg_re & !reg_error; + + assign ro_cache_start_2_we = addr_hit[18] & reg_we & !reg_error; + assign ro_cache_start_2_wd = reg_wdata[31:0]; + assign ro_cache_start_2_re = addr_hit[18] & reg_re & !reg_error; + + assign ro_cache_start_3_we = addr_hit[19] & reg_we & !reg_error; + assign ro_cache_start_3_wd = reg_wdata[31:0]; + assign ro_cache_start_3_re = addr_hit[19] & reg_re & !reg_error; + + assign ro_cache_end_0_we = addr_hit[20] & reg_we & !reg_error; + assign ro_cache_end_0_wd = reg_wdata[31:0]; + assign ro_cache_end_0_re = addr_hit[20] & reg_re & !reg_error; + + assign ro_cache_end_1_we = addr_hit[21] & reg_we & !reg_error; + assign ro_cache_end_1_wd = reg_wdata[31:0]; + assign ro_cache_end_1_re = addr_hit[21] & reg_re & !reg_error; + + assign ro_cache_end_2_we = addr_hit[22] & reg_we & !reg_error; + assign ro_cache_end_2_wd = reg_wdata[31:0]; + assign ro_cache_end_2_re = addr_hit[22] & reg_re & !reg_error; + + assign ro_cache_end_3_we = addr_hit[23] & reg_we & !reg_error; + assign ro_cache_end_3_wd = reg_wdata[31:0]; + assign ro_cache_end_3_re = addr_hit[23] & reg_re & !reg_error; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = eoc_qs; + end + + addr_hit[1]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[2]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[4]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[5]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[6]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[7]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[8]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[9]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[10]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[11]: begin + reg_rdata_next[31:0] = tcdm_start_address_qs; + end + + addr_hit[12]: begin + reg_rdata_next[31:0] = tcdm_end_address_qs; + end + + addr_hit[13]: begin + reg_rdata_next[31:0] = nr_cores_reg_qs; + end + + addr_hit[14]: begin + reg_rdata_next[31:0] = ro_cache_enable_qs; + end + + addr_hit[15]: begin + reg_rdata_next[31:0] = ro_cache_flush_qs; + end + + addr_hit[16]: begin + reg_rdata_next[31:0] = ro_cache_start_0_qs; + end + + addr_hit[17]: begin + reg_rdata_next[31:0] = ro_cache_start_1_qs; + end + + addr_hit[18]: begin + reg_rdata_next[31:0] = ro_cache_start_2_qs; + end + + addr_hit[19]: begin + reg_rdata_next[31:0] = ro_cache_start_3_qs; + end + + addr_hit[20]: begin + reg_rdata_next[31:0] = ro_cache_end_0_qs; + end + + addr_hit[21]: begin + reg_rdata_next[31:0] = ro_cache_end_1_qs; + end + + addr_hit[22]: begin + reg_rdata_next[31:0] = ro_cache_end_2_qs; + end + + addr_hit[23]: begin + reg_rdata_next[31:0] = ro_cache_end_3_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule + +/* verilator lint_off DECLFILENAME */ +module control_registers_reg_top_intf +#( + parameter int AW = 7, + localparam int DW = 32 +) ( + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output control_registers_reg_pkg::control_registers_reg2hw_t reg2hw, // Write + input control_registers_reg_pkg::control_registers_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + localparam int unsigned STRB_WIDTH = DW/8; + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + // Define structs for reg_bus + typedef logic [AW-1:0] addr_t; + typedef logic [DW-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) + + + + control_registers_reg_top #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) + ) i_regs ( + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i + ); + +endmodule +/* verilator lint_on DECLFILENAME */ diff --git a/hardware/src/ctrl_registers.sv b/hardware/src/ctrl_registers.sv index 189c76fc0..3e35434a4 100644 --- a/hardware/src/ctrl_registers.sv +++ b/hardware/src/ctrl_registers.sv @@ -3,12 +3,12 @@ // SPDX-License-Identifier: SHL-0.51 `include "common_cells/registers.svh" +`include "register_interface/typedef.svh" module ctrl_registers import mempool_pkg::ro_cache_ctrl_t; #( parameter int DataWidth = 32, - parameter int NumRegs = 0, // Parameters parameter logic [DataWidth-1:0] TCDMBaseAddr = 0, parameter logic [DataWidth-1:0] TCDMSize = 0, @@ -26,195 +26,142 @@ module ctrl_registers output logic [DataWidth-1:0] eoc_o, output logic eoc_valid_o, output logic [NumCores-1:0] wake_up_o, - output logic [DataWidth-1:0] tcdm_start_address_o, - output logic [DataWidth-1:0] tcdm_end_address_o, - output logic [DataWidth-1:0] num_cores_o, output ro_cache_ctrl_t ro_cache_ctrl_o ); - import mempool_pkg::*; - - /***************** - * Definitions * - *****************/ - - localparam int unsigned DataWidthInBytes = (DataWidth + 7) / 8; - localparam int unsigned RegNumBytes = NumRegs * DataWidthInBytes; - localparam int unsigned RegDataWidth = NumRegs * DataWidth; - - localparam logic [DataWidthInBytes-1:0] ReadOnlyReg = {DataWidthInBytes{1'b1}}; - localparam logic [DataWidthInBytes-1:0] ReadWriteReg = {DataWidthInBytes{1'b0}}; - - // Memory map - // [3 :0 ]:eoc_reg (rw) - // [7 :4 ]:wake_up_reg (rw) - // [11:8 ]:wake_up_group_reg (rw) - // [15:12]:tcdm_start_adress_reg (ro) - // [19:16]:tcdm_end_address_reg (ro) - // [23:20]:nr_cores_address_reg (ro) - // [27:24]:ro_cache_enable (rw) - // [31:28]:ro_cache_flush (rw) - // [35:32]:ro_cache_start_0 (rw) - // [39:36]:ro_cache_end_0 (rw) - // [43:40]:ro_cache_start_1 (rw) - // [47:44]:ro_cache_end_1 (rw) - // [51:48]:ro_cache_start_2 (rw) - // [55:52]:ro_cache_end_2 (rw) - // [59:56]:ro_cache_start_3 (rw) - // [63:60]:ro_cache_end_3 (rw) - - // [95:64]:wake_up_tile[7:0] (rw) - - localparam logic [MAX_NumGroups*DataWidth-1:0] RegRstVal_TileWakeUp = '{MAX_NumGroups*DataWidth{1'b0}}; - localparam logic [NumRegs-MAX_NumGroups-1:0][DataWidth-1:0] RegRstVal = '{ - 32'h0000_0010, - 32'h0000_000C, - 32'h0000_000C, - 32'h0000_0008, - 32'hA000_1000, - 32'hA000_0000, - 32'h8000_1000, - 32'h8000_0000, - {DataWidth{1'b0}}, - 32'h1, - NumCores, - TCDMBaseAddr + TCDMSize, - TCDMBaseAddr, - {DataWidth{1'b0}}, - {DataWidth{1'b0}}, - {DataWidth{1'b0}} - }; - - localparam logic [MAX_NumGroups-1:0][DataWidthInBytes-1:0] AxiReadOnly_TileWakeUp = '{MAX_NumGroups{ReadWriteReg}}; - localparam logic [NumRegs-MAX_NumGroups-1:0][DataWidthInBytes-1:0] AxiReadOnly = '{ - ReadWriteReg, - ReadWriteReg, - ReadWriteReg, - ReadWriteReg, - ReadWriteReg, - ReadWriteReg, - ReadWriteReg, - ReadWriteReg, - ReadWriteReg, - ReadWriteReg, - ReadOnlyReg, - ReadOnlyReg, - ReadOnlyReg, - ReadWriteReg, - ReadWriteReg, - ReadWriteReg - }; + import mempool_pkg::AddrWidth; + import control_registers_reg_pkg::*; /*************** * Registers * ***************/ - logic [DataWidth-1:0] eoc; - logic [DataWidth-1:0] wake_up; - logic [DataWidth-1:0] wake_up_group; - logic [DataWidth-1:0] tcdm_start_address; - logic [DataWidth-1:0] tcdm_end_address; - logic [DataWidth-1:0] num_cores; - logic [DataWidth-1:0] ro_cache_enable; - logic [DataWidth-1:0] ro_cache_flush; - logic [DataWidth-1:0] ro_cache_start_0; - logic [DataWidth-1:0] ro_cache_end_0; - logic [DataWidth-1:0] ro_cache_start_1; - logic [DataWidth-1:0] ro_cache_end_1; - logic [DataWidth-1:0] ro_cache_start_2; - logic [DataWidth-1:0] ro_cache_end_2; - logic [DataWidth-1:0] ro_cache_start_3; - logic [DataWidth-1:0] ro_cache_end_3; - logic [MAX_NumGroups*DataWidth-1:0] wake_up_tile; - - logic [RegNumBytes-1:0] wr_active_d; - logic [RegNumBytes-1:0] wr_active_q; - - axi_lite_regs #( - .RegNumBytes (RegNumBytes ), - .AxiAddrWidth(AddrWidth ), - .AxiDataWidth(AxiLiteDataWidth ), - .AxiReadOnly ({AxiReadOnly_TileWakeUp, AxiReadOnly} ), - .RegRstVal ({RegRstVal_TileWakeUp, RegRstVal} ), - .req_lite_t (axi_lite_req_t ), - .resp_lite_t (axi_lite_resp_t ) - ) i_axi_lite_regs ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .axi_req_i (axi_lite_slave_req_i ), - .axi_resp_o (axi_lite_slave_resp_o ), - .wr_active_o(wr_active_d ), - .rd_active_o(/* Unused */ ), - .reg_d_i ('0 ), - .reg_load_i ('0 ), - .reg_q_o ({ wake_up_tile, - ro_cache_end_3, ro_cache_start_3, - ro_cache_end_2, ro_cache_start_2, - ro_cache_end_1, ro_cache_start_1, - ro_cache_end_0, ro_cache_start_0, - ro_cache_flush, ro_cache_enable, - num_cores, tcdm_end_address, tcdm_start_address, wake_up_group, wake_up, eoc }) + `REG_BUS_TYPEDEF_ALL(ctrl_reg, logic[AddrWidth-1:0], logic[DataWidth-1:0], logic[DataWidth/8-1:0]); + ctrl_reg_req_t ctrl_reg_req; + ctrl_reg_rsp_t ctrl_reg_rsp; + control_registers_reg2hw_t ctrl_reg2hw; + control_registers_hw2reg_t ctrl_hw2reg; + + axi_lite_to_reg #( + .ADDR_WIDTH (AddrWidth ), + .DATA_WIDTH (DataWidth ), + .BUFFER_DEPTH (1 ), + .DECOUPLE_W (0 ), + .axi_lite_req_t(axi_lite_req_t ), + .axi_lite_rsp_t(axi_lite_resp_t), + .reg_req_t (ctrl_reg_req_t ), + .reg_rsp_t (ctrl_reg_rsp_t ) + ) i_axi_lite_to_reg ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .axi_lite_req_i(axi_lite_slave_req_i ), + .axi_lite_rsp_o(axi_lite_slave_resp_o), + .reg_req_o (ctrl_reg_req ), + .reg_rsp_i (ctrl_reg_rsp ) ); - /*************** - * Signals * - ***************/ + control_registers_reg_top #( + .reg_req_t(ctrl_reg_req_t), + .reg_rsp_t(ctrl_reg_rsp_t) + ) i_control_registers_reg_top ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .reg_req_i(ctrl_reg_req), + .reg_rsp_o(ctrl_reg_rsp), + .reg2hw (ctrl_reg2hw ), + .hw2reg (ctrl_hw2reg ), + .devmode_i(1'b0 ) + ); - assign eoc_o = eoc >> 1; - assign tcdm_start_address_o = tcdm_start_address; - assign tcdm_end_address_o = tcdm_end_address; - assign num_cores_o = num_cores; - - assign ro_cache_ctrl_o.enable = ro_cache_enable[0]; - assign ro_cache_ctrl_o.flush_valid = ro_cache_flush[0]; - assign ro_cache_ctrl_o.start_addr[0] = ro_cache_start_0; - assign ro_cache_ctrl_o.start_addr[1] = ro_cache_start_1; - assign ro_cache_ctrl_o.start_addr[2] = ro_cache_start_2; - assign ro_cache_ctrl_o.start_addr[3] = ro_cache_start_3; - assign ro_cache_ctrl_o.end_addr[0] = ro_cache_end_0; - assign ro_cache_ctrl_o.end_addr[1] = ro_cache_end_1; - assign ro_cache_ctrl_o.end_addr[2] = ro_cache_end_2; - assign ro_cache_ctrl_o.end_addr[3] = ro_cache_end_3; + /************************ + * External Registers * + ************************/ + // These registers have hardcoded values (read-only) + assign ctrl_hw2reg.nr_cores_reg.d = NumCores; + assign ctrl_hw2reg.tcdm_start_address.d = TCDMBaseAddr; + assign ctrl_hw2reg.tcdm_end_address.d = TCDMBaseAddr + TCDMSize; + + // These registers are external because they have special reset values. But they are read and + // write so we need to instantiate an actual register + typedef struct packed { + logic [AddrWidth-1:0] start_addr; + logic [AddrWidth-1:0] end_addr; + } ro_cache_region_t; + ro_cache_region_t [ROCacheNumAddrRules-1:0] ro_cache_regions; + assign ro_cache_regions = '{ + '{start_addr: 32'h0000_000C, end_addr: 32'h0000_0010}, + '{start_addr: 32'h0000_0008, end_addr: 32'h0000_000C}, + '{start_addr: 32'hA000_0000, end_addr: 32'hA000_1000}, + '{start_addr: 32'h8000_0000, end_addr: 32'h8000_1000} + }; + for (genvar i = 0; i < ROCacheNumAddrRules; i++) begin : gen_ro_cache_reg + `FFL(ctrl_hw2reg.ro_cache_start[i].d, ctrl_reg2hw.ro_cache_start[i].q, ctrl_reg2hw.ro_cache_start[i].qe, ro_cache_regions[i].start_addr) + `FFL(ctrl_hw2reg.ro_cache_end[i].d, ctrl_reg2hw.ro_cache_end[i].q, ctrl_reg2hw.ro_cache_end[i].qe, ro_cache_regions[i].end_addr) + end + + /************************ + * Wakeup Pulse Logic * + ************************/ + import mempool_pkg::NumCoresPerGroup; + import mempool_pkg::NumCoresPerTile; + import mempool_pkg::NumTilesPerGroup; + import mempool_pkg::NumGroups; + + // Delay the write-enable signal by one cycle so it arrives + // simultaneously with the registered values + logic wake_up_pulse; + logic [MAX_NumGroups-1:0] wake_up_tile_pulse; + logic wake_up_group_pulse; + + `FF(wake_up_pulse, ctrl_reg2hw.wake_up.qe, '0) + for (genvar i = 0; i < MAX_NumGroups; i++) begin : gen_wake_up_tile_reg + `FF(wake_up_tile_pulse[i], ctrl_reg2hw.wake_up_tile[i].qe, '0) + end + `FF(wake_up_group_pulse, ctrl_reg2hw.wake_up_group.qe, '0) always_comb begin wake_up_o = '0; - // converts 32 bit wake up to 256 bit - if (wr_active_q[7:4]) begin - if (wake_up < NumCores) begin - wake_up_o = 1 << wake_up; - end else if (wake_up == {DataWidth{1'b1}}) begin + // converts 32-bit core wake-up into a 'NumCores'-bit mask + if (wake_up_pulse) begin + if (ctrl_reg2hw.wake_up.q < NumCores) begin + wake_up_o = 1 << ctrl_reg2hw.wake_up.q; + end else begin wake_up_o = {NumCores{1'b1}}; end end - // converts 32 bit group wake up mask to 256 bit core wake up mask - if (wr_active_q[11:8]) begin - if (wake_up_group <= {NumGroups{1'b1}}) begin - for(int i = 0; i < NumGroups; i = i + 1) begin - wake_up_o[NumCoresPerGroup * i +: NumCoresPerGroup] = {NumCoresPerGroup{wake_up_group[i]}}; + // converts 32-bit tile wake-up mask into a 'NumCores'-bit mask + for(int g = 0; g < NumGroups; g = g + 1) begin + if (wake_up_tile_pulse[g]) begin + if (ctrl_reg2hw.wake_up_tile[g].q <= {NumTilesPerGroup{1'b1}}) begin + for (int t = 0; t < NumTilesPerGroup; t = t + 1) begin + wake_up_o[NumCoresPerGroup * g + NumCoresPerTile * t +: NumCoresPerTile] = {NumCoresPerTile{ctrl_reg2hw.wake_up_tile[g].q[t]}}; + end end - end else if (wake_up_group == {DataWidth{1'b1}}) begin - wake_up_o = {NumCores{1'b1}}; end end - - // converts 32 bit tile wake up mask to 256 bit core wake up mask - for(int i_g = 0; i_g < NumGroups; i_g = i_g + 1) begin - - if (wr_active_q[64 + 4 * i_g +: 4]) begin - if (wake_up_tile[i_g * DataWidth +: DataWidth] <= {NumTilesPerGroup{1'b1}}) begin - for (int i = 0; i < NumTilesPerGroup; i = i + 1) begin - wake_up_o[NumCoresPerGroup * i_g + NumCoresPerTile * i +: NumCoresPerTile] = {NumCoresPerTile{wake_up_tile[i_g * DataWidth + i]}}; - end + // converts 32-bit group wake-up mask into a 'NumCores'-bit mask + if (wake_up_group_pulse) begin + if (ctrl_reg2hw.wake_up_group.q <= {NumGroups{1'b1}}) begin + for(int i = 0; i < NumGroups; i = i + 1) begin + wake_up_o[NumCoresPerGroup * i +: NumCoresPerGroup] = {NumCoresPerGroup{ctrl_reg2hw.wake_up_group.q[i]}}; end + end else if (ctrl_reg2hw.wake_up_group.q == {DataWidth{1'b1}}) begin + wake_up_o = {NumCores{1'b1}}; end - end - end - assign eoc_valid_o = eoc[0]; - - // register to add +1 latency to the wr_active signal - `FF(wr_active_q, wr_active_d, '0, clk_i, rst_ni) + /*********************** + * Output Assignment * + ***********************/ + assign eoc_o = ctrl_reg2hw.eoc.q >> 1; + assign eoc_valid_o = ctrl_reg2hw.eoc.q[0]; + + assign ro_cache_ctrl_o.enable = ctrl_reg2hw.ro_cache_enable.q[0]; + assign ro_cache_ctrl_o.flush_valid = ctrl_reg2hw.ro_cache_flush.q[0]; + for (genvar i = 0; i < ROCacheNumAddrRules; i++) begin : gen_ro_cache_out + assign ro_cache_ctrl_o.start_addr[i] = ctrl_hw2reg.ro_cache_start[i].d; + assign ro_cache_ctrl_o.end_addr[i] = ctrl_hw2reg.ro_cache_end[i].d; + end /****************** * Assertions * @@ -222,4 +169,10 @@ module ctrl_registers if (NumGroups > MAX_NumGroups) $error("[ctrl_registers] Number of groups exceeds the maximum supported."); + if (MAX_NumGroups != mempool_pkg::MAX_NumGroups) + $error("[ctrl_registers] MAX_NumGroups parameter does not match the one from mempool_pkg."); + + if (ROCacheNumAddrRules != mempool_pkg::ROCacheNumAddrRules) + $error("[ctrl_registers] ROCacheNumAddrRules parameter does not match the one from mempool_pkg."); + endmodule : ctrl_registers diff --git a/hardware/src/mempool_system.sv b/hardware/src/mempool_system.sv index 7bddbe17e..b7fbb00d0 100644 --- a/hardware/src/mempool_system.sv +++ b/hardware/src/mempool_system.sv @@ -718,7 +718,6 @@ module mempool_system ); ctrl_registers #( - .NumRegs (16 + 8 ), .TCDMBaseAddr (TCDMBaseAddr ), .TCDMSize (TCDMSize ), .NumCores (NumCores ), @@ -729,13 +728,10 @@ module mempool_system .rst_ni (rst_ni ), .axi_lite_slave_req_i (axi_lite_slv_req[CtrlRegisters] ), .axi_lite_slave_resp_o(axi_lite_slv_resp[CtrlRegisters]), - .ro_cache_ctrl_o (ro_cache_ctrl ), - .tcdm_start_address_o (/* Unused */ ), - .tcdm_end_address_o (/* Unused */ ), - .num_cores_o (/* Unused */ ), - .wake_up_o (wake_up ), .eoc_o (/* Unused */ ), - .eoc_valid_o (eoc_valid_o ) + .eoc_valid_o (eoc_valid_o ), + .wake_up_o (wake_up ), + .ro_cache_ctrl_o (ro_cache_ctrl ) ); mempool_dma #( diff --git a/hardware/tb/verilator/waiver.vlt b/hardware/tb/verilator/waiver.vlt index e52cedca5..2b2b4be24 100644 --- a/hardware/tb/verilator/waiver.vlt +++ b/hardware/tb/verilator/waiver.vlt @@ -25,6 +25,9 @@ lint_off -rule PINCONNECTEMPTY -file "*/deps/*" -match "*" lint_off -rule DECLFILENAME -file "*/deps/*" -match "*" lint_off -rule LITENDIAN -file "*/deps/fpnew/*" -match "*" +// Ignore unused register ports in lowRISC's prims +lint_off -rule PINCONNECTEMPTY -file "*/src/control_registers/*" -match "*" + // Ignore unused RISCV instruction encoding parameters lint_off -rule UNUSED -file "*/deps/snitch/src/riscv_instr.sv" -match "*" diff --git a/scripts/license-checker.hjson b/scripts/license-checker.hjson index eea7ec365..8666e0955 100644 --- a/scripts/license-checker.hjson +++ b/scripts/license-checker.hjson @@ -13,6 +13,7 @@ match_regex: 'true' exclude_paths: [ # Exclude anything that is explicitly mentioned in the README + 'software/runtime/control_registers.h' 'software/runtime/printf*' 'software/runtime/encoding.h' 'software/runtime/mempool_dma_frontend.h' diff --git a/scripts/lint.sh b/scripts/lint.sh index b313feb11..5b321dbe3 100755 --- a/scripts/lint.sh +++ b/scripts/lint.sh @@ -39,6 +39,7 @@ echo "Checking for trailing whitespaces and tabs in unstaged files" git --no-pager diff --check -- \ ':(exclude)**.def' \ ':(exclude)**.patch' \ + ':(exclude)hardware/src/control_registers/*.sv' \ ':(exclude)toolchain/**' \ ':(exclude)software/riscv-tests/**' \ || EXIT_STATUS=$? @@ -47,6 +48,7 @@ echo "Checking for trailing whitespaces and tabs between HEAD and $base" git --no-pager diff --check $base HEAD -- \ ':(exclude)**.def' \ ':(exclude)**.patch' \ + ':(exclude)hardware/src/control_registers/*.sv' \ ':(exclude)toolchain/**' \ ':(exclude)software/riscv-tests/**' \ || EXIT_STATUS=$? diff --git a/software/runtime/addrmap.h b/software/runtime/addrmap.h new file mode 100644 index 000000000..2c6029169 --- /dev/null +++ b/software/runtime/addrmap.h @@ -0,0 +1,14 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Author: Samuel Riedel, ETH Zurich + +#ifndef _ADDRMAP_H_ +#define _ADDRMAP_H_ + +#define CONTROL_REGISTER_OFFSET (0x40000000) + +#include "control_registers.h" + +#endif // _DMA_H_ diff --git a/software/runtime/arch.ld.c b/software/runtime/arch.ld.c index 8d003388b..1d8de5e57 100644 --- a/software/runtime/arch.ld.c +++ b/software/runtime/arch.ld.c @@ -31,32 +31,5 @@ SECTIONS { __heap_start = __l1_start; __heap_end = __l1_end; - // Hardware register location - eoc_reg = 0x40000000; - wake_up_reg = 0x40000004; - wake_up_group_reg = 0x40000008; - tcdm_start_address_reg = 0x4000000C; - tcdm_end_address_reg = 0x40000010; - nr_cores_address_reg = 0x40000014; - ro_cache_enable = 0x40000018; - ro_cache_flush = 0x4000001C; - ro_cache_start_0 = 0x40000020; - ro_cache_end_0 = 0x40000024; - ro_cache_start_1 = 0x40000028; - ro_cache_end_1 = 0x4000002C; - ro_cache_start_2 = 0x40000030; - ro_cache_end_2 = 0x40000034; - ro_cache_start_3 = 0x40000038; - ro_cache_end_3 = 0x4000003C; - - wake_up_tile_g0_reg = 0x40000040; - wake_up_tile_g1_reg = 0x40000044; - wake_up_tile_g2_reg = 0x40000048; - wake_up_tile_g3_reg = 0x4000004C; - wake_up_tile_g4_reg = 0x40000050; - wake_up_tile_g5_reg = 0x40000054; - wake_up_tile_g6_reg = 0x40000058; - wake_up_tile_g7_reg = 0x4000005C; - fake_uart = 0xC0000000; } diff --git a/software/runtime/control_registers.h b/software/runtime/control_registers.h new file mode 100644 index 000000000..95bd21e45 --- /dev/null +++ b/software/runtime/control_registers.h @@ -0,0 +1,116 @@ +// Generated register defines for control_registers + +// Copyright information found in source file: +// Copyright 2024 ETH Zurich and University of Bologna. + +// Licensing information found in source file: +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +#ifndef _CONTROL_REGISTERS_REG_DEFS_ +#define _CONTROL_REGISTERS_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Number of programmable address regions for the read-only cache +#define CONTROL_REGISTERS_PARAM_R_O_CACHE_NUM_ADDR_RULES 4 + +// Maximum number of groups that we support in any configuration +#define CONTROL_REGISTERS_PARAM_MAX_NUMGROUPS 8 + +// Register width +#define CONTROL_REGISTERS_PARAM_REG_WIDTH 32 + +// End-of-Computation Register +#define CONTROL_REGISTERS_EOC_REG_OFFSET 0x0 + +// Wake Up Register +#define CONTROL_REGISTERS_WAKE_UP_REG_OFFSET 0x4 + +// Wake Up Tile Register (common parameters) +#define CONTROL_REGISTERS_WAKE_UP_TILE_WAKE_UP_TILE_FIELD_WIDTH 32 +#define CONTROL_REGISTERS_WAKE_UP_TILE_WAKE_UP_TILE_FIELDS_PER_REG 1 +#define CONTROL_REGISTERS_WAKE_UP_TILE_MULTIREG_COUNT 8 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_0_REG_OFFSET 0x8 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_1_REG_OFFSET 0xc + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_2_REG_OFFSET 0x10 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_3_REG_OFFSET 0x14 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_4_REG_OFFSET 0x18 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_5_REG_OFFSET 0x1c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_6_REG_OFFSET 0x20 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_7_REG_OFFSET 0x24 + +// Wake Up Group Register +#define CONTROL_REGISTERS_WAKE_UP_GROUP_REG_OFFSET 0x28 + +// TCDM Start Address Register +#define CONTROL_REGISTERS_TCDM_START_ADDRESS_REG_OFFSET 0x2c + +// TCDM End Address Register +#define CONTROL_REGISTERS_TCDM_END_ADDRESS_REG_OFFSET 0x30 + +// Number of Cores Register +#define CONTROL_REGISTERS_NR_CORES_REG_REG_OFFSET 0x34 + +// Read-only cache Enable +#define CONTROL_REGISTERS_RO_CACHE_ENABLE_REG_OFFSET 0x38 + +// Read-only cache Flush +#define CONTROL_REGISTERS_RO_CACHE_FLUSH_REG_OFFSET 0x3c + +// Read-only cache Region Start (common parameters) +#define CONTROL_REGISTERS_RO_CACHE_START_RO_CACHE_START_FIELD_WIDTH 32 +#define CONTROL_REGISTERS_RO_CACHE_START_RO_CACHE_START_FIELDS_PER_REG 1 +#define CONTROL_REGISTERS_RO_CACHE_START_MULTIREG_COUNT 4 + +// Read-only cache Region Start +#define CONTROL_REGISTERS_RO_CACHE_START_0_REG_OFFSET 0x40 + +// Read-only cache Region Start +#define CONTROL_REGISTERS_RO_CACHE_START_1_REG_OFFSET 0x44 + +// Read-only cache Region Start +#define CONTROL_REGISTERS_RO_CACHE_START_2_REG_OFFSET 0x48 + +// Read-only cache Region Start +#define CONTROL_REGISTERS_RO_CACHE_START_3_REG_OFFSET 0x4c + +// Read-only cache Region End (common parameters) +#define CONTROL_REGISTERS_RO_CACHE_END_RO_CACHE_END_FIELD_WIDTH 32 +#define CONTROL_REGISTERS_RO_CACHE_END_RO_CACHE_END_FIELDS_PER_REG 1 +#define CONTROL_REGISTERS_RO_CACHE_END_MULTIREG_COUNT 4 + +// Read-only cache Region End +#define CONTROL_REGISTERS_RO_CACHE_END_0_REG_OFFSET 0x50 + +// Read-only cache Region End +#define CONTROL_REGISTERS_RO_CACHE_END_1_REG_OFFSET 0x54 + +// Read-only cache Region End +#define CONTROL_REGISTERS_RO_CACHE_END_2_REG_OFFSET 0x58 + +// Read-only cache Region End +#define CONTROL_REGISTERS_RO_CACHE_END_3_REG_OFFSET 0x5c + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _CONTROL_REGISTERS_REG_DEFS_ +// End generated register defines for control_registers \ No newline at end of file diff --git a/software/runtime/crt0.S b/software/runtime/crt0.S index 1cc1905c6..4de3d2b70 100644 --- a/software/runtime/crt0.S +++ b/software/runtime/crt0.S @@ -7,6 +7,8 @@ // #define TOP4_STACK +#include "addrmap.h" + .globl _start .globl _eoc .section .text; @@ -77,14 +79,14 @@ _reset_vector: csrw stacklimit, t0 // write stack limit into CSR // Configure the RO cache or directly jump to main bnez a0, _jump_main - la t0, ro_cache_end_0 // Get peripheral register to set cacheable region + li t0, (CONTROL_REGISTER_OFFSET + CONTROL_REGISTERS_RO_CACHE_END_0_REG_OFFSET) // Get peripheral register to set cacheable region la t1, _erodata // Write the end of the read-only data to be cacheable sw t1, 0(t0) _jump_main: call main _eoc: - la t0, eoc_reg + li t0, (CONTROL_REGISTER_OFFSET + CONTROL_REGISTERS_EOC_REG_OFFSET) slli t1, a0, 1 addi t1, t1, 1 sw t1, 0(t0) diff --git a/software/runtime/riscv_test.h b/software/runtime/riscv_test.h index 31882d421..1bf169534 100644 --- a/software/runtime/riscv_test.h +++ b/software/runtime/riscv_test.h @@ -8,6 +8,7 @@ #define _ENV_PHYSICAL_SINGLE_CORE_H #include "encoding.h" +#include "addrmap.h" //----------------------------------------------------------------------- // Begin Macro @@ -95,7 +96,7 @@ reset_vector: \ #define RVTEST_CODE_END \ _eoc: \ - la t0, eoc_reg; \ + li t0, (CONTROL_REGISTER_OFFSET + CONTROL_REGISTERS_EOC_REG_OFFSET); \ slli t1, a0, 1; \ addi t1, t1, 1; \ sw t1, 0(t0); \ diff --git a/software/runtime/runtime.h b/software/runtime/runtime.h index 4abdbd682..958d6775d 100644 --- a/software/runtime/runtime.h +++ b/software/runtime/runtime.h @@ -6,6 +6,7 @@ // Matheus Cavalcante, ETH Zurich #pragma once +#include "addrmap.h" #include "alloc.h" #include "encoding.h" #include @@ -14,18 +15,37 @@ #define NUM_BANKS_PER_TILE NUM_CORES_PER_TILE *BANKING_FACTOR extern char l1_alloc_base; -extern uint32_t atomic_barrier; -extern volatile uint32_t wake_up_reg; -extern volatile uint32_t wake_up_group_reg; - -extern volatile uint32_t wake_up_tile_g0_reg; -extern volatile uint32_t wake_up_tile_g1_reg; -extern volatile uint32_t wake_up_tile_g2_reg; -extern volatile uint32_t wake_up_tile_g3_reg; -extern volatile uint32_t wake_up_tile_g4_reg; -extern volatile uint32_t wake_up_tile_g5_reg; -extern volatile uint32_t wake_up_tile_g6_reg; -extern volatile uint32_t wake_up_tile_g7_reg; +static uint32_t volatile *wake_up_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_REG_OFFSET); +static uint32_t volatile *wake_up_group_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_GROUP_REG_OFFSET); + +static uint32_t volatile *wake_up_tile_g0_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_TILE_0_REG_OFFSET); +static uint32_t volatile *wake_up_tile_g1_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_TILE_1_REG_OFFSET); +static uint32_t volatile *wake_up_tile_g2_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_TILE_2_REG_OFFSET); +static uint32_t volatile *wake_up_tile_g3_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_TILE_3_REG_OFFSET); +static uint32_t volatile *wake_up_tile_g4_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_TILE_4_REG_OFFSET); +static uint32_t volatile *wake_up_tile_g5_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_TILE_5_REG_OFFSET); +static uint32_t volatile *wake_up_tile_g6_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_TILE_6_REG_OFFSET); +static uint32_t volatile *wake_up_tile_g7_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_TILE_7_REG_OFFSET); typedef uint32_t mempool_id_t; typedef uint32_t mempool_timer_t; @@ -127,10 +147,10 @@ static inline void mempool_wfi() { asm volatile("wfi"); } // Wake up core with given core_id by writing in the wake up control register. // If core_id equals -1, wake up all cores. -static inline void wake_up(uint32_t core_id) { wake_up_reg = core_id; } +static inline void wake_up(uint32_t core_id) { *wake_up_reg = core_id; } static inline void wake_up_all() { wake_up((uint32_t)-1); } static inline void wake_up_group(uint32_t group_mask) { - wake_up_group_reg = group_mask; + *wake_up_group_reg = group_mask; } static inline void wake_up_all_group() { wake_up_group((uint32_t)-1); } @@ -138,31 +158,31 @@ static inline void wake_up_tile(uint32_t group_id, uint32_t tile_mask) { switch (group_id) { case 0: - wake_up_tile_g0_reg = tile_mask; + *wake_up_tile_g0_reg = tile_mask; break; case 1: - wake_up_tile_g1_reg = tile_mask; + *wake_up_tile_g1_reg = tile_mask; break; case 2: - wake_up_tile_g2_reg = tile_mask; + *wake_up_tile_g2_reg = tile_mask; break; case 3: - wake_up_tile_g3_reg = tile_mask; + *wake_up_tile_g3_reg = tile_mask; break; case 4: - wake_up_tile_g4_reg = tile_mask; + *wake_up_tile_g4_reg = tile_mask; break; case 5: - wake_up_tile_g5_reg = tile_mask; + *wake_up_tile_g5_reg = tile_mask; break; case 6: - wake_up_tile_g6_reg = tile_mask; + *wake_up_tile_g6_reg = tile_mask; break; case 7: - wake_up_tile_g7_reg = tile_mask; + *wake_up_tile_g7_reg = tile_mask; break; default: - wake_up_tile_g0_reg = tile_mask; + *wake_up_tile_g0_reg = tile_mask; break; } } From 083c2f52b6b5211169197156673c933d9ed7d878 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Fri, 23 Feb 2024 18:31:27 +0100 Subject: [PATCH 02/14] [hardware] Propagate atomics into the AXI interconnect --- hardware/scripts/questa/wave_tile.tcl | 10 +- hardware/src/mempool_pkg.sv | 12 +- hardware/src/mempool_tile.sv | 217 ++++++++++++++------------ hardware/src/tcdm_shim.sv | 102 +++++------- 4 files changed, 172 insertions(+), 169 deletions(-) diff --git a/hardware/scripts/questa/wave_tile.tcl b/hardware/scripts/questa/wave_tile.tcl index 4dd08b9ab..9740b30ac 100644 --- a/hardware/scripts/questa/wave_tile.tcl +++ b/hardware/scripts/questa/wave_tile.tcl @@ -89,13 +89,9 @@ if {$config == {terapool}} { add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/local_resp_* add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/soc_data_* add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/mask_map - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/soc_req_o - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/soc_resp_i - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/soc_qvalid - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/soc_qready - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/soc_pvalid - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/soc_pready - + add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/snitch_to_soc_* + add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/mux_to_soc_* + add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/mux_to_soc_* for {set i 0} {$i < 16} {incr i} { add wave -noupdate -group group_[$1] -group Tile_[$2] -group tcdm_adapter[$i] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_banks[$i]/i_tcdm_adapter/* } diff --git a/hardware/src/mempool_pkg.sv b/hardware/src/mempool_pkg.sv index feedd66e9..5d427feec 100644 --- a/hardware/src/mempool_pkg.sv +++ b/hardware/src/mempool_pkg.sv @@ -110,13 +110,21 @@ package mempool_pkg; `AXI_TYPEDEF_AW_CHAN_T(axi_core_aw_t, addr_t, axi_core_id_t, logic); - `AXI_TYPEDEF_W_CHAN_T(axi_core_w_t, axi_data_t, axi_strb_t, logic); + `AXI_TYPEDEF_W_CHAN_T(axi_core_w_t, data_t, strb_t, logic); `AXI_TYPEDEF_B_CHAN_T(axi_core_b_t, axi_core_id_t, logic); `AXI_TYPEDEF_AR_CHAN_T(axi_core_ar_t, addr_t, axi_core_id_t, logic); - `AXI_TYPEDEF_R_CHAN_T(axi_core_r_t, axi_data_t, axi_core_id_t, logic); + `AXI_TYPEDEF_R_CHAN_T(axi_core_r_t, data_t, axi_core_id_t, logic); `AXI_TYPEDEF_REQ_T(axi_core_req_t, axi_core_aw_t, axi_core_w_t, axi_core_ar_t); `AXI_TYPEDEF_RESP_T(axi_core_resp_t, axi_core_b_t, axi_core_r_t ); + `AXI_TYPEDEF_AW_CHAN_T(axi_cache_aw_t, addr_t, axi_core_id_t, logic); + `AXI_TYPEDEF_W_CHAN_T(axi_cache_w_t, axi_data_t, axi_strb_t, logic); + `AXI_TYPEDEF_B_CHAN_T(axi_cache_b_t, axi_core_id_t, logic); + `AXI_TYPEDEF_AR_CHAN_T(axi_cache_ar_t, addr_t, axi_core_id_t, logic); + `AXI_TYPEDEF_R_CHAN_T(axi_cache_r_t, axi_data_t, axi_core_id_t, logic); + `AXI_TYPEDEF_REQ_T(axi_cache_req_t, axi_cache_aw_t, axi_cache_w_t, axi_cache_ar_t); + `AXI_TYPEDEF_RESP_T(axi_cache_resp_t, axi_cache_b_t, axi_cache_r_t ); + `AXI_TYPEDEF_AW_CHAN_T(axi_tile_aw_t, addr_t, axi_tile_id_t, logic); `AXI_TYPEDEF_W_CHAN_T(axi_tile_w_t, axi_data_t, axi_strb_t, logic); `AXI_TYPEDEF_B_CHAN_T(axi_tile_b_t, axi_tile_id_t, logic); diff --git a/hardware/src/mempool_tile.sv b/hardware/src/mempool_tile.sv index f1e083548..6a9bad452 100644 --- a/hardware/src/mempool_tile.sv +++ b/hardware/src/mempool_tile.sv @@ -60,6 +60,7 @@ module mempool_tile ****************/ `include "common_cells/registers.svh" + `include "reqrsp_interface/typedef.svh" /***************** * Definitions * @@ -283,8 +284,8 @@ module mempool_tile * Instruction Cache * ***********************/ // Instruction interface - axi_core_req_t [NumCaches-1:0] axi_cache_req_d, axi_cache_req_q; - axi_core_resp_t [NumCaches-1:0] axi_cache_resp_d, axi_cache_resp_q; + axi_cache_req_t [NumCaches-1:0] axi_cache_req_d, axi_cache_req_q; + axi_cache_resp_t [NumCaches-1:0] axi_cache_resp_d, axi_cache_resp_q; for (genvar c = 0; unsigned'(c) < NumCaches; c++) begin: gen_caches snitch_icache #( @@ -309,8 +310,8 @@ module mempool_tile .EARLY_LATCH (1 ), .L0_EARLY_TAG_WIDTH (11 ), .ISO_CROSSING (0 ), - .axi_req_t (axi_core_req_t ), - .axi_rsp_t (axi_core_resp_t ) + .axi_req_t (axi_cache_req_t ), + .axi_rsp_t (axi_cache_resp_t ) ) i_snitch_icache ( .clk_i (clk_i ), .clk_d2_i (clk_i ), @@ -331,13 +332,13 @@ module mempool_tile .axi_rsp_i (axi_cache_resp_q[c] ) ); axi_cut #( - .aw_chan_t (axi_core_aw_t ), - .w_chan_t (axi_core_w_t ), - .b_chan_t (axi_core_b_t ), - .ar_chan_t (axi_core_ar_t ), - .r_chan_t (axi_core_r_t ), - .axi_req_t (axi_core_req_t ), - .axi_resp_t(axi_core_resp_t) + .aw_chan_t (axi_cache_aw_t ), + .w_chan_t (axi_cache_w_t ), + .b_chan_t (axi_cache_b_t ), + .ar_chan_t (axi_cache_ar_t ), + .r_chan_t (axi_cache_r_t ), + .axi_req_t (axi_cache_req_t ), + .axi_resp_t(axi_cache_resp_t) ) axi_cache_slice ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -933,7 +934,6 @@ module mempool_tile .soc_qvalid_o (soc_data_qvalid[c] ), .soc_qready_i (soc_data_qready[c] ), .soc_pdata_i (soc_data_p[c].data ), - .soc_pwrite_i (soc_data_p[c].write ), .soc_perror_i (soc_data_p[c].error ), .soc_pvalid_i (soc_data_pvalid[c] ), .soc_pready_o (soc_data_pready[c] ), @@ -1004,72 +1004,67 @@ module mempool_tile * AXI Plug * ****************/ - snitch_pkg::dreq_t soc_req_o; - snitch_pkg::dresp_t soc_resp_i; - - logic soc_qvalid; - logic soc_qready; - logic soc_pvalid; - logic soc_pready; - - // We don't care about this - assign soc_resp_i.id = 'x; - - snitch_demux #( - .NrPorts (NumCoresPerTile ), - .req_t (snitch_pkg::dreq_t ), - .resp_t (snitch_pkg::dresp_t) - ) i_snitch_demux_data ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - // Inputs - .req_payload_i (soc_data_q ), - .req_valid_i (soc_data_qvalid), - .req_ready_o (soc_data_qready), - .resp_payload_o(soc_data_p ), - .resp_last_o (/* Unused */ ), - .resp_valid_o (soc_data_pvalid), - .resp_ready_i (soc_data_pready), - // Output - .req_payload_o (soc_req_o ), - .req_valid_o (soc_qvalid ), - .req_ready_i (soc_qready ), - .resp_payload_i(soc_resp_i ), - .resp_last_i (1'b1 ), - .resp_valid_i (soc_pvalid ), - .resp_ready_o (soc_pready ) - ); + `REQRSP_TYPEDEF_ALL(soc, snitch_pkg::addr_t, snitch_pkg::data_t, snitch_pkg::strb_t) - // Core request + // Pack the cores' soc_req/rsp into a reqrsp bus + soc_req_t [NumCoresPerTile-1:0] snitch_to_soc_req; + soc_rsp_t [NumCoresPerTile-1:0] snitch_to_soc_rsp; + soc_req_t mux_to_soc_req; + soc_rsp_t mux_to_soc_rsp; + // AXI core request axi_core_req_t axi_cores_req_d, axi_cores_req_q; axi_core_resp_t axi_cores_resp_d, axi_cores_resp_q; + axi_cache_req_t axi_cores_wide_req; + axi_cache_resp_t axi_cores_wide_resp; + + for (genvar c = 0; c < NumCoresPerTile; c++) begin: gen_core_soc_reqrsp + assign snitch_to_soc_req[c].q.addr = soc_data_q[c].addr; + assign snitch_to_soc_req[c].q.write = soc_data_q[c].write; + assign snitch_to_soc_req[c].q.amo = reqrsp_pkg::amo_op_e'(soc_data_q[c].amo); + assign snitch_to_soc_req[c].q.data = soc_data_q[c].data; + assign snitch_to_soc_req[c].q.strb = soc_data_q[c].strb; + assign snitch_to_soc_req[c].q.size = 3'b010; // AXI-style size: 2^x bytes + assign snitch_to_soc_req[c].q_valid = soc_data_qvalid[c]; + assign soc_data_qready[c] = snitch_to_soc_rsp[c].q_ready; + assign soc_data_p[c].data = snitch_to_soc_rsp[c].p.data; + assign soc_data_p[c].error = snitch_to_soc_rsp[c].p.error; + assign soc_data_p[c].id = '0; // Don't care + assign soc_data_p[c].write = '0; // Don't care + assign soc_data_pvalid[c] = snitch_to_soc_rsp[c].p_valid; + assign snitch_to_soc_req[c].p_ready = soc_data_pready[c]; + end + + reqrsp_mux #( + .NrPorts (NumCoresPerTile), + .AddrWidth (AddrWidth ), + .DataWidth (DataWidth ), + .req_t (soc_req_t ), + .rsp_t (soc_rsp_t ), + .RespDepth (NumCoresPerTile), + .RegisterReq ('0 ) + ) i_reqrsp_mux_snitch_soc ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .slv_req_i (snitch_to_soc_req), + .slv_rsp_o (snitch_to_soc_rsp), + .mst_req_o (mux_to_soc_req ), + .mst_rsp_i (mux_to_soc_rsp ) + ); - snitch_axi_adapter #( - .addr_t (snitch_pkg::addr_t), - .data_t (snitch_pkg::data_t), - .strb_t (snitch_pkg::strb_t), - .axi_mst_req_t (axi_core_req_t ), - .axi_mst_resp_t (axi_core_resp_t ) - ) i_snitch_core_axi_adapter ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .slv_qaddr_i (soc_req_o.addr ), - .slv_qwrite_i(soc_req_o.write ), - .slv_qamo_i (soc_req_o.amo ), - .slv_qdata_i (soc_req_o.data ), - .slv_qsize_i (3'b010 ), - .slv_qstrb_i (soc_req_o.strb ), - .slv_qrlen_i ('0 ), - .slv_qvalid_i(soc_qvalid ), - .slv_qready_o(soc_qready ), - .slv_pdata_o (soc_resp_i.data ), - .slv_pwrite_o(soc_resp_i.write), - .slv_perror_o(soc_resp_i.error), - .slv_plast_o (/* Unused */ ), - .slv_pvalid_o(soc_pvalid ), - .slv_pready_i(soc_pready ), - .axi_req_o (axi_cores_req_d ), - .axi_resp_i (axi_cores_resp_q) + reqrsp_to_axi #( + .MaxTrans (NumCoresPerTile), + .DataWidth (DataWidth ), + .reqrsp_req_t (soc_req_t ), + .reqrsp_rsp_t (soc_rsp_t ), + .axi_req_t (axi_core_req_t ), + .axi_rsp_t (axi_core_resp_t) + ) i_reqrsp_snitch_to_axi ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .reqrsp_req_i (mux_to_soc_req ), + .reqrsp_rsp_o (mux_to_soc_rsp ), + .axi_req_o (axi_cores_req_d ), + .axi_rsp_i (axi_cores_resp_q) ); axi_cut #( @@ -1089,32 +1084,58 @@ module mempool_tile .mst_resp_i(axi_cores_resp_d) ); + axi_dw_converter #( + .AxiMaxReads (NumCoresPerTile ), + .AxiSlvPortDataWidth (DataWidth ), + .AxiMstPortDataWidth (AxiDataWidth ), + .AxiAddrWidth (AddrWidth ), + .AxiIdWidth (AxiCoreIdWidth ), + .aw_chan_t (axi_core_aw_t ), + .mst_w_chan_t (axi_cache_w_t ), + .slv_w_chan_t (axi_core_w_t ), + .b_chan_t (axi_core_b_t ), + .ar_chan_t (axi_core_ar_t ), + .mst_r_chan_t (axi_cache_r_t ), + .slv_r_chan_t (axi_core_r_t ), + .axi_mst_req_t (axi_cache_req_t ), + .axi_mst_resp_t (axi_cache_resp_t), + .axi_slv_req_t (axi_core_req_t ), + .axi_slv_resp_t (axi_core_resp_t ) + ) i_axi_dw_converter_cores ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .slv_req_i (axi_cores_req_q ), + .slv_resp_o (axi_cores_resp_d ), + .mst_req_o (axi_cores_wide_req ), + .mst_resp_i (axi_cores_wide_resp) + ); + axi_mux #( - .SlvAxiIDWidth (AxiCoreIdWidth ), - .slv_aw_chan_t (axi_core_aw_t ), - .mst_aw_chan_t (axi_tile_aw_t ), - .w_chan_t (axi_tile_w_t ), - .slv_b_chan_t (axi_core_b_t ), - .mst_b_chan_t (axi_tile_b_t ), - .slv_ar_chan_t (axi_core_ar_t ), - .mst_ar_chan_t (axi_tile_ar_t ), - .slv_r_chan_t (axi_core_r_t ), - .mst_r_chan_t (axi_tile_r_t ), - .slv_req_t (axi_core_req_t ), - .slv_resp_t (axi_core_resp_t), - .mst_req_t (axi_tile_req_t ), - .mst_resp_t (axi_tile_resp_t), - .NoSlvPorts (1+NumCaches ), - .MaxWTrans (8 ), - .FallThrough (1 ) + .SlvAxiIDWidth (AxiCoreIdWidth ), + .slv_aw_chan_t (axi_cache_aw_t ), + .mst_aw_chan_t (axi_tile_aw_t ), + .w_chan_t (axi_cache_w_t ), + .slv_b_chan_t (axi_cache_b_t ), + .mst_b_chan_t (axi_tile_b_t ), + .slv_ar_chan_t (axi_cache_ar_t ), + .mst_ar_chan_t (axi_tile_ar_t ), + .slv_r_chan_t (axi_cache_r_t ), + .mst_r_chan_t (axi_tile_r_t ), + .slv_req_t (axi_cache_req_t ), + .slv_resp_t (axi_cache_resp_t), + .mst_req_t (axi_tile_req_t ), + .mst_resp_t (axi_tile_resp_t ), + .NoSlvPorts (1+NumCaches ), + .MaxWTrans (NumCoresPerTile ), + .FallThrough (1 ) ) i_axi_mux ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .test_i (1'b0 ), - .slv_reqs_i ({axi_cores_req_q, axi_cache_req_q} ), - .slv_resps_o({axi_cores_resp_d, axi_cache_resp_d}), - .mst_req_o (axi_mst_req_o ), - .mst_resp_i (axi_mst_resp_i ) + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (1'b0 ), + .slv_reqs_i ({axi_cores_wide_req, axi_cache_req_q} ), + .slv_resps_o({axi_cores_wide_resp, axi_cache_resp_d}), + .mst_req_o (axi_mst_req_o ), + .mst_resp_i (axi_mst_resp_i ) ); /****************** diff --git a/hardware/src/tcdm_shim.sv b/hardware/src/tcdm_shim.sv index 5da72f997..d7c09ed1f 100644 --- a/hardware/src/tcdm_shim.sv +++ b/hardware/src/tcdm_shim.sv @@ -45,7 +45,6 @@ module tcdm_shim output logic [NrSoC-1:0] soc_qvalid_o, input logic [NrSoC-1:0] soc_qready_i, input logic [NrSoC-1:0] [DataWidth-1:0] soc_pdata_i, - input logic [NrSoC-1:0] soc_pwrite_i, input logic [NrSoC-1:0] soc_perror_i, input logic [NrSoC-1:0] soc_pvalid_i, output logic [NrSoC-1:0] soc_pready_o, @@ -68,67 +67,46 @@ module tcdm_shim ); // Imports - import snitch_pkg::dreq_t ; + import snitch_pkg::dreq_t; import snitch_pkg::dresp_t; // Includes `include "common_cells/registers.svh" - dreq_t data_qpayload ; - dreq_t [NrSoC-1:0] soc_qpayload ; + dreq_t data_qpayload; + dreq_t [NrSoC-1:0] soc_qpayload; dreq_t [NrTCDM-1:0] tcdm_qpayload; - dresp_t data_ppayload ; - dresp_t [NrSoC-1:0] soc_ppayload ; + dresp_t data_ppayload; + dresp_t [NrSoC-1:0] soc_ppayload; dresp_t [NrTCDM-1:0] tcdm_ppayload; for (genvar i = 0; i < NrTCDM; i++) begin : gen_tcdm_ppayload - assign tcdm_ppayload[i].id = tcdm_resp_id_i[i] ; + assign tcdm_ppayload[i].id = tcdm_resp_id_i[i]; assign tcdm_ppayload[i].data = tcdm_resp_rdata_i[i]; - assign tcdm_ppayload[i].write = 1'b0 ; // Don't care - assign tcdm_ppayload[i].error = 1'b0 ; + assign tcdm_ppayload[i].write = 1'b0; // Don't care + assign tcdm_ppayload[i].error = 1'b0; end // ROB IDs of the SoC requests (come back in order) logic [NrSoC-1:0][MetaIdWidth-1:0] soc_meta_id; for (genvar i = 0; i < NrSoC; i++) begin: gen_soc_meta_id_fifo - logic [NrSoC-1:0][MetaIdWidth-1:0] meta_read; - logic [NrSoC-1:0][MetaIdWidth-1:0] meta_write; - - assign soc_meta_id[i] = soc_pwrite_i ? meta_write : meta_read; - - fifo_v3 #( - .DEPTH (MaxOutStandingTrans), - .DATA_WIDTH(MetaIdWidth ) - ) i_soc_meta_id_read_fifo ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .flush_i (1'b0 ), - .testmode_i(1'b0 ), - .data_i (data_qid_i ), - .push_i (soc_qvalid_o[i] & soc_qready_i[i] &!soc_qwrite_o[i]), - .full_o (/* Unused */ ), - .data_o (meta_read ), - .pop_i (soc_pvalid_i[i] & soc_pready_o[i] & !soc_pwrite_i ), - .empty_o (/* Unused */ ), - .usage_o (/* Unused */ ) - ); fifo_v3 #( .DEPTH (MaxOutStandingTrans), .DATA_WIDTH(MetaIdWidth ) - ) i_soc_meta_id_write_fifo ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .flush_i (1'b0 ), - .testmode_i(1'b0 ), - .data_i (data_qid_i ), - .push_i (soc_qvalid_o[i] & soc_qready_i[i] & soc_qwrite_o[i]), - .full_o (/* Unused */ ), - .data_o (meta_write ), - .pop_i (soc_pvalid_i[i] & soc_pready_o[i] & soc_pwrite_i ), - .empty_o (/* Unused */ ), - .usage_o (/* Unused */ ) + ) i_soc_meta_id_fifo ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i (1'b0 ), + .testmode_i(1'b0 ), + .data_i (data_qid_i ), + .push_i (soc_qvalid_o[i] & soc_qready_i[i]), + .full_o (/* Unused */ ), + .data_o (soc_meta_id ), + .pop_i (soc_pvalid_i[i] & soc_pready_o[i]), + .empty_o (/* Unused */ ), + .usage_o (/* Unused */ ) ); end: gen_soc_meta_id_fifo @@ -160,39 +138,39 @@ module tcdm_shim // Connect TCDM output ports for (genvar i = 0; i < NrTCDM; i++) begin : gen_tcdm_con - assign tcdm_req_tgt_addr_o[i] = tcdm_qpayload[i].addr ; - assign tcdm_req_wdata_o[i] = tcdm_qpayload[i].data ; - assign tcdm_req_amo_o[i] = tcdm_qpayload[i].amo ; - assign tcdm_req_id_o[i] = tcdm_qpayload[i].id ; + assign tcdm_req_tgt_addr_o[i] = tcdm_qpayload[i].addr; + assign tcdm_req_wdata_o[i] = tcdm_qpayload[i].data; + assign tcdm_req_amo_o[i] = tcdm_qpayload[i].amo; + assign tcdm_req_id_o[i] = tcdm_qpayload[i].id; assign tcdm_req_wen_o[i] = tcdm_qpayload[i].write; - assign tcdm_req_be_o[i] = tcdm_qpayload[i].strb ; + assign tcdm_req_be_o[i] = tcdm_qpayload[i].strb; end // Connect SOCs for (genvar i = 0; i < NrSoC; i++) begin : gen_soc_con - assign soc_qaddr_o[i] = soc_qpayload[i].addr ; + assign soc_qaddr_o[i] = soc_qpayload[i].addr; assign soc_qwrite_o[i] = soc_qpayload[i].write; - assign soc_qamo_o[i] = soc_qpayload[i].amo ; - assign soc_qdata_o[i] = soc_qpayload[i].data ; - assign soc_qstrb_o[i] = soc_qpayload[i].strb ; - assign soc_ppayload[i].data = soc_pdata_i[i] ; - assign soc_ppayload[i].id = soc_meta_id[i] ; - assign soc_ppayload[i].write = soc_pwrite_i[i] ; - assign soc_ppayload[i].error = soc_perror_i[i] ; + assign soc_qamo_o[i] = soc_qpayload[i].amo; + assign soc_qdata_o[i] = soc_qpayload[i].data; + assign soc_qstrb_o[i] = soc_qpayload[i].strb; + assign soc_ppayload[i].data = soc_pdata_i[i]; + assign soc_ppayload[i].id = soc_meta_id[i]; + assign soc_ppayload[i].write = '0; // Don't care + assign soc_ppayload[i].error = soc_perror_i[i]; end // Request interface - assign data_qpayload.addr = data_qaddr_i ; + assign data_qpayload.addr = data_qaddr_i; assign data_qpayload.write = data_qwrite_i; - assign data_qpayload.amo = data_qamo_i ; - assign data_qpayload.data = data_qdata_i ; - assign data_qpayload.id = data_qid_i ; - assign data_qpayload.strb = data_qstrb_i ; + assign data_qpayload.amo = data_qamo_i; + assign data_qpayload.data = data_qdata_i; + assign data_qpayload.id = data_qid_i; + assign data_qpayload.strb = data_qstrb_i; // Response interface - assign data_pdata_o = data_ppayload.data ; + assign data_pdata_o = data_ppayload.data; assign data_perror_o = data_ppayload.error; - assign data_pid_o = data_ppayload.id ; + assign data_pid_o = data_ppayload.id; // Elaboration-time assertions From f7a45b6e35dd4159d99b0ac032b31de52c46e839 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Fri, 23 Feb 2024 18:33:50 +0100 Subject: [PATCH 03/14] [snitch] Remove deprecated snitch modules --- hardware/deps/snitch/Bender.yml | 2 - .../deps/snitch/src/snitch_axi_adapter.sv | 269 ------------------ hardware/deps/snitch/src/snitch_demux.sv | 150 ---------- 3 files changed, 421 deletions(-) delete mode 100644 hardware/deps/snitch/src/snitch_axi_adapter.sv delete mode 100644 hardware/deps/snitch/src/snitch_demux.sv diff --git a/hardware/deps/snitch/Bender.yml b/hardware/deps/snitch/Bender.yml index 21e259e6f..a7fa87775 100644 --- a/hardware/deps/snitch/Bender.yml +++ b/hardware/deps/snitch/Bender.yml @@ -29,5 +29,3 @@ sources: - src/snitch_fp_divsqrt.sv - src/snitch_fpu.sv - src/snitch_shared_muldiv.sv - - src/snitch_demux.sv - - src/snitch_axi_adapter.sv diff --git a/hardware/deps/snitch/src/snitch_axi_adapter.sv b/hardware/deps/snitch/src/snitch_axi_adapter.sv deleted file mode 100644 index 3c991a570..000000000 --- a/hardware/deps/snitch/src/snitch_axi_adapter.sv +++ /dev/null @@ -1,269 +0,0 @@ -// Copyright 2018-2019 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// File: axi_adapter.sv -// Author: Florian Zaruba -// Date: 1.8.2018 -// -// Description: Manages communication with the AXI Bus - -module snitch_axi_adapter #( - parameter int unsigned WriteFIFODepth = 2, - parameter int unsigned ReadFIFODepth = 2, - parameter type addr_t = logic, - parameter type data_t = logic, - parameter type strb_t = logic, - parameter type axi_mst_req_t = logic, - parameter type axi_mst_resp_t = logic -) ( - input logic clk_i, - input logic rst_ni, - // AXI port - input axi_mst_resp_t axi_resp_i, - output axi_mst_req_t axi_req_o, - - input addr_t slv_qaddr_i, - input logic slv_qwrite_i, - input logic [3:0] slv_qamo_i, - input data_t slv_qdata_i, - input logic [2:0] slv_qsize_i, - input strb_t slv_qstrb_i, - input logic [7:0] slv_qrlen_i, - input logic slv_qvalid_i, - output logic slv_qready_o, - output data_t slv_pdata_o, - output logic slv_pwrite_o, - output logic slv_perror_o, - output logic slv_plast_o, - output logic slv_pvalid_o, - input logic slv_pready_i -); - - localparam DataWidth = $bits(data_t); - localparam StrbWidth = $bits(strb_t); - localparam SlvByteOffset = $clog2($bits(strb_t)); - localparam AxiByteOffset = $clog2($bits(axi_req_o.w.strb)); - - typedef enum logic [3:0] { - AMONone = 4'h0, - AMOSwap = 4'h1, - AMOAdd = 4'h2, - AMOAnd = 4'h3, - AMOOr = 4'h4, - AMOXor = 4'h5, - AMOMax = 4'h6, - AMOMaxu = 4'h7, - AMOMin = 4'h8, - AMOMinu = 4'h9, - AMOLR = 4'hA, - AMOSC = 4'hB - } amo_op_t; - - typedef struct packed { - data_t data; - strb_t strb; - } write_t; - - typedef struct packed { - data_t data; - logic write; - logic error; - logic last; - } resp_t; - - logic write_full; - logic write_empty; - logic read_full; - write_t write_data_in; - write_t write_data_out; - write_t r_data; - - assign axi_req_o.aw.addr = slv_qaddr_i; - assign axi_req_o.aw.prot = 3'b0; - assign axi_req_o.aw.region = 4'b0; - assign axi_req_o.aw.size = slv_qsize_i; - assign axi_req_o.aw.len = '0; - assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; - assign axi_req_o.aw.lock = 1'b0; - assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE; - assign axi_req_o.aw.qos = 4'b0; - assign axi_req_o.aw.id = '0; - assign axi_req_o.aw.user = '0; - assign axi_req_o.aw_valid = ~write_full & slv_qvalid_i & slv_qwrite_i; - - always_comb begin - write_data_in.data = slv_qdata_i; - write_data_in.strb = slv_qstrb_i; - unique case (amo_op_t'(slv_qamo_i)) - // RISC-V atops have a load semantic - AMOSwap: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ATOMICSWAP}; - AMOAdd: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD}; - AMOAnd: begin - // in this case we need to invert the data to get a "CLR" - write_data_in.data = ~slv_qdata_i; - axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR}; - end - AMOOr: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET}; - AMOXor: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR}; - AMOMax: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX}; - AMOMaxu: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX}; - AMOMin: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN}; - AMOMinu: axi_req_o.aw.atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN}; - default: axi_req_o.aw.atop = '0; - endcase - end - - localparam int unsigned ShiftWidth = (SlvByteOffset == AxiByteOffset) ? 1 : AxiByteOffset - SlvByteOffset; - typedef logic [ShiftWidth-1:0] shift_t; - typedef struct packed { - write_t data; - shift_t shift; - } write_ext_t; - - if (SlvByteOffset == AxiByteOffset) begin : gen_w_data - // Write - fifo_v3 #( - .DEPTH ( WriteFIFODepth ), - .dtype ( write_t ) - ) i_fifo_w_data ( - .clk_i, - .rst_ni, - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .full_o ( write_full ), - .empty_o ( write_empty ), - .usage_o ( /* NC */ ), - .data_i ( write_data_in ), - .push_i ( slv_qvalid_i & slv_qready_o & slv_qwrite_i ), - .data_o ( write_data_out ), - .pop_i ( axi_req_o.w_valid & axi_resp_i.w_ready ) - ); - assign axi_req_o.w.data = write_data_out.data; - assign axi_req_o.w.strb = write_data_out.strb; - - // Read - assign read_full = 1'b0; - assign r_data = axi_resp_i.r.data; - end else begin : gen_w_data - // Write - write_ext_t write_data_ext_in, write_data_ext_out; - - fifo_v3 #( - .DEPTH ( WriteFIFODepth ), - .dtype ( write_ext_t ) - ) i_fifo_w_data ( - .clk_i, - .rst_ni, - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .full_o ( write_full ), - .empty_o ( write_empty ), - .usage_o ( /* NC */ ), - .data_i ( write_data_ext_in ), - .push_i ( slv_qvalid_i & slv_qready_o & slv_qwrite_i ), - .data_o ( write_data_ext_out ), - .pop_i ( axi_req_o.w_valid & axi_resp_i.w_ready ) - ); - - assign write_data_ext_in.data = write_data_in; - assign write_data_ext_in.shift = slv_qaddr_i[AxiByteOffset-1:SlvByteOffset]; - assign axi_req_o.w.data = {'0, write_data_ext_out.data.data} << ($bits(data_t) * write_data_ext_out.shift); - assign axi_req_o.w.strb = {'0, write_data_ext_out.data.strb} << ($bits(strb_t) * write_data_ext_out.shift); - - // Read - shift_t read_shift; - - fifo_v3 #( - .DEPTH ( ReadFIFODepth ), - .DATA_WIDTH ( AxiByteOffset-SlvByteOffset ) - ) i_fifo_r_shift ( - .clk_i, - .rst_ni, - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .full_o ( read_full ), - .empty_o ( /* NC */ ), - .usage_o ( /* NC */ ), - .data_i ( slv_qaddr_i[AxiByteOffset-1:SlvByteOffset] ), - .push_i ( slv_qvalid_i & slv_qready_o & ~slv_qwrite_i ), - .data_o ( read_shift ), - .pop_i ( axi_resp_i.r_valid & axi_req_o.r_ready ) - ); - - assign r_data = axi_resp_i.r.data >> ($bits(data_t) * read_shift); - end - assign axi_req_o.w.last = 1'b1; - assign axi_req_o.w.user = '0; - assign axi_req_o.w_valid = ~write_empty; - - assign axi_req_o.ar.addr = slv_qaddr_i; - assign axi_req_o.ar.prot = 3'b0; - assign axi_req_o.ar.region = 4'b0; - assign axi_req_o.ar.size = slv_qsize_i; - assign axi_req_o.ar.len = slv_qrlen_i; - assign axi_req_o.ar.burst = axi_pkg::BURST_INCR; - assign axi_req_o.ar.lock = 1'b0; - assign axi_req_o.ar.cache = axi_pkg::CACHE_MODIFIABLE; - assign axi_req_o.ar.qos = 4'b0; - assign axi_req_o.ar.id = '0; - assign axi_req_o.ar.user = '0; - assign axi_req_o.ar_valid = ~read_full & slv_qvalid_i & ~slv_qwrite_i; - - // Response arbitration because we can get an R and B response simultaneously - resp_t r_resp, b_resp, slv_resp; - logic r_error, b_error; - - assign r_error = (axi_resp_i.r.resp inside {axi_pkg::RESP_EXOKAY, axi_pkg::RESP_OKAY}) ? 1'b0 : 1'b1; - assign b_error = (axi_resp_i.b.resp inside {axi_pkg::RESP_EXOKAY, axi_pkg::RESP_OKAY}) ? 1'b0 : 1'b1; - - assign r_resp = '{ - data: r_data, - write: 1'b0, - error: r_error, - last: axi_resp_i.r.last - }; - - assign b_resp = '{ - data: r_data, - write: 1'b1, - error: b_error, - last: 1'b1 - }; - - rr_arb_tree #( - .NumIn (2), - .DataType (resp_t), - .ExtPrio (1'b1), - .AxiVldRdy (1'b1), - .LockIn (1'b0) - ) i_response_arbiter ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .flush_i('0 ), - .rr_i ('0 ), - .req_i ({axi_resp_i.b_valid,axi_resp_i.r_valid}), - .gnt_o ({axi_req_o.b_ready,axi_req_o.r_ready} ), - .data_i ({b_resp,r_resp} ), - .gnt_i (slv_pready_i ), - .req_o (slv_pvalid_o ), - .data_o (slv_resp ), - .idx_o ( ) - ); - - assign slv_pdata_o = slv_resp.data; - assign slv_pwrite_o = slv_resp.write; - assign slv_perror_o = slv_resp.error; - assign slv_plast_o = slv_resp.last; - - assign slv_qready_o = (axi_resp_i.ar_ready & axi_req_o.ar_valid) - | (axi_resp_i.aw_ready & axi_req_o.aw_valid); - - `ifndef VERILATOR - // pragma translate_off - hot_one : assert property ( - @(posedge clk_i) disable iff (!rst_ni) (slv_qvalid_i & slv_qwrite_i & slv_qready_o) |-> (slv_qrlen_i == 0)) - else $warning("Bursts are not supported for write transactions"); - // pragma translate_on - `endif -endmodule diff --git a/hardware/deps/snitch/src/snitch_demux.sv b/hardware/deps/snitch/src/snitch_demux.sv deleted file mode 100644 index 387979170..000000000 --- a/hardware/deps/snitch/src/snitch_demux.sv +++ /dev/null @@ -1,150 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -/// Arbitrates request/response interface -/// Author: Florian Zaruba - -/// Demux based on arbitration -module snitch_demux #( - parameter int unsigned NrPorts = 4, - parameter type req_t = snitch_pkg::dreq_t, - parameter type resp_t = snitch_pkg::dresp_t, - parameter int unsigned RespDepth = 8, - parameter bit [NrPorts-1:0] RegisterReq = '0, - parameter Arbiter = "rr" // "rr" or "prio" -) ( - input logic clk_i, - input logic rst_ni, - // request port - input req_t [NrPorts-1:0] req_payload_i, - input logic [NrPorts-1:0] req_valid_i, - output logic [NrPorts-1:0] req_ready_o, - - output resp_t [NrPorts-1:0] resp_payload_o, - output logic [NrPorts-1:0] resp_last_o, - output logic [NrPorts-1:0] resp_valid_o, - input logic [NrPorts-1:0] resp_ready_i, - // response port - output req_t req_payload_o, - output logic req_valid_o, - input logic req_ready_i, - - input resp_t resp_payload_i, - input logic resp_last_i, - input logic resp_valid_i, - output logic resp_ready_o -); - - localparam LogNrPorts = (NrPorts > 1) ? $clog2(NrPorts) : 1; - - logic req_valid_mask; - logic req_ready_mask; - logic [LogNrPorts-1:0] idx, idx_r, idx_w, idx_rsp; - logic full_r, full_w, full; - - req_t [NrPorts-1:0] req_payload_q; - logic [NrPorts-1:0] req_valid_q; - logic [NrPorts-1:0] req_ready_q; - - // Cut the incoming path - for (genvar i = 0; i < NrPorts; i++) begin : gen_spill_regs - spill_register #( - .T ( req_t ), - .Bypass ( !RegisterReq[i] ) - ) i_spill_register_tcdm_req ( - .clk_i, - .rst_ni, - .valid_i ( req_valid_i[i] ), - .ready_o ( req_ready_o[i] ), - .data_i ( req_payload_i[i] ), - .valid_o ( req_valid_q[i] ), - .ready_i ( req_ready_q[i] ), - .data_o ( req_payload_q[i] ) - ); - end - - assign req_valid_o = req_valid_mask & ~full; - assign req_ready_mask = req_ready_i & ~full; - - /// Arbitrate on instruction request port - stream_arbiter #( - .DATA_T ( req_t ), - .N_INP ( NrPorts ), - .ARBITER ( Arbiter ) - ) i_stream_arbiter_req ( - .clk_i, - .rst_ni, - .inp_data_i ( req_payload_q ), - .inp_valid_i ( req_valid_q ), - .inp_ready_o ( req_ready_q ), - .oup_data_o ( req_payload_o ), - .oup_valid_o ( req_valid_mask ), - .oup_ready_i ( req_ready_mask ) - ); - - if (NrPorts == 1) begin : gen_connection - assign idx_rsp = 0; - assign full = 1'b0; - end else begin : gen_demux - onehot_to_bin #( - .ONEHOT_WIDTH ( NrPorts ) - ) i_onehot_to_bin ( - .onehot ( req_valid_q & req_ready_q ), - .bin ( idx ) - ); - - fifo_v3 #( - .DATA_WIDTH ( LogNrPorts ), - .DEPTH ( RespDepth ) - ) i_r_resp_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .full_o ( full_r ), - .empty_o ( ), - .usage_o ( ), - .data_i ( idx ), - .push_i ( req_valid_o && req_ready_i && !req_payload_o.write ), - .data_o ( idx_r ), - .pop_i ( resp_ready_o && resp_valid_i && resp_last_i && !resp_payload_i.write ) - ); - - fifo_v3 #( - .DATA_WIDTH ( LogNrPorts ), - .DEPTH ( RespDepth ) - ) i_w_resp_fifo ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .flush_i ( 1'b0 ), - .testmode_i ( 1'b0 ), - .full_o ( full_w ), - .empty_o ( ), - .usage_o ( ), - .data_i ( idx ), - .push_i ( req_valid_o && req_ready_i && req_payload_o.write ), - .data_o ( idx_w ), - .pop_i ( resp_ready_o && resp_valid_i && resp_last_i && resp_payload_i.write ) - ); - - assign idx_rsp = resp_payload_i.write ? idx_w : idx_r; - assign full = req_payload_o.write ? full_w : full_r; - end - - stream_demux #( - .N_OUP ( NrPorts ) - ) i_stream_demux_resp ( - .inp_valid_i ( resp_valid_i ), - .inp_ready_o ( resp_ready_o ), - .oup_sel_i ( idx_rsp ), - .oup_valid_o ( resp_valid_o ), - .oup_ready_i ( resp_ready_i ) - ); - - for (genvar i = 0; i < NrPorts; i++) begin - assign resp_payload_o[i] = resp_payload_i; - assign resp_last_o[i] = resp_last_i; - end - -endmodule From 6e08d678bfae3354bea0c934c917f7dc64113188 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Fri, 1 Mar 2024 15:54:53 +0100 Subject: [PATCH 04/14] [hardware] Support atomics in the interleaved L2 banks --- hardware/src/mempool_system.sv | 207 ++++++++++++++++++++------------- 1 file changed, 129 insertions(+), 78 deletions(-) diff --git a/hardware/src/mempool_system.sv b/hardware/src/mempool_system.sv index b7fbb00d0..9fdc07e1c 100644 --- a/hardware/src/mempool_system.sv +++ b/hardware/src/mempool_system.sv @@ -30,6 +30,8 @@ module mempool_system import axi_pkg::xbar_cfg_t; import axi_pkg::xbar_rule_32_t; + `include "reqrsp_interface/typedef.svh" + /********* * AXI * *********/ @@ -238,104 +240,153 @@ module mempool_system * L2 SRAM * *************/ - localparam int unsigned NumAXIMastersLog2 = NumAXIMasters == 1 ? 1 : $clog2(NumAXIMasters); - typedef logic [L2AddrWidth-1:0] l2_mem_addr_t; + `REQRSP_TYPEDEF_ALL(axi_to_l2, addr_t, axi_data_t, axi_strb_t) typedef logic [L2BankAddrWidth-1:0] l2_bank_addr_t; - typedef logic [NumAXIMastersLog2-1:0] bank_ini_t; - // Axi2Mems to l2_xbar - logic [NumAXIMasters-1:0] mem_req; - logic [NumAXIMasters-1:0] mem_gnt; - logic [NumAXIMasters-1:0] mem_rvalid; - addr_t [NumAXIMasters-1:0] mem_addr_full; - l2_mem_addr_t [NumAXIMasters-1:0] mem_addr; - axi_data_t [NumAXIMasters-1:0] mem_wdata; - axi_strb_t [NumAXIMasters-1:0] mem_strb; - logic [NumAXIMasters-1:0] mem_we; - axi_data_t [NumAXIMasters-1:0] mem_rdata; - // l2_xbar to banks + // Axi2ReqRsp + axi_to_l2_req_t [NumAXIMasters-1:0] axi_to_l2_req; + axi_to_l2_rsp_t [NumAXIMasters-1:0] axi_to_l2_rsp; + // Axi2ReqRsp unpacked + localparam int unsigned NumAXIMastersWidth = (NumAXIMasters > 32'd1) ? unsigned'($clog2(NumAXIMasters)) : 32'd1; + localparam int unsigned NumL2BanksWidth = (NumL2Banks > 32'd1) ? unsigned'($clog2(NumL2Banks)) : 32'd1; + typedef logic [NumAXIMastersWidth-1:0] l2_axi_idx_t; + typedef logic [NumL2BanksWidth-1:0] l2_bank_idx_t; + axi_to_l2_req_chan_t [NumAXIMasters-1:0] axi_to_l2_req_chan; + axi_to_l2_rsp_chan_t [NumAXIMasters-1:0] axi_to_l2_rsp_chan; + logic [NumAXIMasters-1:0] axi_to_l2_q_valid; + logic [NumAXIMasters-1:0] axi_to_l2_q_ready; + l2_bank_idx_t [NumAXIMasters-1:0] axi_to_l2_q_sel; + l2_axi_idx_t [NumL2Banks-1:0] axi_to_l2_q_idx; + logic [NumAXIMasters-1:0] axi_to_l2_p_valid; + logic [NumAXIMasters-1:0] axi_to_l2_p_ready; + l2_axi_idx_t [NumL2Banks-1:0] axi_to_l2_p_sel; + // Axi2ReqRsp to bank_adapter + axi_to_l2_req_chan_t [NumL2Banks-1:0] mem_req_chan; + axi_to_l2_rsp_chan_t [NumL2Banks-1:0] mem_rsp_chan; + logic [NumL2Banks-1:0] mem_req_valid; + logic [NumL2Banks-1:0] mem_req_ready; + logic [NumL2Banks-1:0] mem_rsp_valid; + logic [NumL2Banks-1:0] mem_rsp_ready; + // bank_adapter to banks logic [NumL2Banks-1:0] bank_req; - logic [NumL2Banks-1:0] bank_gnt; - logic [NumL2Banks-1:0] bank_rvalid; + logic [NumL2Banks-1:0] bank_we; l2_bank_addr_t [NumL2Banks-1:0] bank_addr; - bank_ini_t [NumL2Banks-1:0] bank_ini_d, bank_ini_q; axi_data_t [NumL2Banks-1:0] bank_wdata; axi_strb_t [NumL2Banks-1:0] bank_strb; - logic [NumL2Banks-1:0] bank_we; axi_data_t [NumL2Banks-1:0] bank_rdata; for (genvar i = 0; i < NumAXIMasters; i++) begin : gen_l2_adapters - axi2mem #( - .axi_req_t (axi_tile_req_t ), - .axi_resp_t(axi_tile_resp_t), - .AddrWidth (L2AddrWidth ), - .DataWidth (AxiDataWidth ), - .IdWidth (AxiTileIdWidth ), - .NumBanks (1 ), - .BufDepth (3 ) - ) i_axi2mem ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .busy_o (/*unsused*/ ), - .axi_req_i (axi_l2_req[i] ), - .axi_resp_o (axi_l2_resp[i]), - .mem_req_o (mem_req[i] ), - .mem_gnt_i (mem_gnt[i] ), - .mem_addr_o (mem_addr[i] ), - .mem_wdata_o (mem_wdata[i] ), - .mem_strb_o (mem_strb[i] ), - .mem_atop_o (/*unused*/ ), - .mem_we_o (mem_we[i] ), - .mem_rvalid_i(mem_rvalid[i] ), - .mem_rdata_i (mem_rdata[i] ) + axi_to_reqrsp #( + .axi_req_t (axi_tile_req_t ), + .axi_rsp_t (axi_tile_resp_t), + .AddrWidth (L2AddrWidth ), + .DataWidth (AxiDataWidth ), + .IdWidth (AxiTileIdWidth ), + .BufDepth (3 ), + .reqrsp_req_t (axi_to_l2_req_t), + .reqrsp_rsp_t (axi_to_l2_rsp_t) + ) i_axi_to_reqrsp ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .busy_o (/*unused*/ ), + .axi_req_i (axi_l2_req[i] ), + .axi_rsp_o (axi_l2_resp[i] ), + .reqrsp_req_o (axi_to_l2_req[i]), + .reqrsp_rsp_i (axi_to_l2_rsp[i]) ); + // Repack the structs for the xbar + assign axi_to_l2_req_chan[i] = axi_to_l2_req[i].q; + assign axi_to_l2_q_valid[i] = axi_to_l2_req[i].q_valid; + assign axi_to_l2_rsp[i].q_ready = axi_to_l2_q_ready[i]; + assign axi_to_l2_rsp[i].p = axi_to_l2_rsp_chan[i]; + assign axi_to_l2_rsp[i].p_valid = axi_to_l2_p_valid[i]; + assign axi_to_l2_p_ready[i] = axi_to_l2_req[i].p_ready; + // Generate the selection signal + assign axi_to_l2_q_sel[i] = axi_to_l2_req_chan[i].addr[$clog2(L2BankBeWidth)+:NumL2BanksWidth]; end - variable_latency_interconnect #( - .NumIn (NumAXIMasters ), - .NumOut (NumL2Banks ), - .AddrWidth (L2AddrWidth ), - .DataWidth (L2BankWidth ), - .BeWidth (L2BankBeWidth ), - .AddrMemWidth (L2BankAddrWidth), - .AxiVldRdy (1'b1 ), - .SpillRegisterReq (64'b1 ), - .SpillRegisterResp(64'b1 ) - ) i_l2_xbar ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - // master side - .req_valid_i (mem_req ), - .req_ready_o (mem_gnt ), - .req_tgt_addr_i (mem_addr ), - .req_wen_i (mem_we ), - .req_wdata_i (mem_wdata ), - .req_be_i (mem_strb ), - .resp_valid_o (mem_rvalid ), - .resp_ready_i ('1 ), - .resp_rdata_o (mem_rdata ), - // slave side - .req_valid_o (bank_req ), - .req_ready_i ('1 ), - .req_ini_addr_o (bank_ini_d ), - .req_tgt_addr_o (bank_addr ), - .req_wen_o (bank_we ), - .req_wdata_o (bank_wdata ), - .req_be_o (bank_strb ), - .resp_valid_i (bank_rvalid), - .resp_ready_o (/*unused*/ ), // This only works because resp_ready_i = 1 - .resp_ini_addr_i(bank_ini_q ), - .resp_rdata_i (bank_rdata ) + stream_xbar #( + .NumInp (NumAXIMasters ), + .NumOut (NumL2Banks ), + .payload_t (axi_to_l2_req_chan_t), + .OutSpillReg (1'b1 ), + .ExtPrio (1'b0 ), + .AxiVldRdy (1'b1 ), + .LockIn (1'b1 ) + ) i_l2_req_xbar ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i (1'b0 ), + .rr_i ('0 ), + .data_i (axi_to_l2_req_chan), + .sel_i (axi_to_l2_q_sel ), + .valid_i (axi_to_l2_q_valid ), + .ready_o (axi_to_l2_q_ready ), + .data_o (mem_req_chan ), + .idx_o (axi_to_l2_q_idx ), + .valid_o (mem_req_valid ), + .ready_i (mem_req_ready ) ); - `FF(bank_rvalid, bank_req, 1'b0, clk_i, rst_ni) - `FF(bank_ini_q, bank_ini_d, 1'b0, clk_i, rst_ni) + stream_xbar #( + .NumInp (NumL2Banks ), + .NumOut (NumAXIMasters ), + .payload_t (axi_to_l2_rsp_chan_t), + .OutSpillReg (1'b0 ), + .ExtPrio (1'b0 ), + .AxiVldRdy (1'b1 ), + .LockIn (1'b1 ) + ) i_l2_rsp_xbar ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i (1'b0 ), + .rr_i ('0 ), + .data_i (mem_rsp_chan ), + .sel_i (axi_to_l2_p_sel ), + .valid_i (mem_rsp_valid ), + .ready_o (mem_rsp_ready ), + .data_o (axi_to_l2_rsp_chan), + .idx_o (/*unused*/ ), + .valid_o (axi_to_l2_p_valid ), + .ready_i (axi_to_l2_p_ready ) + ); // The initialization at reset is not supported by Verilator. Therefore, we disable the SimInit at // reset for Verilator. Since our preloading through the SystemVerilog testbench requires the // SimInit value to be assigned at reset, we use the "custom" string to invoke the initialization // without setting the memory to known values like "ones" or "zeros". localparam L2SimInit = `ifdef VERILATOR "none" `else "custom" `endif; + localparam L2BankAddrIndex = $clog2(L2BankBeWidth)+$clog2(NumL2Banks); for (genvar i = 0; i < NumL2Banks; i++) begin : gen_l2_banks + tcdm_adapter #( + .AddrWidth (L2BankAddrWidth ), + .DataWidth (L2BankWidth ), + .metadata_t (l2_axi_idx_t ), + .LrScEnable (1'b0 ), + .RegisterAmo(1'b0 ) + ) i_bank_adapter ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .in_valid_i (mem_req_valid[i] ), + .in_ready_o (mem_req_ready[i] ), + .in_address_i(mem_req_chan[i].addr[L2BankAddrIndex+:L2BankAddrWidth]), + .in_amo_i (mem_req_chan[i].amo ), + .in_write_i (mem_req_chan[i].write ), + .in_wdata_i (mem_req_chan[i].data ), + .in_meta_i (axi_to_l2_q_idx[i] ), + .in_be_i (mem_req_chan[i].strb ), + .in_valid_o (mem_rsp_valid[i] ), + .in_ready_i (mem_rsp_ready[i] ), + .in_rdata_o (mem_rsp_chan[i].data ), + .in_meta_o (axi_to_l2_p_sel[i] ), + .out_req_o (bank_req[i] ), + .out_add_o (bank_addr[i] ), + .out_write_o (bank_we[i] ), + .out_wdata_o (bank_wdata[i] ), + .out_be_o (bank_strb[i] ), + .out_rdata_i (bank_rdata[i] ) + ); + assign mem_rsp_chan[i].error = 1'b0; + tc_sram #( .DataWidth(L2BankWidth ), .NumWords (L2BankNumWords), From 5c13dddc1b18e7444b37d5d795f82b56fa62e180 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Tue, 5 Mar 2024 15:17:13 +0100 Subject: [PATCH 05/14] [hardware] Extend tcdm_adapter to support arbitrary widths --- hardware/src/mempool_system.sv | 16 +++-- hardware/src/mempool_tile.sv | 13 +++-- hardware/src/tcdm_adapter.sv | 104 +++++++++++++++++---------------- 3 files changed, 71 insertions(+), 62 deletions(-) diff --git a/hardware/src/mempool_system.sv b/hardware/src/mempool_system.sv index 9fdc07e1c..b5479a387 100644 --- a/hardware/src/mempool_system.sv +++ b/hardware/src/mempool_system.sv @@ -357,18 +357,22 @@ module mempool_system localparam L2SimInit = `ifdef VERILATOR "none" `else "custom" `endif; localparam L2BankAddrIndex = $clog2(L2BankBeWidth)+$clog2(NumL2Banks); for (genvar i = 0; i < NumL2Banks; i++) begin : gen_l2_banks + // Address scrambling: Cut out the bits used to index the individual banks + logic [AddrWidth-1:0] addr_scrambled; + assign addr_scrambled = {'0, mem_req_chan[i].addr[AddrWidth-1:L2BankAddrIndex], mem_req_chan[i].addr[0+:$clog2(L2BankBeWidth)]}; tcdm_adapter #( - .AddrWidth (L2BankAddrWidth ), - .DataWidth (L2BankWidth ), - .metadata_t (l2_axi_idx_t ), - .LrScEnable (1'b0 ), - .RegisterAmo(1'b0 ) + .AddrWidth (AddrWidth ), + .BankAddrWidth (L2BankAddrWidth ), + .DataWidth (L2BankWidth ), + .metadata_t (l2_axi_idx_t ), + .LrScEnable (1'b0 ), + .RegisterAmo (1'b0 ) ) i_bank_adapter ( .clk_i (clk_i ), .rst_ni (rst_ni ), .in_valid_i (mem_req_valid[i] ), .in_ready_o (mem_req_ready[i] ), - .in_address_i(mem_req_chan[i].addr[L2BankAddrIndex+:L2BankAddrWidth]), + .in_address_i(addr_scrambled ), .in_amo_i (mem_req_chan[i].amo ), .in_write_i (mem_req_chan[i].write ), .in_wdata_i (mem_req_chan[i].data ), diff --git a/hardware/src/mempool_tile.sv b/hardware/src/mempool_tile.sv index 6a9bad452..961488bc4 100644 --- a/hardware/src/mempool_tile.sv +++ b/hardware/src/mempool_tile.sv @@ -510,17 +510,18 @@ module mempool_tile assign bank_resp_wide[b] = meta_out.wide; tcdm_adapter #( - .AddrWidth (TCDMAddrMemWidth), - .DataWidth (DataWidth ), - .metadata_t (bank_metadata_t ), - .LrScEnable (LrScEnable ), - .RegisterAmo(1'b0 ) + .AddrWidth (TCDMAddrMemWidth+ByteOffset), + .BankAddrWidth (TCDMAddrMemWidth ), + .DataWidth (DataWidth ), + .metadata_t (bank_metadata_t ), + .LrScEnable (LrScEnable ), + .RegisterAmo (1'b0 ) ) i_tcdm_adapter ( .clk_i (clk_i ), .rst_ni (rst_ni ), .in_valid_i (bank_req_valid[b] ), .in_ready_o (bank_req_ready[b] ), - .in_address_i(bank_req_payload[b].tgt_addr[idx_width(NumBanksPerTile) +: TCDMAddrMemWidth]), + .in_address_i({bank_req_payload[b].tgt_addr[idx_width(NumBanksPerTile) +: TCDMAddrMemWidth],{ByteOffset{1'b0}}}), .in_amo_i (bank_req_payload[b].wdata.amo ), .in_write_i (bank_req_payload[b].wen ), .in_wdata_i (bank_req_payload[b].wdata.data ), diff --git a/hardware/src/tcdm_adapter.sv b/hardware/src/tcdm_adapter.sv index 6723f8070..72c3cb2c3 100644 --- a/hardware/src/tcdm_adapter.sv +++ b/hardware/src/tcdm_adapter.sv @@ -11,37 +11,38 @@ `include "common_cells/registers.svh" module tcdm_adapter #( - parameter int unsigned AddrWidth = 32, - parameter int unsigned DataWidth = 32, - parameter type metadata_t = logic, - parameter bit LrScEnable = 1, + parameter int unsigned AddrWidth = 32, + parameter int unsigned BankAddrWidth = AddrWidth, + parameter int unsigned DataWidth = 32, + parameter type metadata_t = logic, + parameter bit LrScEnable = 1, // Cut path between request and response at the cost of increased AMO latency parameter bit RegisterAmo = 1'b0, // Dependent parameters. DO NOT CHANGE. localparam int unsigned BeWidth = DataWidth/8 ) ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, // master side - input logic in_valid_i, // Bank request - output logic in_ready_o, // Bank grant - input logic [AddrWidth-1:0] in_address_i, // Address - input logic [3:0] in_amo_i, // Atomic Memory Operation - input logic in_write_i, // 1: Store, 0: Load - input logic [DataWidth-1:0] in_wdata_i, // Write data - input metadata_t in_meta_i, // Meta data - input logic [BeWidth-1:0] in_be_i, // Byte enable - output logic in_valid_o, // Read data - input logic in_ready_i, // Read data - output logic [DataWidth-1:0] in_rdata_o, // Read data - output metadata_t in_meta_o, // Meta data + input logic in_valid_i, // Bank request + output logic in_ready_o, // Bank grant + input logic [AddrWidth-1:0] in_address_i, // Address + input logic [3:0] in_amo_i, // Atomic Memory Operation + input logic in_write_i, // 1: Store, 0: Load + input logic [DataWidth-1:0] in_wdata_i, // Write data + input metadata_t in_meta_i, // Meta data + input logic [BeWidth-1:0] in_be_i, // Byte enable + output logic in_valid_o, // Read data + input logic in_ready_i, // Read data + output logic [DataWidth-1:0] in_rdata_o, // Read data + output metadata_t in_meta_o, // Meta data // slave side - output logic out_req_o, // Bank request - output logic [AddrWidth-1:0] out_add_o, // Address - output logic out_write_o, // 1: Store, 0: Load - output logic [DataWidth-1:0] out_wdata_o, // Write data - output logic [BeWidth-1:0] out_be_o, // Bit enable - input logic [DataWidth-1:0] out_rdata_i // Read data + output logic out_req_o, // Bank request + output logic [BankAddrWidth-1:0] out_add_o, // Address + output logic out_write_o, // 1: Store, 0: Load + output logic [DataWidth-1:0] out_wdata_o, // Write data + output logic [BeWidth-1:0] out_be_o, // Bit enable + input logic [DataWidth-1:0] out_rdata_i // Read data ); import mempool_pkg::NumCores; @@ -49,6 +50,8 @@ module tcdm_adapter #( import mempool_pkg::NumCoresPerTile; import cf_math_pkg::idx_width; + localparam int unsigned AmoWidth = 32; // Only 32 is tested for now + typedef enum logic [3:0] { AMONone = 4'h0, AMOSwap = 4'h1, @@ -77,15 +80,19 @@ module tcdm_adapter #( Idle, DoAMO, WriteBackAMO } state_q, state_d; - logic load_amo; - amo_op_t amo_op_q; - logic amo_wb; - logic [BeWidth-1:0] be_expand; - logic [AddrWidth-1:0] addr_q; + logic load_amo; + amo_op_t amo_op_q; + logic amo_wb; + logic [BankAddrWidth-1:0] in_address_bank; + + logic [AddrWidth-1:0] amo_addr_q; + logic [BeWidth-1:0] amo_be_q; + logic [AmoWidth-1:0] amo_operand_a; + logic [AmoWidth-1:0] amo_operand_b_q; + logic [AmoWidth-1:0] amo_result, amo_result_q; - logic [31:0] amo_operand_a; - logic [31:0] amo_operand_b_q; - logic [31:0] amo_result, amo_result_q; + // Cut off the bits indexing the bytes of the same bank word + assign in_address_bank = in_address_i[$clog2(BeWidth)+:BankAddrWidth]; // Store the metadata at handshake spill_register #( @@ -161,7 +168,7 @@ module tcdm_adapter #( /// This address is aligned to the memory size /// implying that the reservation happen on a set size /// equal to the word width of the memory (32 or 64 bit). - logic [AddrWidth-1:0] addr; + logic [BankAddrWidth-1:0] addr; /// Which core made this reservation. Important to /// track the reservations from different cores and /// to prevent any live-locking. @@ -200,7 +207,7 @@ module tcdm_adapter #( if (amo_op_t'(in_amo_i) == AMOLR && (!reservation_q.valid || reservation_q.core == unique_core_id)) begin reservation_d.valid = 1'b1; - reservation_d.addr = in_address_i; + reservation_d.addr = in_address_bank; reservation_d.core = unique_core_id; end @@ -211,7 +218,7 @@ module tcdm_adapter #( // check whether another core has made a write attempt if ((unique_core_id != reservation_q.core) && - (in_address_i == reservation_q.addr) && + (in_address_bank == reservation_q.addr) && (!(amo_op_t'(in_amo_i) inside {AMONone, AMOLR, AMOSC}) || in_write_i)) begin reservation_d.valid = 1'b0; end @@ -220,7 +227,7 @@ module tcdm_adapter #( if (reservation_q.valid && amo_op_t'(in_amo_i) == AMOSC && reservation_q.core == unique_core_id) begin reservation_d.valid = 1'b0; - sc_successful_d = (reservation_q.addr == in_address_i); + sc_successful_d = (reservation_q.addr == in_address_bank); end end end // always_comb @@ -238,7 +245,7 @@ module tcdm_adapter #( // feed-through in_ready_o = rdata_ready; out_req_o = in_valid_i && in_ready_o; - out_add_o = in_address_i; + out_add_o = in_address_bank; out_write_o = in_write_i || (sc_successful_d && (amo_op_t'(in_amo_i) == AMOSC)); out_wdata_o = in_wdata_i; out_be_o = in_be_i; @@ -262,13 +269,13 @@ module tcdm_adapter #( amo_wb = 1'b1; out_req_o = 1'b1; out_write_o = 1'b1; - out_add_o = addr_q; - out_be_o = 4'b1111; + out_add_o = amo_addr_q[$clog2(BeWidth)+:BankAddrWidth]; + out_be_o = amo_be_q; // serve from register if we cut the path if (RegisterAmo) begin - out_wdata_o = amo_result_q; + out_wdata_o[amo_addr_q[0+:$clog2(BeWidth)]*8+:AmoWidth] = amo_result_q; end else begin - out_wdata_o = amo_result; + out_wdata_o[amo_addr_q[0+:$clog2(BeWidth)]*8+:AmoWidth] = amo_result; end end default:; @@ -285,14 +292,16 @@ module tcdm_adapter #( if (!rst_ni) begin state_q <= Idle; amo_op_q <= amo_op_t'('0); - addr_q <= '0; + amo_addr_q <= '0; + amo_be_q <= '0; amo_operand_b_q <= '0; end else begin state_q <= state_d; if (load_amo) begin amo_op_q <= amo_op_t'(in_amo_i); - addr_q <= in_address_i; - amo_operand_b_q <= in_wdata_i; + amo_addr_q <= in_address_i; + amo_be_q <= in_be_i; + amo_operand_b_q <= in_wdata_i[in_address_i[0+:$clog2(BeWidth)]*8+:AmoWidth]; end else begin amo_op_q <= AMONone; end @@ -305,7 +314,7 @@ module tcdm_adapter #( logic [33:0] adder_sum; logic [32:0] adder_operand_a, adder_operand_b; - assign amo_operand_a = out_rdata_i; + assign amo_operand_a = out_rdata_i[amo_addr_q[0+:$clog2(BeWidth)]*8+:AmoWidth]; assign adder_sum = adder_operand_a + adder_operand_b; /* verilator lint_off WIDTH */ always_comb begin : amo_alu @@ -345,11 +354,6 @@ module tcdm_adapter #( end // pragma translate_off - // Check for unsupported parameters - if (DataWidth != 32) begin - $error($sformatf("Module currently only supports DataWidth = 32. DataWidth is currently set to: %0d", DataWidth)); - end - `ifndef VERILATOR assert_rdata_full : assert property( @(posedge clk_i) disable iff (~rst_ni) (out_gnt |-> !rdata_full)) From 7f5c6c39337277c0621655ba4a169e5edc142b6d Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Wed, 28 Aug 2024 16:02:59 +0200 Subject: [PATCH 06/14] [software] Add atomics tests --- CHANGELOG.md | 1 + software/tests/baremetal/atomics/main.c | 142 ++++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 software/tests/baremetal/atomics/main.c diff --git a/CHANGELOG.md b/CHANGELOG.md index 76793e524..8b316f598 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Add `apb` dependency of version 0.2.4 - Add support for the `FENCE` instruction - Add support for DRAMsys5.0 co-simulation +- Add support for atomics in L2 ### Changes - Add physical feasible TeraPool configuration with SubGroup hierarchy. diff --git a/software/tests/baremetal/atomics/main.c b/software/tests/baremetal/atomics/main.c new file mode 100644 index 000000000..850deb476 --- /dev/null +++ b/software/tests/baremetal/atomics/main.c @@ -0,0 +1,142 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Author: Samuel Riedel, ETH Zurich + +#include +#include + +#include "runtime.h" + +uint32_t volatile l1 __attribute__((section(".l1"))); +uint32_t volatile l2 __attribute__((section(".l2"))); + +int atomics(uint32_t volatile *addr) { + uint32_t golden, ret, op; + + // Init + *addr = 0x12345678; + + // AMO Swap + golden = *addr; + op = 0x23456789; + asm volatile("amoswap.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 1; + } + + // AMO Add + golden = *addr; + op = 0x199; + asm volatile("amoadd.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 11; + } + if (*addr != golden + op) { + return 12; + } + + // AMO Xor + golden = *addr; + op = 0x12345678; + asm volatile("amoxor.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 21; + } + if (*addr != (golden ^ op)) { + return 22; + } + + // AMO And + golden = *addr; + op = 0x0000FF33; + asm volatile("amoand.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 31; + } + if (*addr != (golden & op)) { + return 32; + } + + // AMO Or + golden = *addr; + op = 0x12340000; + asm volatile("amoor.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 41; + } + if (*addr != (golden | op)) { + return 42; + } + + // AMO Min + golden = *addr; + op = 0xF0000001; + asm volatile("amomin.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 51; + } + if (*addr != ((int32_t)golden < (int32_t)op ? golden : op)) { + return 52; + } + + // AMO Max + golden = *addr; + op = 0x00000001; + asm volatile("amomax.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 61; + } + if (*addr != ((int32_t)golden > (int32_t)op ? golden : op)) { + return 62; + } + + // AMO UMin + golden = *addr; + op = 0x00000010; + asm volatile("amominu.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 71; + } + if (*addr != (golden < op ? golden : op)) { + return 72; + } + + // AMO UMax + golden = *addr; + op = 0x00000010; + asm volatile("amomaxu.w %0, %1, (%2)" : "=r"(ret) : "r"(op), "r"(addr)); + if (ret != golden) { + return 81; + } + if (*addr != (golden > op ? golden : op)) { + return 82; + } + + return 0; +} + +int main() { + uint32_t core_id = mempool_get_core_id(); + + if (core_id != 0) { + mempool_wfi(); + } + + int ret = 0; + + // L1 memory + ret = atomics(&l1); + if (ret) { + return ret; + } + + // L2 memory + ret = atomics(&l2); + if (ret) { + return ret + 100; + } + + return 0; +} From 99500e47fc4a409067327c45b951c39960c1d754 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Fri, 5 Apr 2024 15:24:11 +0200 Subject: [PATCH 07/14] [hardware] Replicate the cluster and DMAs for a multi-cluster config --- config/config.mk | 3 + config/multipool.mk | 49 +++++++++++ hardware/Makefile | 1 + hardware/src/mempool_cluster.sv | 38 ++++----- hardware/src/mempool_pkg.sv | 33 +++++--- hardware/src/mempool_system.sv | 110 ++++++++++++------------ hardware/tb/mempool_tb.sv | 146 +++++++++++++++++--------------- 7 files changed, 230 insertions(+), 150 deletions(-) create mode 100644 config/multipool.mk diff --git a/config/config.mk b/config/config.mk index 9ea9a0fd0..e579fec8a 100644 --- a/config/config.mk +++ b/config/config.mk @@ -21,6 +21,9 @@ ifndef config endif include $(MEMPOOL_DIR)/config/$(config).mk +# Number of clusters +num_clusters ?= 1 + ############################# ## Address configuration ## ############################# diff --git a/config/multipool.mk b/config/multipool.mk new file mode 100644 index 000000000..ecb8f6faf --- /dev/null +++ b/config/multipool.mk @@ -0,0 +1,49 @@ +# Copyright 2021 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Samuel Riedel, ETH Zurich + +############### +## MemPool ## +############### + +# Number of cores +num_cores ?= 64 + +# Number of groups +num_groups ?= 16 + +# Number of clusters +num_clusters ?= 4 + +# Number of cores per MemPool tile +num_cores_per_tile ?= 4 + +# L1 scratchpad banking factor +banking_factor ?= 4 + +# Radix for hierarchical AXI interconnect +axi_hier_radix ?= 20 + +# Number of AXI masters per group +axi_masters_per_group ?= 1 + + +######################### +## AXI configuration ## +######################### +# AXI bus data width (in bits) +axi_data_width ?= 512 + +# Read-only cache line width in AXI interconnect (in bits) +ro_line_width ?= 512 + +# Number of DMA backends in each group +dmas_per_group ?= 1 + +# Radix for hierarchical AXI interconnect +axi_hier_radix ?= 2 + +# Number of AXI masters per group +axi_masters_per_group ?= 1 diff --git a/hardware/Makefile b/hardware/Makefile index 6de18eb4f..3ce1ea784 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -113,6 +113,7 @@ vlog_defs += -DNUM_CORES=$(num_cores) vlog_defs += -DNUM_CORES_PER_TILE=$(num_cores_per_tile) vlog_defs += -DNUM_DIVSQRT_PER_TILE=$(num_divsqrt_per_tile) vlog_defs += -DNUM_GROUPS=$(num_groups) +vlog_defs += -DNUM_CLUSTERS=$(num_clusters) vlog_defs += -DBANKING_FACTOR=$(banking_factor) vlog_defs += -DL2_BASE=32\'d$(l2_base) vlog_defs += -DL2_SIZE=32\'d$(l2_size) diff --git a/hardware/src/mempool_cluster.sv b/hardware/src/mempool_cluster.sv index 561e0d369..8aefd9c17 100644 --- a/hardware/src/mempool_cluster.sv +++ b/hardware/src/mempool_cluster.sv @@ -17,32 +17,32 @@ module mempool_cluster parameter int unsigned NumAXIMasters = NumGroups * NumAXIMastersPerGroup ) ( // Clock and reset - input logic clk_i, - input logic rst_ni, - input logic testmode_i, + input logic clk_i, + input logic rst_ni, + input logic testmode_i, // Scan chain - input logic scan_enable_i, - input logic scan_data_i, - output logic scan_data_o, + input logic scan_enable_i, + input logic scan_data_i, + output logic scan_data_o, // Wake up signal - input logic [NumCores-1:0] wake_up_i, + input logic [NumCoresPerCluster-1:0] wake_up_i, // RO-Cache configuration - input ro_cache_ctrl_t ro_cache_ctrl_i, + input ro_cache_ctrl_t ro_cache_ctrl_i, // DMA request - input dma_req_t dma_req_i, - input logic dma_req_valid_i, - output logic dma_req_ready_o, + input dma_req_t dma_req_i, + input logic dma_req_valid_i, + output logic dma_req_ready_o, // DMA status - output dma_meta_t dma_meta_o, + output dma_meta_t dma_meta_o, // AXI Interface - output axi_tile_req_t [NumAXIMasters-1:0] axi_mst_req_o, - input axi_tile_resp_t [NumAXIMasters-1:0] axi_mst_resp_i + output axi_tile_req_t [NumAXIMasters-1:0] axi_mst_req_o, + input axi_tile_resp_t [NumAXIMasters-1:0] axi_mst_resp_i ); /********************* * Control Signals * *********************/ - logic [NumCores-1:0] wake_up_q; + logic [NumCoresPerCluster-1:0] wake_up_q; `FF(wake_up_q, wake_up_i, '0, clk_i, rst_ni); ro_cache_ctrl_t [NumGroups-1:0] ro_cache_ctrl_q; @@ -494,13 +494,13 @@ module mempool_cluster * Assertions * ****************/ - if (NumCores > 1024) - $fatal(1, "[mempool] MemPool is currently limited to 1024 cores."); + if (NumCoresPerCluster > 1024) + $fatal(1, "[mempool] The MemPool cluster is currently limited to 1024 cores."); - if (NumTiles < NumGroups) + if (NumTilesPerCluster < NumGroupsPerCluster) $fatal(1, "[mempool] MemPool requires more tiles than groups."); - if (NumCores != NumTiles * NumCoresPerTile) + if (NumCoresPerCluster != NumTilesPerCluster * NumCoresPerTile) $fatal(1, "[mempool] The number of cores is not divisible by the number of cores per tile."); if (BankingFactor < 1) diff --git a/hardware/src/mempool_pkg.sv b/hardware/src/mempool_pkg.sv index 5d427feec..62aa02fdd 100644 --- a/hardware/src/mempool_pkg.sv +++ b/hardware/src/mempool_pkg.sv @@ -14,19 +14,23 @@ package mempool_pkg; `include "axi/assign.svh" `include "axi/typedef.svh" - localparam integer unsigned NumCores = `ifdef NUM_CORES `NUM_CORES `else 0 `endif; - localparam integer unsigned NumCoresPerTile = `ifdef NUM_CORES_PER_TILE `NUM_CORES_PER_TILE `else 0 `endif; - localparam integer unsigned NumDivsqrtPerTile = `ifdef NUM_DIVSQRT_PER_TILE `NUM_DIVSQRT_PER_TILE `else (snitch_pkg::XDIVSQRT) `endif; - localparam integer unsigned NumGroups = `ifdef NUM_GROUPS `NUM_GROUPS `else 0 `endif; - localparam integer unsigned MAX_NumGroups = 8; - localparam integer unsigned NumTiles = NumCores / NumCoresPerTile; - localparam integer unsigned NumTilesPerGroup = NumTiles / NumGroups; - localparam integer unsigned NumCoresPerGroup = NumCores / NumGroups; - localparam integer unsigned NumCoresPerCache = NumCoresPerTile; - localparam integer unsigned AxiCoreIdWidth = 1; - localparam integer unsigned AxiTileIdWidth = AxiCoreIdWidth+1; // + 1 for cache - localparam integer unsigned AxiDataWidth = `ifdef AXI_DATA_WIDTH `AXI_DATA_WIDTH `else 0 `endif; - localparam integer unsigned AxiLiteDataWidth = 32; + localparam integer unsigned NumCores = `ifdef NUM_CORES `NUM_CORES `else 0 `endif; + localparam integer unsigned NumCoresPerTile = `ifdef NUM_CORES_PER_TILE `NUM_CORES_PER_TILE `else 0 `endif; + localparam integer unsigned NumDivsqrtPerTile = `ifdef NUM_DIVSQRT_PER_TILE `NUM_DIVSQRT_PER_TILE `else (snitch_pkg::XDIVSQRT) `endif; + localparam integer unsigned NumGroups = `ifdef NUM_GROUPS `NUM_GROUPS `else 0 `endif; + localparam integer unsigned NumClusters = `ifdef NUM_CLUSTERS `NUM_CLUSTERS `else 0 `endif; + localparam integer unsigned MAX_NumGroups = 32; + localparam integer unsigned NumGroupsPerCluster = NumGroups / NumClusters; + localparam integer unsigned NumTiles = NumCores / NumCoresPerTile; + localparam integer unsigned NumTilesPerCluster = NumTiles / NumClusters; + localparam integer unsigned NumTilesPerGroup = NumTiles / NumGroups; + localparam integer unsigned NumCoresPerCluster = NumCores / NumClusters; + localparam integer unsigned NumCoresPerGroup = NumCores / NumGroups; + localparam integer unsigned NumCoresPerCache = NumCoresPerTile; + localparam integer unsigned AxiCoreIdWidth = 1; + localparam integer unsigned AxiTileIdWidth = AxiCoreIdWidth+1; // + 1 for cache + localparam integer unsigned AxiDataWidth = `ifdef AXI_DATA_WIDTH `AXI_DATA_WIDTH `else 0 `endif; + localparam integer unsigned AxiLiteDataWidth = 32; /*********************** * MEMORY PARAMETERS * @@ -36,10 +40,13 @@ package mempool_pkg; localparam integer unsigned DataWidth = 32; localparam integer unsigned BeWidth = DataWidth / 8; localparam integer unsigned ByteOffset = $clog2(BeWidth); + // L1 SPM memory localparam integer unsigned BankingFactor = `ifdef BANKING_FACTOR `BANKING_FACTOR `else 0 `endif; localparam bit LrScEnable = 1'b1; localparam integer unsigned TCDMSizePerBank = `ifdef L1_BANK_SIZE `L1_BANK_SIZE `else 0 `endif; localparam integer unsigned NumBanks = NumCores * BankingFactor; + localparam integer unsigned L1Size = NumCores * BankingFactor * TCDMSizePerBank; + localparam integer unsigned L1SizePerCluster = L1Size / NumClusters; localparam integer unsigned NumBanksPerTile = NumBanks / NumTiles; localparam integer unsigned NumBanksPerGroup = NumBanks / NumGroups; localparam integer unsigned TCDMAddrMemWidth = $clog2(TCDMSizePerBank / mempool_pkg::BeWidth); diff --git a/hardware/src/mempool_system.sv b/hardware/src/mempool_system.sv index b5479a387..9dab93693 100644 --- a/hardware/src/mempool_system.sv +++ b/hardware/src/mempool_system.sv @@ -91,11 +91,11 @@ module mempool_system logic [DataWidth-1:0] eoc; ro_cache_ctrl_t ro_cache_ctrl; - dma_req_t dma_req; - logic dma_req_valid; - logic dma_req_ready; - dma_meta_t dma_meta; - logic [1-1:0] dma_id; + dma_req_t[NumClusters-1:0] dma_req; + logic[NumClusters-1:0] dma_req_valid; + logic[NumClusters-1:0] dma_req_ready; + dma_meta_t[NumClusters-1:0] dma_meta; + logic[NumClusters-1:0][1-1:0] dma_id; localparam xbar_cfg_t MstDemuxCfg = '{ NoSlvPorts : 1, // Each master has a private demux @@ -132,26 +132,27 @@ module mempool_system /********************* * MemPool Cluster * ********************/ - - mempool_cluster #( - .TCDMBaseAddr(TCDMBaseAddr), - .BootAddr (BootAddr ) - ) i_mempool_cluster ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .wake_up_i (wake_up ), - .testmode_i (1'b0 ), - .scan_enable_i (1'b0 ), - .scan_data_i (1'b0 ), - .scan_data_o (/* Unused */ ), - .ro_cache_ctrl_i(ro_cache_ctrl ), - .dma_req_i (dma_req ), - .dma_req_valid_i(dma_req_valid ), - .dma_req_ready_o(dma_req_ready ), - .dma_meta_o (dma_meta ), - .axi_mst_req_o (axi_mst_req[NumAXIMasters-2:0] ), - .axi_mst_resp_i (axi_mst_resp[NumAXIMasters-2:0]) - ); + for (genvar i = 0; i < NumClusters; i++) begin : gen_clusters + mempool_cluster #( + .TCDMBaseAddr(i*L1SizePerCluster), + .BootAddr (BootAddr ) + ) i_mempool_cluster ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .wake_up_i (wake_up[i*NumCoresPerCluster+:NumCoresPerCluster] ), + .testmode_i (1'b0 ), + .scan_enable_i (1'b0 ), + .scan_data_i (1'b0 ), + .scan_data_o (/* Unused */ ), + .ro_cache_ctrl_i(ro_cache_ctrl ), + .dma_req_i (dma_req[i] ), + .dma_req_valid_i(dma_req_valid[i] ), + .dma_req_ready_o(dma_req_ready[i] ), + .dma_meta_o (dma_meta[i] ), + .axi_mst_req_o (axi_mst_req[i*NumAXIMastersPerGroup+:NumAXIMastersPerGroup] ), + .axi_mst_resp_i (axi_mst_resp[i*NumAXIMastersPerGroup+:NumAXIMastersPerGroup]) + ); + end /********************** * AXI Interconnect * @@ -658,12 +659,14 @@ module mempool_system * Control Registers * ***********************/ - localparam NumPeriphs = 2; // Control registers + DMA + localparam NumPeriphs = 1 + NumClusters; // Control registers + (NumClusters * DMA) - typedef enum logic [$clog2(NumPeriphs) - 1:0] { - CtrlRegisters, - DMA - } axi_lite_xbar_slave_target; + localparam CtrlRegisters = 0; + localparam DMA = 1; + // typedef enum logic [$clog2(NumPeriphs) - 1:0] { + // CtrlRegisters, + // DMA + // } axi_lite_xbar_slave_target; axi_periph_req_t axi_periph_narrow_req; axi_periph_resp_t axi_periph_narrow_resp; @@ -692,12 +695,13 @@ module mempool_system localparam addr_t CtrlRegistersEndAddr = 32'h4001_0000; localparam addr_t DMABaseAddr = 32'h4001_0000; localparam addr_t DMAEndAddr = 32'h4002_0000; + localparam addr_t DMARangeAddr = DMAEndAddr - DMABaseAddr; xbar_rule_32_t [NumPeriphs-1:0] axi_lite_xbar_rules; - assign axi_lite_xbar_rules = '{ - '{idx: CtrlRegisters, start_addr: CtrlRegistersBaseAddr, end_addr: CtrlRegistersEndAddr}, - '{idx: DMA, start_addr: DMABaseAddr, end_addr: DMAEndAddr} - }; + assign axi_lite_xbar_rules[CtrlRegisters] = '{idx: CtrlRegisters, start_addr: CtrlRegistersBaseAddr, end_addr: CtrlRegistersEndAddr}; + for (genvar i = 0; i < NumClusters; i++) begin : gen_dma_addr_map + assign axi_lite_xbar_rules[DMA + i] = '{idx: DMA + i, start_addr: DMABaseAddr+(i*DMARangeAddr), end_addr: DMAEndAddr+(i*DMARangeAddr)}; + end axi_dw_converter #( .AxiMaxReads (1 ), // Number of outstanding reads @@ -789,24 +793,26 @@ module mempool_system .ro_cache_ctrl_o (ro_cache_ctrl ) ); - mempool_dma #( - .axi_lite_req_t(axi_lite_slv_req_t ), - .axi_lite_rsp_t(axi_lite_slv_resp_t ), - .burst_req_t (dma_req_t ), - .NumBackends (NumGroups ), - .DmaIdWidth (1 ) - ) i_mempool_dma ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .config_req_i (axi_lite_slv_req[DMA] ), - .config_res_o (axi_lite_slv_resp[DMA] ), - .burst_req_o (dma_req ), - .valid_o (dma_req_valid ), - .ready_i (dma_req_ready ), - .backend_idle_i (dma_meta.backend_idle ), - .trans_complete_i(dma_meta.trans_complete), - .dma_id_o (dma_id ) - ); + for (genvar i = 0; i < NumClusters; i++) begin : gen_mempool_dma + mempool_dma #( + .axi_lite_req_t(axi_lite_slv_req_t ), + .axi_lite_rsp_t(axi_lite_slv_resp_t ), + .burst_req_t (dma_req_t ), + .NumBackends (NumGroupsPerCluster ), + .DmaIdWidth (1 ) + ) i_mempool_dma ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .config_req_i (axi_lite_slv_req[DMA+i] ), + .config_res_o (axi_lite_slv_resp[DMA+i] ), + .burst_req_o (dma_req[i] ), + .valid_o (dma_req_valid[i] ), + .ready_i (dma_req_ready[i] ), + .backend_idle_i (dma_meta[i].backend_idle ), + .trans_complete_i(dma_meta[i].trans_complete), + .dma_id_o (dma_id[i] ) + ); + end assign busy_o = 1'b0; diff --git a/hardware/tb/mempool_tb.sv b/hardware/tb/mempool_tb.sv index 9d6a04928..8c9a50663 100644 --- a/hardware/tb/mempool_tb.sv +++ b/hardware/tb/mempool_tb.sv @@ -194,23 +194,27 @@ module mempool_tb; logic [NumCores-1:0] wfi; `ifdef TERAPOOL - for (genvar g = 0; g < NumGroups; g++) begin: gen_wfi_groups - for (genvar sg = 0; sg < NumSubGroupsPerGroup; sg++) begin: gen_wfi_sub_groups - for (genvar t = 0; t < NumTilesPerSubGroup; t++) begin: gen_wfi_tiles + for (genvar cl = 0; cl < NumClusters; cl++) begin: gen_wfi_clusters + for (genvar g = 0; g < NumGroupsPerCluster; g++) begin: gen_wfi_groups + for (genvar sg = 0; sg < NumSubGroupsPerGroup; sg++) begin: gen_wfi_sub_groups + for (genvar t = 0; t < NumTilesPerSubGroup; t++) begin: gen_wfi_tiles + for (genvar c = 0; c < NumCoresPerTile; c++) begin: gen_wfi_cores + assign wfi[cl*NumCoresPerCluster + g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.wfi_q; + end: gen_wfi_cores + end: gen_wfi_tiles + end: gen_wfi_sub_groups + end: gen_wfi_groups + end: gen_wfi_clusters + `else + for (genvar cl = 0; cl < NumClusters; cl++) begin: gen_wfi_clusters + for (genvar g = 0; g < NumGroupsPerCluster; g++) begin: gen_wfi_groups + for (genvar t = 0; t < NumTilesPerGroup; t++) begin: gen_wfi_tiles for (genvar c = 0; c < NumCoresPerTile; c++) begin: gen_wfi_cores - assign wfi[g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = dut.i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.wfi_q; + assign wfi[cl*NumCoresPerCluster + g*NumCoresPerGroup + t*NumCoresPerTile + c] = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.wfi_q; end: gen_wfi_cores end: gen_wfi_tiles - end: gen_wfi_sub_groups - end: gen_wfi_groups - `else - for (genvar g = 0; g < NumGroups; g++) begin: gen_wfi_groups - for (genvar t = 0; t < NumTilesPerGroup; t++) begin: gen_wfi_tiles - for (genvar c = 0; c < NumCoresPerTile; c++) begin: gen_wfi_cores - assign wfi[g*NumTilesPerGroup*NumCoresPerTile + t*NumCoresPerTile + c] = dut.i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.wfi_q; - end: gen_wfi_cores - end: gen_wfi_tiles - end: gen_wfi_groups + end: gen_wfi_groups + end: gen_wfi_clusters `endif `endif @@ -403,43 +407,47 @@ module mempool_tb; assign lsu_utilization = $countones(lsu_handshake); assign lsu_pressure = $countones(lsu_request); `ifdef TERAPOOL - for (genvar g = 0; g < NumGroups; g++) begin - for (genvar sg = 0; sg < NumSubGroupsPerGroup; sg++) begin - for (genvar t = 0; t < NumTilesPerSubGroup; t++) begin + for (genvar cl = 0; cl < NumClusters; cl++) begin + for (genvar g = 0; g < NumGroupsPerCluster; g++) begin + for (genvar sg = 0; sg < NumSubGroupsPerGroup; sg++) begin + for (genvar t = 0; t < NumTilesPerSubGroup; t++) begin + for (genvar c = 0; c < NumCoresPerTile; c++) begin + logic valid_instr, stall; + logic lsu_valid, lsu_ready; + // Snitch + assign valid_instr = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.valid_instr; + assign stall = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.stall; + assign instruction_handshake[cl*NumCoresPerCluster+g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = valid_instr & !stall; + // Interconnect + assign lsu_valid = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.data_qvalid_o; + assign lsu_ready = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.data_qready_i; + assign lsu_request[cl*NumCoresPerCluster+g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = lsu_valid & !lsu_ready; + assign lsu_handshake[cl*NumCoresPerCluster+g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = lsu_valid & lsu_ready; + end + end + end + end + end + `else + for (genvar cl = 0; cl < NumClusters; cl++) begin + for (genvar g = 0; g < NumGroupsPerCluster; g++) begin + for (genvar t = 0; t < NumTilesPerGroup; t++) begin for (genvar c = 0; c < NumCoresPerTile; c++) begin logic valid_instr, stall; logic lsu_valid, lsu_ready; // Snitch - assign valid_instr = dut.i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.valid_instr; - assign stall = dut.i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.stall; - assign instruction_handshake[g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = valid_instr & !stall; + assign valid_instr = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.valid_instr; + assign stall = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.stall; + assign instruction_handshake[cl*NumCoresPerCluster+g*NumCoresPerGroup+t*NumCoresPerTile+c] = valid_instr & !stall; // Interconnect - assign lsu_valid = dut.i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.data_qvalid_o; - assign lsu_ready = dut.i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.data_qready_i; - assign lsu_request[g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = lsu_valid & !lsu_ready; - assign lsu_handshake[g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = lsu_valid & lsu_ready; + assign lsu_valid = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.data_qvalid_o; + assign lsu_ready = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.data_qready_i; + assign lsu_request[cl*NumCoresPerCluster+g*NumCoresPerGroup+t*NumCoresPerTile+c] = lsu_valid & !lsu_ready; + assign lsu_handshake[cl*NumCoresPerCluster+g*NumCoresPerGroup+t*NumCoresPerTile+c] = lsu_valid & lsu_ready; end end end end - `else - for (genvar g = 0; g < NumGroups; g++) begin - for (genvar t = 0; t < NumTilesPerGroup; t++) begin - for (genvar c = 0; c < NumCoresPerTile; c++) begin - logic valid_instr, stall; - logic lsu_valid, lsu_ready; - // Snitch - assign valid_instr = dut.i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.valid_instr; - assign stall = dut.i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.stall; - assign instruction_handshake[g*NumTilesPerGroup*NumCoresPerTile+t*NumCoresPerTile+c] = valid_instr & !stall; - // Interconnect - assign lsu_valid = dut.i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.data_qvalid_o; - assign lsu_ready = dut.i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch.data_qready_i; - assign lsu_request[g*NumTilesPerGroup*NumCoresPerTile+t*NumCoresPerTile+c] = lsu_valid & !lsu_ready; - assign lsu_handshake[g*NumTilesPerGroup*NumCoresPerTile+t*NumCoresPerTile+c] = lsu_valid & lsu_ready; - end - end - end `endif // DSPU @@ -449,30 +457,34 @@ module mempool_tb; assign dspu_utilization = $countones(dspu_handshake); assign mac_utilization = $countones(dspu_mac); `ifdef TERAPOOL - for (genvar g = 0; g < NumGroups; g++) begin - for (genvar sg = 0; sg < NumSubGroupsPerGroup; sg++) begin - for (genvar t = 0; t < NumTilesPerSubGroup; t++) begin - for (genvar c = 0; c < NumCoresPerTile; c++) begin - logic dsp_valid, dsp_ready, mac; - assign dsp_valid = dut.i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.in_valid_i; - assign dsp_ready = dut.i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.in_ready_o; - assign mac = dut.i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.operator_i ==? riscv_instr::P_MAC; - assign dspu_handshake[g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = dsp_valid & dsp_ready; - assign dspu_mac[g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = dsp_valid & dsp_ready & mac; + for (genvar cl = 0; cl < NumClusters; cl++) begin + for (genvar g = 0; g < NumGroupsPerCluster; g++) begin + for (genvar sg = 0; sg < NumSubGroupsPerGroup; sg++) begin + for (genvar t = 0; t < NumTilesPerSubGroup; t++) begin + for (genvar c = 0; c < NumCoresPerTile; c++) begin + logic dsp_valid, dsp_ready, mac; + assign dsp_valid = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.in_valid_i; + assign dsp_ready = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.in_ready_o; + assign mac = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].gen_rtl_group.i_group.gen_sub_groups[sg].gen_rtl_sg.i_sub_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.operator_i ==? riscv_instr::P_MAC; + assign dspu_handshake[cl*NumCoresPerCluster+g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = dsp_valid & dsp_ready; + assign dspu_mac[cl*NumCoresPerCluster+g*NumSubGroupsPerGroup*NumTilesPerSubGroup*NumCoresPerTile + sg*NumTilesPerSubGroup*NumCoresPerTile + t*NumCoresPerTile + c] = dsp_valid & dsp_ready & mac; + end end end end end `else - for (genvar g = 0; g < NumGroups; g++) begin - for (genvar t = 0; t < NumTilesPerGroup; t++) begin - for (genvar c = 0; c < NumCoresPerTile; c++) begin - logic dsp_valid, dsp_ready, mac; - assign dsp_valid = dut.i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.in_valid_i; - assign dsp_ready = dut.i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.in_ready_o; - assign mac = dut.i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.operator_i ==? riscv_instr::P_MAC; - assign dspu_handshake[g*NumTilesPerGroup*NumCoresPerTile+t*NumCoresPerTile+c] = dsp_valid & dsp_ready; - assign dspu_mac[g*NumTilesPerGroup*NumCoresPerTile+t*NumCoresPerTile+c] = dsp_valid & dsp_ready & mac; + for (genvar cl = 0; cl < NumClusters; cl++) begin + for (genvar g = 0; g < NumGroupsPerCluster; g++) begin + for (genvar t = 0; t < NumTilesPerGroup; t++) begin + for (genvar c = 0; c < NumCoresPerTile; c++) begin + logic dsp_valid, dsp_ready, mac; + assign dsp_valid = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.in_valid_i; + assign dsp_ready = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.in_ready_o; + assign mac = dut.gen_clusters[cl].i_mempool_cluster.gen_groups[g].i_group.gen_tiles[t].i_tile.gen_cores[c].gen_mempool_cc.riscv_core.i_snitch_ipu.gen_xpulpimg.i_dspu.operator_i ==? riscv_instr::P_MAC; + assign dspu_handshake[cl*NumCoresPerCluster+g*NumCoresPerGroup+t*NumCoresPerTile+c] = dsp_valid & dsp_ready; + assign dspu_mac[cl*NumCoresPerCluster+g*NumCoresPerGroup+t*NumCoresPerTile+c] = dsp_valid & dsp_ready & mac; + end end end end @@ -484,11 +496,13 @@ module mempool_tb; int unsigned axi_w_utilization, axi_r_utilization; assign axi_w_utilization = $countones(w_valid & w_ready); assign axi_r_utilization = $countones(r_ready & r_valid); - for (genvar a = 0; a < NumGroups*NumAXIMastersPerGroup; a++) begin - assign w_valid[a] = dut.i_mempool_cluster.axi_mst_req_o[a].w_valid; - assign w_ready[a] = dut.i_mempool_cluster.axi_mst_resp_i[a].w_ready; - assign r_ready[a] = dut.i_mempool_cluster.axi_mst_req_o[a].r_ready; - assign r_valid[a] = dut.i_mempool_cluster.axi_mst_resp_i[a].r_valid; + for (genvar cl = 0; cl < NumClusters; cl++) begin + for (genvar a = 0; a < NumGroupsPerCluster*NumAXIMastersPerGroup; a++) begin + assign w_valid[cl*NumGroupsPerCluster*NumAXIMastersPerGroup+a] = dut.gen_clusters[cl].i_mempool_cluster.axi_mst_req_o[a].w_valid; + assign w_ready[cl*NumGroupsPerCluster*NumAXIMastersPerGroup+a] = dut.gen_clusters[cl].i_mempool_cluster.axi_mst_resp_i[a].w_ready; + assign r_ready[cl*NumGroupsPerCluster*NumAXIMastersPerGroup+a] = dut.gen_clusters[cl].i_mempool_cluster.axi_mst_req_o[a].r_ready; + assign r_valid[cl*NumGroupsPerCluster*NumAXIMastersPerGroup+a] = dut.gen_clusters[cl].i_mempool_cluster.axi_mst_resp_i[a].r_valid; + end end `endif From af8c3398be0f07db2fc635e000918c8d778b692b Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 8 Apr 2024 15:23:05 +0200 Subject: [PATCH 08/14] [hardware] Update wave scripts --- hardware/scripts/questa/wave.tcl | 144 ++--- hardware/scripts/questa/wave_cache.tcl | 82 +-- hardware/scripts/questa/wave_cluster.tcl | 25 +- hardware/scripts/questa/wave_core.tcl | 636 +++++++++++------------ hardware/scripts/questa/wave_tile.tcl | 166 +++--- 5 files changed, 527 insertions(+), 526 deletions(-) diff --git a/hardware/scripts/questa/wave.tcl b/hardware/scripts/questa/wave.tcl index fc3bfaf4d..5b10c1483 100644 --- a/hardware/scripts/questa/wave.tcl +++ b/hardware/scripts/questa/wave.tcl @@ -31,98 +31,100 @@ add wave /mempool_tb/wfi # Add all cores from group 0 tile 0 for {set core 0} {$core < [examine -radix dec mempool_pkg::NumCoresPerTile]} {incr core} { if {$config == {terapool}} { - do ../scripts/questa/wave_core.tcl 0 0 0 $core + do ../scripts/questa/wave_core.tcl 0 0 0 0 $core } else { - do ../scripts/questa/wave_core.tcl 0 0 $core + do ../scripts/questa/wave_core.tcl 0 0 0 $core } } # Add specific cores from different tiles if {$config == {terapool}} { - do ../scripts/questa/wave_core.tcl 1 0 0 0 + do ../scripts/questa/wave_core.tcl 0 1 0 0 0 } else { - do ../scripts/questa/wave_core.tcl 1 0 0 + do ../scripts/questa/wave_core.tcl 0 1 0 0 } # Add groups -for {set group 0} {$group < [examine -radix dec /mempool_pkg::NumGroups]} {incr group} { - # Add tiles - if {$config == {terapool}} { - for {set subgroup 0} {$subgroup < [expr min(4,[examine -radix dec /mempool_pkg::NumSubGroupsPerGroup])]} {incr subgroup} { - for {set tile 0} {$tile < [expr min(4,[examine -radix dec /mempool_pkg::NumTilesPerSubGroup])]} {incr tile} { - do ../scripts/questa/wave_tile.tcl $group $subgroup $tile +for {set cluster 0} {$cluster < [examine -radix dec /mempool_pkg::NumClusters]} {incr cluster} { + # Add cluster + do ../scripts/questa/wave_cluster.tcl $cluster + add wave -Group cluster_[$cluster] -Group dma /mempool_tb/dut/gen_mempool_dma[$cluster]/i_mempool_dma/* + add wave -Group cluster_[$cluster] -Group dma -Group reg /mempool_tb/dut/gen_mempool_dma[$cluster]/i_mempool_dma/i_mempool_dma_frontend_reg_top/* + # Add groups + for {set group 0} {$group < [examine -radix dec /mempool_pkg::NumGroupsPerCluster]} {incr group} { + # Add tiles + if {$config == {terapool}} { + for {set subgroup 0} {$subgroup < [expr min(4,[examine -radix dec /mempool_pkg::NumSubGroupsPerGroup])]} {incr subgroup} { + for {set tile 0} {$tile < [expr min(4,[examine -radix dec /mempool_pkg::NumTilesPerSubGroup])]} {incr tile} { + do ../scripts/questa/wave_tile.tcl $cluster $group $subgroup $tile + } + } + } else { + for {set tile 0} {$tile < [expr min(4,[examine -radix dec /mempool_pkg::NumTilesPerGroup])]} {incr tile} { + do ../scripts/questa/wave_tile.tcl $cluster $group $tile } } - } else { - for {set tile 0} {$tile < [expr min(4,[examine -radix dec /mempool_pkg::NumTilesPerGroup])]} {incr tile} { - do ../scripts/questa/wave_tile.tcl $group $tile - } - } - # Interconnects - for {set tgtgroup 0} {$tgtgroup < [examine -radix dec /mempool_pkg::NumGroups]} {incr tgtgroup} { - if {$tgtgroup != $group} { - set interco_idx [expr $group ^ $tgtgroup] - if {$config == {terapool}} { - add wave -group group_[$group] -group interconnect_to_group[$tgtgroup] /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/gen_remote_interco[$interco_idx]/i_remote_interco/* - } else { - add wave -group group_[$group] -group interconnect_to_group[$tgtgroup] /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/gen_remote_interco[$interco_idx]/i_remote_interco/* + # Interconnects + for {set tgtgroup 0} {$tgtgroup < [examine -radix dec /mempool_pkg::NumGroupsPerCluster]} {incr tgtgroup} { + if {$tgtgroup != $group} { + set interco_idx [expr $group ^ $tgtgroup] + if {$config == {terapool}} { + add wave -group cluster_[$cluster] -group group_[$group] -group interconnect_to_group[$tgtgroup] /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/gen_remote_interco[$interco_idx]/i_remote_interco/* + } else { + add wave -group cluster_[$cluster] -group group_[$group] -group interconnect_to_group[$tgtgroup] /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/gen_remote_interco[$interco_idx]/i_remote_interco/* + } } } - } - if {$config != {terapool}} { - add wave -group group_[$group] -group interconnect_local /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/i_local_interco/* - } -} - -# Add cluster -do ../scripts/questa/wave_cluster.tcl - -add wave -Group Control_Registers /mempool_tb/dut/i_ctrl_registers/* - -add wave -Group DMA /mempool_tb/dut/i_mempool_dma/* -add wave -Group DMA -Group Reg /mempool_tb/dut/i_mempool_dma/i_mempool_dma_frontend_reg_top/* -for {set group 0} {$group < [examine -radix dec /mempool_pkg::NumGroups]} {incr group} { - if {$config == {terapool}} { - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/NoMstPorts - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/DmaRegionWidth - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/DmaRegionStart - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/DmaRegionEnd - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/DmaRegionAddressBits - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/FullRegionAddressBits - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/* - for {set subgroup 0} {$subgroup < [examine -radix dec /mempool_pkg::NumSubGroupsPerGroup]} {incr subgroup} { - for {set dma 0} {$dma < [examine -radix dec /mempool_pkg::NumDmasPerSubGroup]} {incr dma} { - add wave -Group DMA_${group}_${subgroup}_${dma} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/gen_sub_groups[$subgroup]/gen_rtl_sg/i_sub_group/gen_dmas[$dma]/i_axi_dma_backend/* + if {$config != {terapool}} { + add wave -group cluster_[$cluster] -group group_[$group] -group interconnect_local /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_local_interco/* } } - } else { - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/NoMstPorts - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/DmaRegionWidth - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/DmaRegionStart - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/DmaRegionEnd - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/DmaRegionAddressBits - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/FullRegionAddressBits - add wave -Group DMA_midend_${group} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/* - for {set dma 0} {$dma < [examine -radix dec /mempool_pkg::NumDmasPerGroup]} {incr dma} { - add wave -Group DMA_${group}_${dma} /mempool_tb/dut/i_mempool_cluster/gen_groups[$group]/i_group/gen_dmas[$dma]/i_axi_dma_backend/* - } - } } -add wave -Group DMA_midend_cluster /mempool_tb/dut/i_mempool_cluster/i_idma_distributed_midend/NoMstPorts -add wave -Group DMA_midend_cluster /mempool_tb/dut/i_mempool_cluster/i_idma_distributed_midend/DmaRegionWidth -add wave -Group DMA_midend_cluster /mempool_tb/dut/i_mempool_cluster/i_idma_distributed_midend/DmaRegionStart -add wave -Group DMA_midend_cluster /mempool_tb/dut/i_mempool_cluster/i_idma_distributed_midend/DmaRegionEnd -add wave -Group DMA_midend_cluster /mempool_tb/dut/i_mempool_cluster/i_idma_distributed_midend/DmaRegionAddressBits -add wave -Group DMA_midend_cluster /mempool_tb/dut/i_mempool_cluster/i_idma_distributed_midend/FullRegionAddressBits -add wave -Group DMA_midend_cluster /mempool_tb/dut/i_mempool_cluster/i_idma_distributed_midend/* - +add wave -Group Control_Registers /mempool_tb/dut/i_ctrl_registers/* -add wave -Group DMA_split /mempool_tb/dut/i_mempool_cluster/i_idma_split_midend/* +# for {set group 0} {$group < [examine -radix dec /mempool_pkg::NumGroups]} {incr group} { +# if {$config == {terapool}} { +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/NoMstPorts +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/DmaRegionWidth +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/DmaRegionStart +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/DmaRegionEnd +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/DmaRegionAddressBits +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/FullRegionAddressBits +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/* +# for {set subgroup 0} {$subgroup < [examine -radix dec /mempool_pkg::NumSubGroupsPerGroup]} {incr subgroup} { +# for {set dma 0} {$dma < [examine -radix dec /mempool_pkg::NumDmasPerSubGroup]} {incr dma} { +# add wave -Group DMA_${group}_${subgroup}_${dma} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/gen_sub_groups[$subgroup]/gen_rtl_sg/i_sub_group/gen_dmas[$dma]/i_axi_dma_backend/* +# } +# } +# } else { +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/NoMstPorts +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/DmaRegionWidth +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/DmaRegionStart +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/DmaRegionEnd +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/DmaRegionAddressBits +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/FullRegionAddressBits +# add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_idma_distributed_midend/* +# for {set dma 0} {$dma < [examine -radix dec /mempool_pkg::NumDmasPerGroup]} {incr dma} { +# add wave -Group DMA_${group}_${dma} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/gen_dmas[$dma]/i_axi_dma_backend/* +# } +# } +# } + +# add wave -Group DMA_midend_cluster /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/i_idma_distributed_midend/NoMstPorts +# add wave -Group DMA_midend_cluster /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/i_idma_distributed_midend/DmaRegionWidth +# add wave -Group DMA_midend_cluster /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/i_idma_distributed_midend/DmaRegionStart +# add wave -Group DMA_midend_cluster /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/i_idma_distributed_midend/DmaRegionEnd +# add wave -Group DMA_midend_cluster /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/i_idma_distributed_midend/DmaRegionAddressBits +# add wave -Group DMA_midend_cluster /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/i_idma_distributed_midend/FullRegionAddressBits +# add wave -Group DMA_midend_cluster /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/i_idma_distributed_midend/* + + +# add wave -Group DMA_split /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/i_idma_split_midend/* if {$config == {terapool}} { - do ../scripts/questa/wave_cache.tcl 0 0 0 0 + do ../scripts/questa/wave_cache.tcl 0 0 0 0 0 } else { - do ../scripts/questa/wave_cache.tcl 0 0 0 + do ../scripts/questa/wave_cache.tcl 0 0 0 0 } diff --git a/hardware/scripts/questa/wave_cache.tcl b/hardware/scripts/questa/wave_cache.tcl index 7333307d9..706034661 100644 --- a/hardware/scripts/questa/wave_cache.tcl +++ b/hardware/scripts/questa/wave_cache.tcl @@ -2,54 +2,54 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Create cache for core $3 from group $1 tile $2 (core_id=NUM_CORES_PER_group*$1+NUM_CORES_PER_TILE*$2+$3) +# Create cache for core $4 from cluster $1 group $2 tile $3 if {$config == {terapool}} { - add wave -noupdate -group cache[$1][$2][$3][$4] -divider Parameters - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/NR_FETCH_PORTS - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/L0_LINE_COUNT - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/LINE_WIDTH - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/LINE_COUNT - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/SET_COUNT - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/FETCH_DW - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/FILL_AW - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/FILL_DW - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/EARLY_LATCH - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/L0_EARLY_TAG_WIDTH - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/ISO_CROSSING - add wave -noupdate -group cache[$1][$2][$3][$4] -divider Signals - add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/* + add wave -noupdate -group cache[$1][$2][$3][$4][$5] -divider Parameters + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/NR_FETCH_PORTS + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/L0_LINE_COUNT + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/LINE_WIDTH + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/LINE_COUNT + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/SET_COUNT + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/FETCH_DW + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/FILL_AW + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/FILL_DW + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/EARLY_LATCH + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/L0_EARLY_TAG_WIDTH + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/ISO_CROSSING + add wave -noupdate -group cache[$1][$2][$3][$4][$5] -divider Signals + add wave -noupdate -group cache[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/* - for {set i 0} {$i < [examine -radix dec /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/NR_FETCH_PORTS]} {incr i} { - add wave -noupdate -group cache[$1][$2][$3][$4] -group refill[$i] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/gen_prefetcher[$i]/i_snitch_icache_l0/* + for {set i 0} {$i < [examine -radix dec /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/NR_FETCH_PORTS]} {incr i} { + add wave -noupdate -group cache[$1][$2][$3][$4][$5] -group refill[$i] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/gen_prefetcher[$i]/i_snitch_icache_l0/* } - add wave -noupdate -group cache[$1][$2][$3][$4] -group lookup /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/gen_serial_lookup/i_lookup/* - add wave -noupdate -group cache[$1][$2][$3][$4] -group handler /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/i_handler/* - add wave -noupdate -group cache[$1][$2][$3][$4] -group handler /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/i_handler/pending_q - add wave -noupdate -group cache[$1][$2][$3][$4] -group refill /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/i_refill/* + add wave -noupdate -group cache[$1][$2][$3][$4][$5] -group lookup /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/gen_serial_lookup/i_lookup/* + add wave -noupdate -group cache[$1][$2][$3][$4][$5] -group handler /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/i_handler/* + add wave -noupdate -group cache[$1][$2][$3][$4][$5] -group handler /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/i_handler/pending_q + add wave -noupdate -group cache[$1][$2][$3][$4][$5] -group refill /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[$5]/i_snitch_icache/i_refill/* } else { - add wave -noupdate -group cache[$1][$2][$3] -divider Parameters - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/NR_FETCH_PORTS - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/L0_LINE_COUNT - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/LINE_WIDTH - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/LINE_COUNT - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/SET_COUNT - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/FETCH_DW - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/FILL_AW - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/FILL_DW - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/EARLY_LATCH - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/L0_EARLY_TAG_WIDTH - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/ISO_CROSSING - add wave -noupdate -group cache[$1][$2][$3] -divider Signals - add wave -noupdate -group cache[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/* + add wave -noupdate -group cache[$1][$2][$3][$4] -divider Parameters + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/NR_FETCH_PORTS + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/L0_LINE_COUNT + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/LINE_WIDTH + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/LINE_COUNT + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/SET_COUNT + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/FETCH_DW + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/FILL_AW + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/FILL_DW + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/EARLY_LATCH + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/L0_EARLY_TAG_WIDTH + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/ISO_CROSSING + add wave -noupdate -group cache[$1][$2][$3][$4] -divider Signals + add wave -noupdate -group cache[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/* - for {set i 0} {$i < [examine -radix dec /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/NR_FETCH_PORTS]} {incr i} { - add wave -noupdate -group cache[$1][$2][$3] -group refill[$i] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/gen_prefetcher[$i]/i_snitch_icache_l0/* + for {set i 0} {$i < [examine -radix dec /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/NR_FETCH_PORTS]} {incr i} { + add wave -noupdate -group cache[$1][$2][$3][$4] -group refill[$i] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/gen_prefetcher[$i]/i_snitch_icache_l0/* } - add wave -noupdate -group cache[$1][$2][$3] -group lookup /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/gen_serial_lookup/i_lookup/* - add wave -noupdate -group cache[$1][$2][$3] -group handler /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/i_handler/* - add wave -noupdate -group cache[$1][$2][$3] -group handler /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/i_handler/pending_q - add wave -noupdate -group cache[$1][$2][$3] -group refill /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[$3]/i_snitch_icache/i_refill/* + add wave -noupdate -group cache[$1][$2][$3][$4] -group lookup /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/gen_serial_lookup/i_lookup/* + add wave -noupdate -group cache[$1][$2][$3][$4] -group handler /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/i_handler/* + add wave -noupdate -group cache[$1][$2][$3][$4] -group handler /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/i_handler/pending_q + add wave -noupdate -group cache[$1][$2][$3][$4] -group refill /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[$4]/i_snitch_icache/i_refill/* } diff --git a/hardware/scripts/questa/wave_cluster.tcl b/hardware/scripts/questa/wave_cluster.tcl index e0b6b5044..2dcebec04 100644 --- a/hardware/scripts/questa/wave_cluster.tcl +++ b/hardware/scripts/questa/wave_cluster.tcl @@ -2,17 +2,16 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -# Create cache for core $3 from group $1 tile $2 (core_id=NUM_CORES_PER_group*$1+NUM_CORES_PER_TILE*$2+$3) +# Create cluster $1 -add wave -noupdate -group cluster -divider Parameters -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/TCDMBaseAddr -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/BootAddr -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/NumDMAReq -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/NumAXIMasters -add wave -noupdate -group cluster -divider Signals -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/clk_i -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/rst_ni -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/axi_mst_req_o -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/axi_mst_resp_i -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/ro_cache_ctrl_i -add wave -noupdate -group cluster mempool_tb/dut/i_mempool_cluster/dma_* +add wave -noupdate -group cluster_[$1] -divider Parameters +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/TCDMBaseAddr +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/BootAddr +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/NumDMAReq +add wave -noupdate -group cluster_[$1] -divider Signals +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/clk_i +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/rst_ni +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/axi_mst_req_o +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/axi_mst_resp_i +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/ro_cache_ctrl_i +add wave -noupdate -group cluster_[$1] mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/dma_* diff --git a/hardware/scripts/questa/wave_core.tcl b/hardware/scripts/questa/wave_core.tcl index 85340078d..8776f74f0 100644 --- a/hardware/scripts/questa/wave_core.tcl +++ b/hardware/scripts/questa/wave_core.tcl @@ -4,339 +4,339 @@ # Create group for core $3 from group $1 tile $2 (core_id=NUM_CORES_PER_group*$1+NUM_CORES_PER_TILE*$2+$3) if {$config == {terapool}} { - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/BootAddr - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/MTVEC - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RVE - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RVM - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterOffloadReq - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterOffloadResp - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterTCDMReq - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterTCDMResp - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/clk_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rst_i - add wave -noupdate -group core[$1][$2][$3][$4] -radix unsigned /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/hart_id_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/BootAddr + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/MTVEC + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RVE + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RVM + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RegisterOffloadReq + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RegisterOffloadResp + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RegisterTCDMReq + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RegisterTCDMResp + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/clk_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rst_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -radix unsigned /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/hart_id_i - add wave -noupdate -group core[$1][$2][$3][$4] -divider Instructions - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_addr_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_data_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_valid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_ready_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider Instructions + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/inst_addr_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/inst_data_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/inst_valid_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/inst_ready_i - add wave -noupdate -group core[$1][$2][$3][$4] -divider Load/Store - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qaddr_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qwrite_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qamo_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qdata_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qstrb_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qvalid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qready_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pdata_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_perror_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pvalid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pready_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider Load/Store + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qaddr_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qwrite_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qamo_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qdata_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qstrb_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qvalid_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qready_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_pdata_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_perror_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_pvalid_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_pready_o - add wave -noupdate -group core[$1][$2][$3][$4] -divider Accelerator - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qaddr_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_op_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_arga_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argb_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argc_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qvalid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qready_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pdata_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_perror_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pvalid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pready_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider Accelerator + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qaddr_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qid_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_op_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_arga_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argb_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argc_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qvalid_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qready_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_pdata_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_pid_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_perror_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_pvalid_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_pready_o - add wave -noupdate -group core[$1][$2][$3][$4] -divider FPSS - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_valid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_ready_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_valid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_ready_i - add wave -noupdate -group core[$1][$2][$3][$4] -divider FPU - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/operands_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/rnd_mode_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_mod_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/src_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/dst_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/int_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/vectorial_op_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_valid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_ready_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/result_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/status_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_valid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_ready_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider FPSS + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_valid_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_ready_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_valid_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_ready_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider FPU + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/operands_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/rnd_mode_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_mod_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/src_fmt_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/dst_fmt_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/int_fmt_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/vectorial_op_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_valid_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_ready_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/result_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/status_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_valid_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_ready_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/illegal_inst - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/stall - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_stall - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_stall - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/fence_stall - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/zero_lsb - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/pc_d - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/pc_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wfi_d - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wfi_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_sync_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_d - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_q + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/illegal_inst + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/stall + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_stall + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_stall + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/fence_stall + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/zero_lsb + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/pc_d + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/pc_q + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wfi_d + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wfi_q + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wake_up_sync_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wake_up_d + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wake_up_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider LSU - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_size - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_amo - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ld_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_qready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_qvalid - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_pvalid - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_pready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_empty - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_load - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_acc + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal -divider LSU + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ls_size + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ls_amo + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ld_result + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_qready + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_qvalid + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_pvalid + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_pready + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_rd + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_empty + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/retire_load + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/retire_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/retire_acc - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider Register - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/raddr_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/waddr_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/wdata_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/we_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/rdata_o - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/mem + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal -divider Register + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/raddr_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/waddr_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/wdata_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/we_i + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/rdata_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/mem - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider ALU - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/iimm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/uimm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/jimm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/bimm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/simm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/adder_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rs1 - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rs2 - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_raddr - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_rdata - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_waddr - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_wdata - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_we - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/consec_pc - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/sb_d - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/sb_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_load - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_store - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_signed - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_fp_load - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_fp_store - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_misaligned - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ld_addr_misaligned - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/st_addr_misaligned - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/valid_instr - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/exception - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_op - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa_select - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb_select - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/write_rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/uses_rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/next_pc - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd_select - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd_bypass - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_branch - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_rvalue - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_en - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/cycle_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/instret_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_register_rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/operands_ready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/dst_ready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa_ready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb_ready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_reversed - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_left_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_ext - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result_ext - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_left - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_arithmetic - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_opa - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_opb - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_writeback - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_en - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/core_events_o + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal -divider ALU + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opa + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opb + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/iimm + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/uimm + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/jimm + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/bimm + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/simm + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/adder_result + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_result + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rd + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rs1 + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rs2 + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_raddr + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_rdata + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_waddr + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_wdata + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_we + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/consec_pc + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/sb_d + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/sb_q + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_load + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_store + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_signed + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_fp_load + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_fp_store + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ls_misaligned + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ld_addr_misaligned + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/st_addr_misaligned + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/valid_instr + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/exception + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_op + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opa_select + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opb_select + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/write_rd + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/uses_rd + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/next_pc + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rd_select + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rd_bypass + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_branch + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/csr_rvalue + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/csr_en + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/cycle_q + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/instret_q + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_register_rd + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/operands_ready + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/dst_ready + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opa_ready + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opb_ready + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_opa + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_reversed + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_left_result + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_ext + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result_ext + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_left + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_arithmetic + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_opa + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_opb + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_writeback + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_q + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_en + add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/core_events_o } else { - add wave -noupdate -group core[$1][$2][$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/BootAddr - add wave -noupdate -group core[$1][$2][$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/MTVEC - add wave -noupdate -group core[$1][$2][$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/RVE - add wave -noupdate -group core[$1][$2][$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/RVM - add wave -noupdate -group core[$1][$2][$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/RegisterOffloadReq - add wave -noupdate -group core[$1][$2][$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/RegisterOffloadResp - add wave -noupdate -group core[$1][$2][$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/RegisterTCDMReq - add wave -noupdate -group core[$1][$2][$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/RegisterTCDMResp - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/clk_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/rst_i - add wave -noupdate -group core[$1][$2][$3] -radix unsigned /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/hart_id_i + add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/BootAddr + add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/MTVEC + add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RVE + add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RVM + add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterOffloadReq + add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterOffloadResp + add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterTCDMReq + add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterTCDMResp + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/clk_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rst_i + add wave -noupdate -group core[$1][$2][$3][$4] -radix unsigned /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/hart_id_i - add wave -noupdate -group core[$1][$2][$3] -divider Instructions - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/inst_addr_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/inst_data_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/inst_valid_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/inst_ready_i + add wave -noupdate -group core[$1][$2][$3][$4] -divider Instructions + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_addr_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_data_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_valid_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_ready_i - add wave -noupdate -group core[$1][$2][$3] -divider Load/Store - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_qaddr_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_qwrite_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_qamo_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_qdata_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_qstrb_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_qvalid_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_qready_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_pdata_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_perror_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_pvalid_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/data_pready_o + add wave -noupdate -group core[$1][$2][$3][$4] -divider Load/Store + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qaddr_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qwrite_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qamo_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qdata_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qstrb_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qvalid_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qready_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pdata_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_perror_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pvalid_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pready_o - add wave -noupdate -group core[$1][$2][$3] -divider Accelerator - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_qaddr_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_qid_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_op_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_arga_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argb_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argc_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_qvalid_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_qready_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_pdata_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_pid_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_perror_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_pvalid_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_pready_o + add wave -noupdate -group core[$1][$2][$3][$4] -divider Accelerator + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qaddr_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qid_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_op_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_arga_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argb_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argc_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qvalid_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qready_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pdata_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pid_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_perror_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pvalid_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pready_o - add wave -noupdate -group core[$1][$2][$3] -divider FPSS - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_valid_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_ready_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_valid_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_ready_i - add wave -noupdate -group core[$1][$2][$3] -divider FPU - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/operands_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/rnd_mode_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_mod_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/src_fmt_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/dst_fmt_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/int_fmt_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/vectorial_op_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_valid_i - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_ready_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/result_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/status_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_valid_o - add wave -noupdate -group core[$1][$2][$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_ready_i + add wave -noupdate -group core[$1][$2][$3][$4] -divider FPSS + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_valid_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_ready_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_valid_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_ready_i + add wave -noupdate -group core[$1][$2][$3][$4] -divider FPU + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/operands_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/rnd_mode_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_mod_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/src_fmt_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/dst_fmt_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/int_fmt_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/vectorial_op_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_valid_i + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_ready_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/result_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/status_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_valid_o + add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_ready_i - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/illegal_inst - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/stall - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/lsu_stall - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_stall - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/zero_lsb - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/pc_d - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/pc_q - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/wfi_d - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/wfi_q - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/wake_up_sync_i - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/wake_up_d - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/wake_up_q + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/illegal_inst + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/stall + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_stall + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_stall + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/zero_lsb + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/pc_d + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/pc_q + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wfi_d + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wfi_q + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_sync_i + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_d + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_q - add wave -noupdate -group core[$1][$2][$3] -group Internal -divider LSU - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/ls_size - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/ls_amo - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/ld_result - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/lsu_qready - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/lsu_qvalid - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/lsu_pvalid - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/lsu_pready - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/lsu_rd - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/retire_load - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/retire_i - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/retire_acc + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider LSU + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_size + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_amo + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ld_result + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_qready + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_qvalid + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_pvalid + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_pready + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_rd + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_load + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_i + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_acc - add wave -noupdate -group core[$1][$2][$3] -group Internal -divider Register - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/raddr_i - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/waddr_i - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/wdata_i - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/we_i - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/rdata_o - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/mem + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider Register + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/raddr_i + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/waddr_i + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/wdata_i + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/we_i + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/rdata_o + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/mem - add wave -noupdate -group core[$1][$2][$3] -group Internal -divider ALU - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/opa - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/opb - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/iimm - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/uimm - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/jimm - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/bimm - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/simm - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/adder_result - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/alu_result - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/rd - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/rs1 - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/rs2 - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/gpr_raddr - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/gpr_rdata - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/gpr_waddr - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/gpr_wdata - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/gpr_we - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/consec_pc - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/sb_d - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/sb_q - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/is_load - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/is_store - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/is_signed - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/is_fp_load - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/is_fp_store - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/ls_misaligned - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/ld_addr_misaligned - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/st_addr_misaligned - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/valid_instr - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/exception - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/alu_op - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/opa_select - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/opb_select - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/write_rd - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/uses_rd - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/next_pc - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/rd_select - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/rd_bypass - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/is_branch - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/csr_rvalue - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/csr_en - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/cycle_q - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/instret_q - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/acc_register_rd - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/operands_ready - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/dst_ready - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/opa_ready - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/opb_ready - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/shift_opa - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_reversed - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/shift_left_result - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_ext - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result_ext - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/shift_left - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/shift_arithmetic - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/alu_opa - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/alu_opb - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/alu_writeback - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_q - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_en - add wave -noupdate -group core[$1][$2][$3] -group Internal /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_cores[$3]/gen_mempool_cc/riscv_core/i_snitch/core_events_o + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider ALU + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/iimm + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/uimm + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/jimm + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/bimm + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/simm + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/adder_result + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_result + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rs1 + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rs2 + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_raddr + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_rdata + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_waddr + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_wdata + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_we + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/consec_pc + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/sb_d + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/sb_q + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_load + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_store + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_signed + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_fp_load + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_fp_store + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_misaligned + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ld_addr_misaligned + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/st_addr_misaligned + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/valid_instr + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/exception + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_op + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa_select + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb_select + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/write_rd + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/uses_rd + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/next_pc + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd_select + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd_bypass + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_branch + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_rvalue + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_en + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/cycle_q + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/instret_q + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_register_rd + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/operands_ready + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/dst_ready + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa_ready + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb_ready + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_reversed + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_left_result + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_ext + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result_ext + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_left + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_arithmetic + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_opa + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_opb + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_writeback + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_q + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_en + add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/core_events_o } diff --git a/hardware/scripts/questa/wave_tile.tcl b/hardware/scripts/questa/wave_tile.tcl index 9740b30ac..6dd92ec0f 100644 --- a/hardware/scripts/questa/wave_tile.tcl +++ b/hardware/scripts/questa/wave_tile.tcl @@ -4,95 +4,95 @@ # Create group for group $1 tile $2 if {$config == {terapool}} { - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_pkg::NumBanksPerTile - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_pkg::NumTiles - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_pkg::NumBanks - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/TCDMBaseAddr - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/BootAddr - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[0].i_snitch_icache.LINE_WIDTH - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[0].i_snitch_icache.LINE_COUNT - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_caches[0].i_snitch_icache.SET_COUNT - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_pkg::ICacheLineWidth - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_pkg::ICacheSizeByte - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_pkg::ICacheSets - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group Params /mempool_pkg::NumCores - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/clk_i - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/rst_ni - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/scan_enable_i - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/scan_data_i - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/scan_data_o - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -radix unsigned /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/tile_id_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_pkg::NumBanksPerTile + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_pkg::NumTiles + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_pkg::NumBanks + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/TCDMBaseAddr + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/BootAddr + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[0].i_snitch_icache.LINE_WIDTH + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[0].i_snitch_icache.LINE_COUNT + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_caches[0].i_snitch_icache.SET_COUNT + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_pkg::ICacheLineWidth + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_pkg::ICacheSizeByte + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_pkg::ICacheSets + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group Params /mempool_pkg::NumCores + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/clk_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/rst_ni + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/scan_enable_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/scan_data_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/scan_data_o + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -radix unsigned /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/tile_id_i - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -divider TCDM - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/tcdm_master_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/tcdm_slave_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/axi_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/snitch_inst_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/snitch_data_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/bank_req_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/bank_resp_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/postreg_tcdm_slave_req_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/prereg_tcdm_slave_resp_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/prereg_tcdm_master_req_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/postreg_tcdm_master_resp_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/remote_req_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/remote_resp_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/local_req_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/local_resp_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/soc_data_* - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/mask_map - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/soc_req_o - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/soc_resp_i - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/soc_qvalid - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/soc_qready - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/soc_pvalid - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/soc_pready + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -divider TCDM + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/tcdm_master_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/tcdm_slave_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/axi_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/snitch_inst_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/snitch_data_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/bank_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/bank_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/postreg_tcdm_slave_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/prereg_tcdm_slave_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/prereg_tcdm_master_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/postreg_tcdm_master_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/remote_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/remote_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/local_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/local_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/soc_data_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/mask_map + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/soc_req_o + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/soc_resp_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/soc_qvalid + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/soc_qready + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/soc_pvalid + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/soc_pready for {set i 0} {$i < 16} {incr i} { - add wave -noupdate -group group_[$1] -group sub_group_[$2] -group Tile_[$3] -group tcdm_adapter[$i] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/gen_rtl_group/i_group/gen_sub_groups[$2]/gen_rtl_sg/i_sub_group/gen_tiles[$3]/i_tile/gen_banks[$i]/i_tcdm_adapter/* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group tcdm_adapter[$i] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_banks[$i]/i_tcdm_adapter/* } } else { - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_pkg::NumBanksPerTile - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_pkg::NumTiles - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_pkg::NumBanks - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/TCDMBaseAddr - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/BootAddr - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[0].i_snitch_icache.LINE_WIDTH - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[0].i_snitch_icache.LINE_COUNT - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_caches[0].i_snitch_icache.SET_COUNT - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_pkg::ICacheLineWidth - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_pkg::ICacheSizeByte - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_pkg::ICacheSets - add wave -noupdate -group group_[$1] -group Tile_[$2] -group Params /mempool_pkg::NumCores - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/clk_i - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/rst_ni - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/scan_enable_i - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/scan_data_i - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/scan_data_o - add wave -noupdate -group group_[$1] -group Tile_[$2] -radix unsigned /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/tile_id_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_pkg::NumBanksPerTile + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_pkg::NumTiles + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_pkg::NumBanks + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/TCDMBaseAddr + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/BootAddr + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[0].i_snitch_icache.LINE_WIDTH + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[0].i_snitch_icache.LINE_COUNT + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_caches[0].i_snitch_icache.SET_COUNT + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_pkg::ICacheLineWidth + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_pkg::ICacheSizeByte + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_pkg::ICacheSets + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group Params /mempool_pkg::NumCores + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/clk_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/rst_ni + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/scan_enable_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/scan_data_i + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/scan_data_o + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -radix unsigned /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/tile_id_i - add wave -noupdate -group group_[$1] -group Tile_[$2] -divider TCDM - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/tcdm_master_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/tcdm_slave_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/axi_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/snitch_inst_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/snitch_data_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/bank_req_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/bank_resp_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/postreg_tcdm_slave_req_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/prereg_tcdm_slave_resp_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/prereg_tcdm_master_req_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/postreg_tcdm_master_resp_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/remote_req_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/remote_resp_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/local_req_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/local_resp_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/soc_data_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/mask_map - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/snitch_to_soc_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/mux_to_soc_* - add wave -noupdate -group group_[$1] -group Tile_[$2] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/mux_to_soc_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -divider TCDM + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/tcdm_master_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/tcdm_slave_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/axi_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/snitch_inst_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/snitch_data_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/bank_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/bank_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/postreg_tcdm_slave_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/prereg_tcdm_slave_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/prereg_tcdm_master_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/postreg_tcdm_master_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/remote_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/remote_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/local_req_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/local_resp_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/soc_data_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/mask_map + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/snitch_to_soc_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/mux_to_soc_* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/mux_to_soc_* for {set i 0} {$i < 16} {incr i} { - add wave -noupdate -group group_[$1] -group Tile_[$2] -group tcdm_adapter[$i] /mempool_tb/dut/i_mempool_cluster/gen_groups[$1]/i_group/gen_tiles[$2]/i_tile/gen_banks[$i]/i_tcdm_adapter/* + add wave -noupdate -group cluster_[$1] -group group_[$2] -group tile_[$3] -group tcdm_adapter[$i] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_banks[$i]/i_tcdm_adapter/* } } From 11f4e27e2442d8ba43f7bc7fd0817c681947e270 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 8 Apr 2024 15:24:05 +0200 Subject: [PATCH 09/14] [hardware] Enable multi-cluster MemPool --- hardware/src/address_scrambler.sv | 5 +- hardware/src/mempool_cluster.sv | 198 +++++++++++++------------- hardware/src/mempool_group.sv | 226 +++++++++++++++--------------- hardware/src/mempool_pkg.sv | 33 ++--- hardware/src/mempool_sub_group.sv | 82 +++++------ hardware/src/mempool_system.sv | 13 +- hardware/src/mempool_tile.sv | 115 +++++++-------- hardware/src/tcdm_adapter.sv | 8 +- 8 files changed, 346 insertions(+), 334 deletions(-) diff --git a/hardware/src/address_scrambler.sv b/hardware/src/address_scrambler.sv index d2c790a65..e9b113b0a 100644 --- a/hardware/src/address_scrambler.sv +++ b/hardware/src/address_scrambler.sv @@ -14,7 +14,8 @@ module address_scrambler #( parameter int unsigned NumTiles = 2, parameter int unsigned NumBanksPerTile = 2, parameter bit Bypass = 0, - parameter int unsigned SeqMemSizePerTile = 4*1024 + parameter int unsigned SeqMemSizePerTile = 4*1024, + parameter int unsigned BaseAddr = 0 ) ( input logic [AddrWidth-1:0] address_i, output logic [AddrWidth-1:0] address_o @@ -50,7 +51,7 @@ module address_scrambler #( // Default: Unscrambled address_o[SeqTotalBits-1:ConstantBitsLSB] = {tile_id, scramble}; // If not in bypass mode and address is in sequential region and more than one tile - if (address_i < (NumTiles * SeqMemSizePerTile)) begin + if (address_i < (NumTiles * SeqMemSizePerTile + BaseAddr) && address_i >= BaseAddr) begin address_o[SeqTotalBits-1:ConstantBitsLSB] = {scramble, tile_id}; end end diff --git a/hardware/src/mempool_cluster.sv b/hardware/src/mempool_cluster.sv index 8aefd9c17..4daba29db 100644 --- a/hardware/src/mempool_cluster.sv +++ b/hardware/src/mempool_cluster.sv @@ -13,30 +13,31 @@ module mempool_cluster // Boot address parameter logic [31:0] BootAddr = 32'h0000_0000, // Dependant parameters. DO NOT CHANGE! - parameter int unsigned NumDMAReq = NumGroups * NumDmasPerGroup, - parameter int unsigned NumAXIMasters = NumGroups * NumAXIMastersPerGroup + parameter int unsigned NumDMAReq = NumGroupsPerCluster * NumDmasPerGroup ) ( // Clock and reset - input logic clk_i, - input logic rst_ni, - input logic testmode_i, + input logic clk_i, + input logic rst_ni, + input logic testmode_i, // Scan chain - input logic scan_enable_i, - input logic scan_data_i, - output logic scan_data_o, + input logic scan_enable_i, + input logic scan_data_i, + output logic scan_data_o, + // Cluster ID + input logic [idx_width(NumClusters)-1:0] cluster_id_i, // Wake up signal - input logic [NumCoresPerCluster-1:0] wake_up_i, + input logic [NumCoresPerCluster-1:0] wake_up_i, // RO-Cache configuration - input ro_cache_ctrl_t ro_cache_ctrl_i, + input ro_cache_ctrl_t ro_cache_ctrl_i, // DMA request - input dma_req_t dma_req_i, - input logic dma_req_valid_i, - output logic dma_req_ready_o, + input dma_req_t dma_req_i, + input logic dma_req_valid_i, + output logic dma_req_ready_o, // DMA status - output dma_meta_t dma_meta_o, + output dma_meta_t dma_meta_o, // AXI Interface - output axi_tile_req_t [NumAXIMasters-1:0] axi_mst_req_o, - input axi_tile_resp_t [NumAXIMasters-1:0] axi_mst_resp_i + output axi_tile_req_t [NumAXIMastersPerCluster-1:0] axi_mst_req_o, + input axi_tile_resp_t [NumAXIMastersPerCluster-1:0] axi_mst_resp_i ); /********************* @@ -45,8 +46,8 @@ module mempool_cluster logic [NumCoresPerCluster-1:0] wake_up_q; `FF(wake_up_q, wake_up_i, '0, clk_i, rst_ni); - ro_cache_ctrl_t [NumGroups-1:0] ro_cache_ctrl_q; - for (genvar g = 0; unsigned'(g) < NumGroups; g++) begin: gen_ro_cache_ctrl_q + ro_cache_ctrl_t [NumGroupsPerCluster-1:0] ro_cache_ctrl_q; + for (genvar g = 0; unsigned'(g) < NumGroupsPerCluster; g++) begin: gen_ro_cache_ctrl_q `FF(ro_cache_ctrl_q[g], ro_cache_ctrl_i, ro_cache_ctrl_default, clk_i, rst_ni); end: gen_ro_cache_ctrl_q @@ -77,20 +78,20 @@ module mempool_cluster logic dma_req_split_valid; logic dma_req_split_ready; dma_meta_t dma_meta_split; - dma_req_t [NumGroups-1:0] dma_req_group, dma_req_group_q; - logic [NumGroups-1:0] dma_req_group_valid, dma_req_group_q_valid; - logic [NumGroups-1:0] dma_req_group_ready, dma_req_group_q_ready; - dma_meta_t [NumGroups-1:0] dma_meta, dma_meta_q; + dma_req_t [NumGroupsPerCluster-1:0] dma_req_group, dma_req_group_q; + logic [NumGroupsPerCluster-1:0] dma_req_group_valid, dma_req_group_q_valid; + logic [NumGroupsPerCluster-1:0] dma_req_group_ready, dma_req_group_q_ready; + dma_meta_t [NumGroupsPerCluster-1:0] dma_meta, dma_meta_q; `FF(dma_meta_q, dma_meta, '0, clk_i, rst_ni); idma_split_midend #( - .DmaRegionWidth (NumBanksPerGroup*NumGroups*4), - .DmaRegionStart (TCDMBaseAddr ), - .DmaRegionEnd (TCDMBaseAddr+TCDMSize ), - .AddrWidth (AddrWidth ), - .burst_req_t (dma_req_t ), - .meta_t (dma_meta_t ) + .DmaRegionWidth (NumBanksPerGroup*NumGroupsPerCluster*4), + .DmaRegionStart (TCDMBaseAddr ), + .DmaRegionEnd (TCDMBaseAddr+L1SizePerCluster ), + .AddrWidth (AddrWidth ), + .burst_req_t (dma_req_t ), + .meta_t (dma_meta_t ) ) i_idma_split_midend ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -105,13 +106,13 @@ module mempool_cluster ); idma_distributed_midend #( - .NoMstPorts (NumGroups ), - .DmaRegionWidth (NumBanksPerGroup*4 ), - .DmaRegionStart (TCDMBaseAddr ), - .DmaRegionEnd (TCDMBaseAddr+TCDMSize), - .TransFifoDepth (16 ), - .burst_req_t (dma_req_t ), - .meta_t (dma_meta_t ) + .NoMstPorts (NumGroupsPerCluster ), + .DmaRegionWidth (NumBanksPerGroup*4 ), + .DmaRegionStart (TCDMBaseAddr ), + .DmaRegionEnd (TCDMBaseAddr+L1SizePerCluster), + .TransFifoDepth (16 ), + .burst_req_t (dma_req_t ), + .meta_t (dma_meta_t ) ) i_idma_distributed_midend ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -125,7 +126,7 @@ module mempool_cluster .meta_i (dma_meta_q ) ); - for (genvar g = 0; unsigned'(g) < NumGroups; g++) begin: gen_dma_req_group_register + for (genvar g = 0; unsigned'(g) < NumGroupsPerCluster; g++) begin: gen_dma_req_group_register spill_register #( .T(dma_req_t) ) i_dma_req_group_register ( @@ -148,38 +149,38 @@ module mempool_cluster * Groups * ************/ // TCDM interfaces - tcdm_slave_req_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready; - tcdm_master_resp_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready; - tcdm_slave_req_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready; - tcdm_master_resp_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready; - - tcdm_slave_req_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_postreg; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_postreg; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_postreg; - tcdm_master_resp_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_postreg; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid_postreg; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready_postreg; - tcdm_slave_req_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_postreg; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid_postreg; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready_postreg; - tcdm_master_resp_t [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_postreg; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid_postreg; - logic [NumGroups-1:0][NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready_postreg; + tcdm_slave_req_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready; + tcdm_slave_req_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready; + + tcdm_slave_req_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_postreg; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_postreg; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_postreg; + tcdm_master_resp_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_postreg; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid_postreg; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready_postreg; + tcdm_slave_req_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_postreg; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid_postreg; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready_postreg; + tcdm_master_resp_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_postreg; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid_postreg; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready_postreg; /*************** * Registers * ***************/ // Break paths between request and response with registers - for (genvar g = 0; unsigned'(g) < NumGroups; g++) begin: gen_tcdm_registers_g - for (genvar h = 1; unsigned'(h) < NumGroups; h++) begin: gen_tcdm_registers_h + for (genvar g = 0; unsigned'(g) < NumGroupsPerCluster; g++) begin: gen_tcdm_registers_g + for (genvar h = 1; unsigned'(h) < NumGroupsPerCluster; h++) begin: gen_tcdm_registers_h for (genvar sg = 0; unsigned'(sg) < NumSubGroupsPerGroup; sg++) begin: gen_tcdm_registers_sg for (genvar t = 0; unsigned'(t) < NumTilesPerSubGroup; t++) begin: gen_tcdm_registers_t //TCDM @@ -248,10 +249,10 @@ module mempool_cluster **********************/ // Additional AXI registers for breaking TeraPool's long paths // AXI interfaces - axi_tile_req_t [NumAXIMasters-1:0] axi_mst_req; - axi_tile_resp_t [NumAXIMasters-1:0] axi_mst_resp; + axi_tile_req_t [NumAXIMastersPerCluster-1:0] axi_mst_req; + axi_tile_resp_t [NumAXIMastersPerCluster-1:0] axi_mst_resp; - for (genvar m = 0; m < NumAXIMasters; m++) begin: gen_axi_group_cuts + for (genvar m = 0; m < NumAXIMastersPerCluster; m++) begin: gen_axi_group_cuts axi_cut #( .ar_chan_t (axi_tile_ar_t ), .aw_chan_t (axi_tile_aw_t ), @@ -270,7 +271,9 @@ module mempool_cluster ); end: gen_axi_group_cuts - for (genvar g = 0; unsigned'(g) < NumGroups; g++) begin: gen_groups + for (genvar g = 0; unsigned'(g) < NumGroupsPerCluster; g++) begin: gen_groups + logic [idx_width(NumGroups)-1:0] group_id; + assign group_id = cluster_id_i*NumGroupsPerCluster+g[idx_width(NumGroupsPerCluster)-1:0]; if (PostLayoutGr & (g == 0)) begin: gen_postly_group mempool_group_postlayout i_group ( .clk_i (clk_i ), @@ -279,7 +282,7 @@ module mempool_cluster .scan_enable_i (scan_enable_i ), .scan_data_i (/* Unconnected */ ), .scan_data_o (/* Unconnected */ ), - .group_id_i (g[idx_width(NumGroups)-1:0] ), + .group_id_i (group_id ), // TCDM Master interfaces .tcdm_master_req_o (tcdm_master_req[g] ), .tcdm_master_req_valid_o (tcdm_master_req_valid[g] ), @@ -312,7 +315,7 @@ module mempool_cluster .TCDMBaseAddr (TCDMBaseAddr ), .BootAddr (BootAddr ), // For post-synthesis - .GroupId (g[idx_width(NumGroups)-1:0]) + .GroupId (g[idx_width(NumGroupsPerCluster)-1:0]) ) i_group ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -320,7 +323,7 @@ module mempool_cluster .scan_enable_i (scan_enable_i ), .scan_data_i (/* Unconnected */ ), .scan_data_o (/* Unconnected */ ), - .group_id_i (g[idx_width(NumGroups)-1:0] ), + .group_id_i (group_id ), // TCDM Master interfaces .tcdm_master_req_o (tcdm_master_req[g] ), .tcdm_master_req_valid_o (tcdm_master_req_valid[g] ), @@ -358,7 +361,7 @@ module mempool_cluster .scan_enable_i (scan_enable_i ), .scan_data_i (/* Unconnected */ ), .scan_data_o (/* Unconnected */ ), - .group_id_i (g[idx_width(NumGroups)-1:0] ), + .group_id_i (group_id ), // TCDM Master interfaces .tcdm_master_req_o (tcdm_master_req[g] ), .tcdm_master_req_valid_o (tcdm_master_req_valid[g] ), @@ -392,8 +395,8 @@ module mempool_cluster * Interconnects * *******************/ - for (genvar ini = 0; ini < NumGroups; ini++) begin: gen_interconnections_ini - for (genvar tgt = 0; tgt < NumGroups; tgt++) begin: gen_interconnections_tgt + for (genvar ini = 0; ini < NumGroupsPerCluster; ini++) begin: gen_interconnections_ini + for (genvar tgt = 0; tgt < NumGroupsPerCluster; tgt++) begin: gen_interconnections_tgt // The local connections are inside the groups if (ini != tgt) begin: gen_remote_interconnections assign tcdm_slave_req_postreg[tgt][ini ^ tgt] = tcdm_master_req_postreg[ini][ini ^ tgt]; @@ -417,20 +420,22 @@ module mempool_cluster ************/ // TCDM interfaces - tcdm_slave_req_t [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_req; - logic [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_req_valid; - logic [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_req_ready; - tcdm_master_resp_t [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_resp; - logic [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_resp_valid; - logic [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_resp_ready; - tcdm_slave_req_t [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_req; - logic [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_req_valid; - logic [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_req_ready; - tcdm_master_resp_t [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp; - logic [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_valid; - logic [NumGroups-1:0][NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_ready; - - for (genvar g = 0; unsigned'(g) < NumGroups; g++) begin: gen_groups + tcdm_slave_req_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_req; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_req_valid; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_resp; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_resp_valid; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_resp_ready; + tcdm_slave_req_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_req; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_req_valid; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_valid; + logic [NumGroupsPerCluster-1:0][NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_ready; + + for (genvar g = 0; unsigned'(g) < NumGroupsPerCluster; g++) begin: gen_groups + logic [idx_width(NumGroups)-1:0] group_id; + assign group_id = cluster_id_i*NumGroupsPerCluster+g[idx_width(NumGroupsPerCluster)-1:0]; mempool_group #( .TCDMBaseAddr (TCDMBaseAddr ), .BootAddr (BootAddr ) @@ -441,7 +446,7 @@ module mempool_cluster .scan_enable_i (scan_enable_i ), .scan_data_i (/* Unconnected */ ), .scan_data_o (/* Unconnected */ ), - .group_id_i (g[idx_width(NumGroups)-1:0] ), + .group_id_i (group_id ), // TCDM Master interfaces .tcdm_master_req_o (tcdm_master_req[g] ), .tcdm_master_req_valid_o (tcdm_master_req_valid[g] ), @@ -474,8 +479,8 @@ module mempool_cluster * Interconnects * *******************/ - for (genvar ini = 0; ini < NumGroups; ini++) begin: gen_interconnections_ini - for (genvar tgt = 0; tgt < NumGroups; tgt++) begin: gen_interconnections_tgt + for (genvar ini = 0; ini < NumGroupsPerCluster; ini++) begin: gen_interconnections_ini + for (genvar tgt = 0; tgt < NumGroupsPerCluster; tgt++) begin: gen_interconnections_tgt // The local connections are inside the groups if (ini != tgt) begin: gen_remote_interconnections assign tcdm_slave_req[tgt][ini ^ tgt] = tcdm_master_req[ini][ini ^ tgt]; @@ -495,18 +500,21 @@ module mempool_cluster ****************/ if (NumCoresPerCluster > 1024) - $fatal(1, "[mempool] The MemPool cluster is currently limited to 1024 cores."); + $fatal(1, "[mempool_cluster] The MemPool cluster is currently limited to 1024 cores."); if (NumTilesPerCluster < NumGroupsPerCluster) - $fatal(1, "[mempool] MemPool requires more tiles than groups."); + $fatal(1, "[mempool_cluster] MemPool requires more tiles than groups."); if (NumCoresPerCluster != NumTilesPerCluster * NumCoresPerTile) - $fatal(1, "[mempool] The number of cores is not divisible by the number of cores per tile."); + $fatal(1, "[mempool_cluster] The number of cores is not divisible by the number of cores per tile."); + + if (NumGroupsPerCluster != 4) + $fatal(1, "[mempool_cluster] The number of Groups per cluster must be 4."); if (BankingFactor < 1) - $fatal(1, "[mempool] The banking factor must be a positive integer."); + $fatal(1, "[mempool_cluster] The banking factor must be a positive integer."); if (BankingFactor != 2**$clog2(BankingFactor)) - $fatal(1, "[mempool] The banking factor must be a power of two."); + $fatal(1, "[mempool_cluster] The banking factor must be a power of two."); endmodule : mempool_cluster diff --git a/hardware/src/mempool_group.sv b/hardware/src/mempool_group.sv index 733f98b9c..7e27ccb3a 100644 --- a/hardware/src/mempool_group.sv +++ b/hardware/src/mempool_group.sv @@ -29,34 +29,34 @@ module mempool_group input logic [idx_width(NumGroups)-1:0] group_id_i, `ifdef TERAPOOL // TCDM Master interfaces - output `STRUCT_VECT(tcdm_slave_req_t, [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0]) tcdm_master_req_o, - output logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_o, - input logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_i, - input `STRUCT_VECT(tcdm_master_resp_t, [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0]) tcdm_master_resp_i, - input logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid_i, - output logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready_o, + output `STRUCT_VECT(tcdm_slave_req_t, [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0]) tcdm_master_req_o, + output logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_o, + input logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_i, + input `STRUCT_VECT(tcdm_master_resp_t, [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0]) tcdm_master_resp_i, + input logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid_i, + output logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready_o, // TCDM Slave interfaces - input `STRUCT_VECT(tcdm_slave_req_t, [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0]) tcdm_slave_req_i, - input logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid_i, - output logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready_o, - output `STRUCT_VECT(tcdm_master_resp_t, [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0]) tcdm_slave_resp_o, - output logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid_o, - input logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready_i, + input `STRUCT_VECT(tcdm_slave_req_t, [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0]) tcdm_slave_req_i, + input logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid_i, + output logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready_o, + output `STRUCT_VECT(tcdm_master_resp_t, [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0]) tcdm_slave_resp_o, + output logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid_o, + input logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready_i, `else // TCDM Master interfaces - output `STRUCT_VECT(tcdm_slave_req_t, [NumGroups-1:1][NumTilesPerGroup-1:0]) tcdm_master_req_o, - output logic [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_req_valid_o, - input logic [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_req_ready_i, - input `STRUCT_VECT(tcdm_master_resp_t, [NumGroups-1:1][NumTilesPerGroup-1:0]) tcdm_master_resp_i, - input logic [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_resp_valid_i, - output logic [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_resp_ready_o, + output `STRUCT_VECT(tcdm_slave_req_t, [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0]) tcdm_master_req_o, + output logic [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_req_valid_o, + input logic [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_req_ready_i, + input `STRUCT_VECT(tcdm_master_resp_t, [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0]) tcdm_master_resp_i, + input logic [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_resp_valid_i, + output logic [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_resp_ready_o, // TCDM Slave interfaces - input `STRUCT_VECT(tcdm_slave_req_t, [NumGroups-1:1][NumTilesPerGroup-1:0]) tcdm_slave_req_i, - input logic [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_req_valid_i, - output logic [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_req_ready_o, - output `STRUCT_VECT(tcdm_master_resp_t, [NumGroups-1:1][NumTilesPerGroup-1:0]) tcdm_slave_resp_o, - output logic [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_valid_o, - input logic [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_ready_i, + input `STRUCT_VECT(tcdm_slave_req_t, [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0]) tcdm_slave_req_i, + input logic [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_req_valid_i, + output logic [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_req_ready_o, + output `STRUCT_VECT(tcdm_master_resp_t, [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0]) tcdm_slave_resp_o, + output logic [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_valid_o, + input logic [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_ready_i, `endif // Wake up interface input logic [NumCoresPerGroup-1:0] wake_up_i, @@ -98,14 +98,14 @@ module mempool_group // The ports might be structs flattened to vectors. To access the structs' // internal signals, assign the flattened vectors back to structs. `ifdef TERAPOOL - tcdm_slave_req_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_s; - tcdm_master_resp_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_s; + tcdm_slave_req_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_s; + tcdm_master_resp_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_s; `else - tcdm_slave_req_t [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_master_req_s; - tcdm_master_resp_t [NumGroups-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_s; + tcdm_slave_req_t [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_master_req_s; + tcdm_master_resp_t [NumGroupsPerCluster-1:1][NumTilesPerGroup-1:0] tcdm_slave_resp_s; `endif - for (genvar r = 1; r < NumGroups; r++) begin: gen_tcdm_struct + for (genvar r = 1; r < NumGroupsPerCluster; r++) begin: gen_tcdm_struct assign tcdm_master_req_o[r] = tcdm_master_req_s[r]; assign tcdm_slave_resp_o[r] = tcdm_slave_resp_s[r]; end: gen_tcdm_struct @@ -129,36 +129,36 @@ module mempool_group ****************/ // TCDM interfaces for groups - tcdm_master_req_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_from_sg; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_from_sg; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_to_sg; - tcdm_slave_req_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_to_sg; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid_to_sg; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready_from_sg; - tcdm_master_resp_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_to_sg; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid_to_sg; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready_from_sg; - tcdm_slave_resp_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_from_sg; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid_from_sg; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready_to_sg; - - tcdm_master_req_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready; - tcdm_slave_req_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready; - tcdm_master_resp_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready; - tcdm_slave_resp_t [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid; - logic [NumGroups-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready; + tcdm_master_req_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_from_sg; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_from_sg; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_to_sg; + tcdm_slave_req_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_to_sg; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid_to_sg; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready_from_sg; + tcdm_master_resp_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_to_sg; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid_to_sg; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready_from_sg; + tcdm_slave_resp_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_from_sg; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid_from_sg; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready_to_sg; + + tcdm_master_req_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_valid; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_req_ready; + tcdm_slave_req_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready; + tcdm_slave_resp_t [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid; + logic [NumGroupsPerCluster-1:1][NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready; // TCDM Spill Registers // Control by different target remote access cycles if (RemoteGroupLatencyCycle == 11) begin - for (genvar h = 1; unsigned'(h) < NumGroups; h++) begin: gen_tcdm_registers_to_intrco_g + for (genvar h = 1; unsigned'(h) < NumGroupsPerCluster; h++) begin: gen_tcdm_registers_to_intrco_g for (genvar sg = 0; unsigned'(sg) < NumSubGroupsPerGroup; sg++) begin: gen_tcdm_registers_to_intrco_sg for (genvar t = 0; unsigned'(t) < NumTilesPerSubGroup; t++) begin: gen_tcdm_registers_to_intrco_t spill_register #( @@ -198,7 +198,7 @@ module mempool_group end if (RemoteGroupLatencyCycle == 9 || RemoteGroupLatencyCycle == 11) begin - for (genvar h = 1; unsigned'(h) < NumGroups; h++) begin: gen_tcdm_registers_to_sg_g + for (genvar h = 1; unsigned'(h) < NumGroupsPerCluster; h++) begin: gen_tcdm_registers_to_sg_g for (genvar sg = 0; unsigned'(sg) < NumSubGroupsPerGroup; sg++) begin: gen_tcdm_registers_to_sg_sg for (genvar t = 0; unsigned'(t) < NumTilesPerSubGroup; t++) begin: gen_tcdm_registers_to_sg_t spill_register #( @@ -258,12 +258,12 @@ module mempool_group dma_meta_t [NumDmasPerGroup-1:0] dma_meta; // Connect the IOs to the SubGroups' signals - assign tcdm_master_resp[NumGroups-1:1] = tcdm_master_resp_i[NumGroups-1:1]; - assign tcdm_master_resp_valid[NumGroups-1:1] = tcdm_master_resp_valid_i[NumGroups-1:1]; - assign tcdm_master_resp_ready_o[NumGroups-1:1] = tcdm_master_resp_ready[NumGroups-1:1]; - assign tcdm_slave_req[NumGroups-1:1] = tcdm_slave_req_i[NumGroups-1:1]; - assign tcdm_slave_req_valid[NumGroups-1:1] = tcdm_slave_req_valid_i[NumGroups-1:1]; - assign tcdm_slave_req_ready_o[NumGroups-1:1] = tcdm_slave_req_ready[NumGroups-1:1]; + assign tcdm_master_resp[NumGroupsPerCluster-1:1] = tcdm_master_resp_i[NumGroupsPerCluster-1:1]; + assign tcdm_master_resp_valid[NumGroupsPerCluster-1:1] = tcdm_master_resp_valid_i[NumGroupsPerCluster-1:1]; + assign tcdm_master_resp_ready_o[NumGroupsPerCluster-1:1] = tcdm_master_resp_ready[NumGroupsPerCluster-1:1]; + assign tcdm_slave_req[NumGroupsPerCluster-1:1] = tcdm_slave_req_i[NumGroupsPerCluster-1:1]; + assign tcdm_slave_req_valid[NumGroupsPerCluster-1:1] = tcdm_slave_req_valid_i[NumGroupsPerCluster-1:1]; + assign tcdm_slave_req_ready_o[NumGroupsPerCluster-1:1] = tcdm_slave_req_ready[NumGroupsPerCluster-1:1]; // AXI interfaces axi_tile_req_t [NumAXIMastersPerGroup-1:0] axi_mst_req; @@ -273,18 +273,18 @@ module mempool_group sub_group_id_t id; assign id = (group_id_i << $clog2(NumSubGroupsPerGroup)) | sg[idx_width(NumSubGroupsPerGroup)-1:0]; - tcdm_master_req_t [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_req; - logic [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_req_valid; - logic [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_req_ready; - tcdm_slave_req_t [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_req; - logic [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_req_valid; - logic [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_req_ready; - tcdm_master_resp_t [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_resp; - logic [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_resp_valid; - logic [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_resp_ready; - tcdm_slave_resp_t [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_resp; - logic [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_resp_valid; - logic [NumGroups-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_resp_ready; + tcdm_master_req_t [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_req; + logic [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_req_valid; + logic [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_req_ready; + tcdm_slave_req_t [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_req; + logic [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_req_valid; + logic [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_resp; + logic [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_resp_valid; + logic [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_master_resp_ready; + tcdm_slave_resp_t [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_resp; + logic [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_resp_valid; + logic [NumGroupsPerCluster-1:1] [NumTilesPerSubGroup-1:0] tran_tcdm_slave_resp_ready; if (PostLayoutSg & (GroupId == 0) & (sg == 0)) begin: gen_postly_sg mempool_sub_group_postlayout i_sub_group ( @@ -389,7 +389,7 @@ module mempool_group ); end // Transpose the group requests - for (genvar g = 1; g < NumGroups; g++) begin: gen_tran_group_req + for (genvar g = 1; g < NumGroupsPerCluster; g++) begin: gen_tran_group_req assign tcdm_master_req_from_sg[g][sg] = tran_tcdm_master_req[g]; assign tcdm_master_req_valid_from_sg[g][sg] = tran_tcdm_master_req_valid[g]; assign tran_tcdm_master_req_ready[g] = tcdm_master_req_ready_to_sg[g][sg]; @@ -427,7 +427,7 @@ module mempool_group * Remote Group Interconnects * ********************************/ - for (genvar r = 1; r < NumGroups; r++) begin: gen_remote_interco + for (genvar r = 1; r < NumGroupsPerCluster; r++) begin: gen_remote_interco logic [(NumSubGroupsPerGroup * NumTilesPerSubGroup)-1:0] master_remote_req_valid; logic [(NumSubGroupsPerGroup * NumTilesPerSubGroup)-1:0] master_remote_req_ready; tcdm_addr_t [(NumSubGroupsPerGroup * NumTilesPerSubGroup)-1:0] master_remote_req_tgt_addr; @@ -564,7 +564,7 @@ module mempool_group .NoMstPorts (NumDmasPerGroup ), .DmaRegionWidth (NumBanksPerGroup*4/NumDmasPerGroup ), .DmaRegionStart (TCDMBaseAddr ), - .DmaRegionEnd (TCDMBaseAddr+TCDMSize ), + .DmaRegionEnd (TCDMBaseAddr+L1SizePerCluster ), .TransFifoDepth (16 ), .burst_req_t (dma_req_t ), .meta_t (dma_meta_t ) @@ -598,18 +598,18 @@ module mempool_group ***********/ // TCDM interfaces - tcdm_master_req_t [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_master_req; - logic [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_master_req_valid; - logic [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_master_req_ready; - tcdm_slave_req_t [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_slave_req; - logic [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_slave_req_valid; - logic [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_slave_req_ready; - tcdm_master_resp_t [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_master_resp; - logic [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_master_resp_valid; - logic [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_master_resp_ready; - tcdm_slave_resp_t [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_slave_resp; - logic [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_slave_resp_valid; - logic [NumGroups-1:0][NumTilesPerGroup-1:0] tcdm_slave_resp_ready; + tcdm_master_req_t [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_master_req; + logic [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_master_req_valid; + logic [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_master_req_ready; + tcdm_slave_req_t [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_slave_req; + logic [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_slave_req_valid; + logic [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_slave_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_master_resp; + logic [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_master_resp_valid; + logic [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_master_resp_ready; + tcdm_slave_resp_t [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_slave_resp; + logic [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_slave_resp_valid; + logic [NumGroupsPerCluster-1:0][NumTilesPerGroup-1:0] tcdm_slave_resp_ready; // DMA interfaces tcdm_dma_req_t [NumTilesPerGroup-1:0] tcdm_dma_req; logic [NumTilesPerGroup-1:0] tcdm_dma_req_valid; @@ -619,12 +619,12 @@ module mempool_group logic [NumTilesPerGroup-1:0] tcdm_dma_resp_ready; // Connect the IOs to the tiles' signals - assign tcdm_master_resp[NumGroups-1:1] = tcdm_master_resp_i[NumGroups-1:1]; - assign tcdm_master_resp_valid[NumGroups-1:1] = tcdm_master_resp_valid_i[NumGroups-1:1]; - assign tcdm_master_resp_ready_o[NumGroups-1:1] = tcdm_master_resp_ready[NumGroups-1:1]; - assign tcdm_slave_req[NumGroups-1:1] = tcdm_slave_req_i[NumGroups-1:1]; - assign tcdm_slave_req_valid[NumGroups-1:1] = tcdm_slave_req_valid_i[NumGroups-1:1]; - assign tcdm_slave_req_ready_o[NumGroups-1:1] = tcdm_slave_req_ready[NumGroups-1:1]; + assign tcdm_master_resp[NumGroupsPerCluster-1:1] = tcdm_master_resp_i[NumGroupsPerCluster-1:1]; + assign tcdm_master_resp_valid[NumGroupsPerCluster-1:1] = tcdm_master_resp_valid_i[NumGroupsPerCluster-1:1]; + assign tcdm_master_resp_ready_o[NumGroupsPerCluster-1:1] = tcdm_master_resp_ready[NumGroupsPerCluster-1:1]; + assign tcdm_slave_req[NumGroupsPerCluster-1:1] = tcdm_slave_req_i[NumGroupsPerCluster-1:1]; + assign tcdm_slave_req_valid[NumGroupsPerCluster-1:1] = tcdm_slave_req_valid_i[NumGroupsPerCluster-1:1]; + assign tcdm_slave_req_ready_o[NumGroupsPerCluster-1:1] = tcdm_slave_req_ready[NumGroupsPerCluster-1:1]; // AXI interfaces axi_tile_req_t [NumTilesPerGroup-1:0] axi_tile_req; @@ -636,18 +636,18 @@ module mempool_group tile_id_t id; assign id = (group_id_i << $clog2(NumTilesPerGroup)) | t[idx_width(NumTilesPerGroup)-1:0]; - tcdm_master_req_t [NumGroups-1:0] tran_tcdm_master_req; - logic [NumGroups-1:0] tran_tcdm_master_req_valid; - logic [NumGroups-1:0] tran_tcdm_master_req_ready; - tcdm_slave_req_t [NumGroups-1:0] tran_tcdm_slave_req; - logic [NumGroups-1:0] tran_tcdm_slave_req_valid; - logic [NumGroups-1:0] tran_tcdm_slave_req_ready; - tcdm_master_resp_t [NumGroups-1:0] tran_tcdm_master_resp; - logic [NumGroups-1:0] tran_tcdm_master_resp_valid; - logic [NumGroups-1:0] tran_tcdm_master_resp_ready; - tcdm_slave_resp_t [NumGroups-1:0] tran_tcdm_slave_resp; - logic [NumGroups-1:0] tran_tcdm_slave_resp_valid; - logic [NumGroups-1:0] tran_tcdm_slave_resp_ready; + tcdm_master_req_t [NumGroupsPerCluster-1:0] tran_tcdm_master_req; + logic [NumGroupsPerCluster-1:0] tran_tcdm_master_req_valid; + logic [NumGroupsPerCluster-1:0] tran_tcdm_master_req_ready; + tcdm_slave_req_t [NumGroupsPerCluster-1:0] tran_tcdm_slave_req; + logic [NumGroupsPerCluster-1:0] tran_tcdm_slave_req_valid; + logic [NumGroupsPerCluster-1:0] tran_tcdm_slave_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:0] tran_tcdm_master_resp; + logic [NumGroupsPerCluster-1:0] tran_tcdm_master_resp_valid; + logic [NumGroupsPerCluster-1:0] tran_tcdm_master_resp_ready; + tcdm_slave_resp_t [NumGroupsPerCluster-1:0] tran_tcdm_slave_resp; + logic [NumGroupsPerCluster-1:0] tran_tcdm_slave_resp_valid; + logic [NumGroupsPerCluster-1:0] tran_tcdm_slave_resp_ready; mempool_tile #( .TCDMBaseAddr(TCDMBaseAddr), @@ -688,7 +688,7 @@ module mempool_group ); // Transpose the group requests - for (genvar g = 0; g < NumGroups; g++) begin: gen_tran_group_req + for (genvar g = 0; g < NumGroupsPerCluster; g++) begin: gen_tran_group_req assign tcdm_master_req[g][t] = tran_tcdm_master_req[g]; assign tcdm_master_req_valid[g][t] = tran_tcdm_master_req_valid[g]; assign tran_tcdm_master_req_ready[g] = tcdm_master_req_ready[g][t]; @@ -708,7 +708,7 @@ module mempool_group * Local Interconnect * *************************/ - // The local port is always at the index 0 out of the NumGroups TCDM ports of the tile. + // The local port is always at the index 0 out of the NumGroupsPerCluster TCDM ports of the tile. logic [NumTilesPerGroup-1:0] master_local_req_valid; logic [NumTilesPerGroup-1:0] master_local_req_ready; @@ -796,7 +796,7 @@ module mempool_group * Remote Interconnects * **************************/ - for (genvar r = 1; r < NumGroups; r++) begin: gen_remote_interco + for (genvar r = 1; r < NumGroupsPerCluster; r++) begin: gen_remote_interco logic [NumTilesPerGroup-1:0] master_remote_req_valid; logic [NumTilesPerGroup-1:0] master_remote_req_ready; tcdm_addr_t [NumTilesPerGroup-1:0] master_remote_req_tgt_addr; @@ -974,7 +974,7 @@ module mempool_group .NoMstPorts (NumDmasPerGroup ), .DmaRegionWidth (NumBanksPerGroup*4/NumDmasPerGroup), .DmaRegionStart (TCDMBaseAddr ), - .DmaRegionEnd (TCDMBaseAddr+TCDMSize ), + .DmaRegionEnd (TCDMBaseAddr+L1SizePerCluster ), .TransFifoDepth (16 ), .burst_req_t (dma_req_t ), .meta_t (dma_meta_t ) @@ -1002,7 +1002,7 @@ module mempool_group assign addr_map = '{ '{ // TCDM start_addr: TCDMBaseAddr, - end_addr: TCDMBaseAddr + TCDMSize, + end_addr: TCDMBaseAddr + L1SizePerCluster, idx: 1 } }; @@ -1146,7 +1146,7 @@ module mempool_group wdata: dma_tile_req[t].q.data, wen: dma_tile_req[t].q.write, be: dma_tile_req[t].q.strb, - tgt_addr: {dma_tile_req[t].q.addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroups)+:TCDMAddrMemWidth], + tgt_addr: {dma_tile_req[t].q.addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroupsPerCluster)+:TCDMAddrMemWidth], dma_tile_req[t].q.addr[ByteOffset+:idx_width(NumBanksPerTile)]} }; assign tcdm_dma_req_valid[d*NumTilesPerDma+t] = dma_tile_req[t].q_valid; diff --git a/hardware/src/mempool_pkg.sv b/hardware/src/mempool_pkg.sv index 62aa02fdd..d45a0bd08 100644 --- a/hardware/src/mempool_pkg.sv +++ b/hardware/src/mempool_pkg.sv @@ -36,21 +36,22 @@ package mempool_pkg; * MEMORY PARAMETERS * ***********************/ - localparam integer unsigned AddrWidth = 32; - localparam integer unsigned DataWidth = 32; - localparam integer unsigned BeWidth = DataWidth / 8; - localparam integer unsigned ByteOffset = $clog2(BeWidth); + localparam integer unsigned AddrWidth = 32; + localparam integer unsigned DataWidth = 32; + localparam integer unsigned BeWidth = DataWidth / 8; + localparam integer unsigned ByteOffset = $clog2(BeWidth); // L1 SPM memory - localparam integer unsigned BankingFactor = `ifdef BANKING_FACTOR `BANKING_FACTOR `else 0 `endif; - localparam bit LrScEnable = 1'b1; - localparam integer unsigned TCDMSizePerBank = `ifdef L1_BANK_SIZE `L1_BANK_SIZE `else 0 `endif; - localparam integer unsigned NumBanks = NumCores * BankingFactor; - localparam integer unsigned L1Size = NumCores * BankingFactor * TCDMSizePerBank; - localparam integer unsigned L1SizePerCluster = L1Size / NumClusters; - localparam integer unsigned NumBanksPerTile = NumBanks / NumTiles; - localparam integer unsigned NumBanksPerGroup = NumBanks / NumGroups; - localparam integer unsigned TCDMAddrMemWidth = $clog2(TCDMSizePerBank / mempool_pkg::BeWidth); - localparam integer unsigned TCDMAddrWidth = TCDMAddrMemWidth + idx_width(NumBanksPerGroup); + localparam integer unsigned BankingFactor = `ifdef BANKING_FACTOR `BANKING_FACTOR `else 0 `endif; + localparam bit LrScEnable = 1'b1; + localparam integer unsigned TCDMSizePerBank = `ifdef L1_BANK_SIZE `L1_BANK_SIZE `else 0 `endif; + localparam integer unsigned NumBanks = NumCores * BankingFactor; + localparam integer unsigned L1Size = NumCores * BankingFactor * TCDMSizePerBank; + localparam integer unsigned L1SizePerCluster = L1Size / NumClusters; + localparam integer unsigned NumBanksPerTile = NumBanks / NumTiles; + localparam integer unsigned NumBanksPerGroup = NumBanks / NumGroups; + localparam integer unsigned NumBanksPerCluster = NumBanks / NumClusters; + localparam integer unsigned TCDMAddrMemWidth = $clog2(TCDMSizePerBank / mempool_pkg::BeWidth); + localparam integer unsigned TCDMAddrWidth = TCDMAddrMemWidth + idx_width(NumBanksPerGroup); // L2 localparam integer unsigned L2Size = `ifdef L2_SIZE `L2_SIZE `else 0 `endif; // [B] @@ -106,6 +107,7 @@ package mempool_pkg; `endif localparam integer unsigned NumAXIMastersPerGroup = `ifdef AXI_MASTERS_PER_GROUP `AXI_MASTERS_PER_GROUP `else 1 `endif;; + localparam integer unsigned NumAXIMastersPerCluster = NumAXIMastersPerGroup * NumGroupsPerCluster; localparam NumSystemXbarMasters = (NumGroups * NumAXIMastersPerGroup) + 1; // +1 because the external host is also a master localparam AxiSystemIdWidth = $clog2(NumSystemXbarMasters) + AxiTileIdWidth; @@ -310,8 +312,7 @@ package mempool_pkg; *****************/ // TCDM Memory Region - localparam addr_t TCDMSize = NumBanks * TCDMSizePerBank; - localparam addr_t TCDMMask = ~(TCDMSize - 1); + localparam addr_t TCDMMask = ~(L1SizePerCluster - 1); // Size in bytes of memory that is sequentially addressable per tile localparam int unsigned SeqMemSizePerCore = `ifdef SEQ_MEM_SIZE `SEQ_MEM_SIZE `else 0 `endif; diff --git a/hardware/src/mempool_sub_group.sv b/hardware/src/mempool_sub_group.sv index a3577450f..2c764f9d1 100644 --- a/hardware/src/mempool_sub_group.sv +++ b/hardware/src/mempool_sub_group.sv @@ -24,19 +24,19 @@ module mempool_sub_group // Group ID input logic [idx_width(NumSubGroups)-1:0] sub_group_id_i, // TCDM Master interfaces for remote groups - output `STRUCT_VECT(tcdm_master_req_t, [NumGroups-1:1][NumTilesPerSubGroup-1:0]) tcdm_master_req_o, - output logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_o, - input logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_i, - input `STRUCT_VECT(tcdm_master_resp_t, [NumGroups-1:1][NumTilesPerSubGroup-1:0]) tcdm_master_resp_i, - input logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid_i, - output logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready_o, + output `STRUCT_VECT(tcdm_master_req_t, [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0]) tcdm_master_req_o, + output logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req_valid_o, + input logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req_ready_i, + input `STRUCT_VECT(tcdm_master_resp_t, [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0]) tcdm_master_resp_i, + input logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid_i, + output logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready_o, // TCDM Slave interfaces for remote groups - input `STRUCT_VECT(tcdm_slave_req_t, [NumGroups-1:1][NumTilesPerSubGroup-1:0]) tcdm_slave_req_i, - input logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid_i, - output logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready_o, - output `STRUCT_VECT(tcdm_slave_resp_t, [NumGroups-1:1][NumTilesPerSubGroup-1:0]) tcdm_slave_resp_o, - output logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid_o, - input logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready_i, + input `STRUCT_VECT(tcdm_slave_req_t, [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0]) tcdm_slave_req_i, + input logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid_i, + output logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready_o, + output `STRUCT_VECT(tcdm_slave_resp_t, [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0]) tcdm_slave_resp_o, + output logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid_o, + input logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready_i, // TCDM Master interfaces for remote sub_groups output `STRUCT_VECT(tcdm_slave_req_t, [NumSubGroupsPerGroup-1:1][NumTilesPerSubGroup-1:0]) tcdm_sg_master_req_o, output logic [NumSubGroupsPerGroup-1:1][NumTilesPerSubGroup-1:0] tcdm_sg_master_req_valid_o, @@ -70,7 +70,7 @@ module mempool_sub_group * Definitions * *****************/ - typedef logic [idx_width(NumTiles)-1:0] tile_id_t; + typedef logic [idx_width(NumTilesPerCluster)-1:0] tile_id_t; /********************* * Control Signals * @@ -100,18 +100,18 @@ module mempool_sub_group ***********/ // TCDM interfaces for remote groups - tcdm_master_req_t [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req; - logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req_valid; - logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req_ready; - tcdm_slave_req_t [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req; - logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid; - logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready; - tcdm_master_resp_t [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp; - logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid; - logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready; - tcdm_slave_resp_t [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp; - logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid; - logic [NumGroups-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready; + tcdm_master_req_t [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req; + logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req_valid; + logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_req_ready; + tcdm_slave_req_t [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req; + logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req_valid; + logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp; + logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp_valid; + logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_master_resp_ready; + tcdm_slave_resp_t [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp; + logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp_valid; + logic [NumGroupsPerCluster-1:1][NumTilesPerSubGroup-1:0] tcdm_slave_resp_ready; // TCDM interfaces for sub_groups tcdm_master_req_t [NumSubGroupsPerGroup-1:0][NumTilesPerSubGroup-1:0] tcdm_sg_master_req; @@ -151,18 +151,18 @@ module mempool_sub_group tile_id_t id; assign id = (sub_group_id_i << $clog2(NumTilesPerSubGroup)) | t[idx_width(NumTilesPerSubGroup)-1:0]; - tcdm_master_req_t [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_req; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_req_valid; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_req_ready; - tcdm_slave_req_t [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_req; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_req_valid; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_req_ready; - tcdm_master_resp_t [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_resp; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_resp_valid; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_resp_ready; - tcdm_slave_resp_t [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_resp; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_resp_valid; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_resp_ready; + tcdm_master_req_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_req; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_req_valid; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_req_ready; + tcdm_slave_req_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_req; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_req_valid; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_req_ready; + tcdm_master_resp_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_resp; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_resp_valid; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_master_resp_ready; + tcdm_slave_resp_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_resp; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_resp_valid; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tran_tcdm_slave_resp_ready; mempool_tile #( .TCDMBaseAddr(TCDMBaseAddr), @@ -219,7 +219,7 @@ module mempool_sub_group end: gen_tran_sub_group_req // Transpose the group requests - for (genvar g = 1; g < NumGroups; g++) begin: gen_tran_group_req + for (genvar g = 1; g < NumGroupsPerCluster; g++) begin: gen_tran_group_req assign tcdm_master_req[g][t] = tran_tcdm_master_req[g+NumSubGroupsPerGroup-1]; assign tcdm_master_req_valid[g][t] = tran_tcdm_master_req_valid[g+NumSubGroupsPerGroup-1]; assign tran_tcdm_master_req_ready[g+NumSubGroupsPerGroup-1] = tcdm_master_req_ready[g][t]; @@ -239,7 +239,7 @@ module mempool_sub_group * Local Interconnect * *************************/ - // The local port is always at the index 0 out of the NumGroups TCDM ports of the tile. + // The local port is always at the index 0 out of the NumGroupsPerCluster TCDM ports of the tile. logic [NumTilesPerSubGroup-1:0] master_local_req_valid; logic [NumTilesPerSubGroup-1:0] master_local_req_ready; @@ -490,7 +490,7 @@ module mempool_sub_group assign addr_map = '{ '{ // TCDM start_addr: TCDMBaseAddr, - end_addr: TCDMBaseAddr + TCDMSize, + end_addr: TCDMBaseAddr + L1SizePerCluster, idx: 1 } }; @@ -636,7 +636,7 @@ module mempool_sub_group wdata: dma_tile_req[t].q.data, wen: dma_tile_req[t].q.write, be: dma_tile_req[t].q.strb, - tgt_addr: {dma_tile_req[t].q.addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroups)+:TCDMAddrMemWidth], + tgt_addr: {dma_tile_req[t].q.addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroupsPerCluster)+:TCDMAddrMemWidth], dma_tile_req[t].q.addr[ByteOffset+:idx_width(NumBanksPerTile)]} }; assign tcdm_dma_req_valid[d*NumTilesPerDma+t] = dma_tile_req[t].q_valid; diff --git a/hardware/src/mempool_system.sv b/hardware/src/mempool_system.sv index 9dab93693..b4afb6b4c 100644 --- a/hardware/src/mempool_system.sv +++ b/hardware/src/mempool_system.sv @@ -134,11 +134,12 @@ module mempool_system ********************/ for (genvar i = 0; i < NumClusters; i++) begin : gen_clusters mempool_cluster #( - .TCDMBaseAddr(i*L1SizePerCluster), + .TCDMBaseAddr(i*L1SizePerCluster), // TODO: i*L1SizePerCluster .BootAddr (BootAddr ) ) i_mempool_cluster ( .clk_i (clk_i ), .rst_ni (rst_ni ), + .cluster_id_i (i ), .wake_up_i (wake_up[i*NumCoresPerCluster+:NumCoresPerCluster] ), .testmode_i (1'b0 ), .scan_enable_i (1'b0 ), @@ -149,8 +150,8 @@ module mempool_system .dma_req_valid_i(dma_req_valid[i] ), .dma_req_ready_o(dma_req_ready[i] ), .dma_meta_o (dma_meta[i] ), - .axi_mst_req_o (axi_mst_req[i*NumAXIMastersPerGroup+:NumAXIMastersPerGroup] ), - .axi_mst_resp_i (axi_mst_resp[i*NumAXIMastersPerGroup+:NumAXIMastersPerGroup]) + .axi_mst_req_o (axi_mst_req[i*NumAXIMastersPerCluster+:NumAXIMastersPerCluster] ), + .axi_mst_resp_i (axi_mst_resp[i*NumAXIMastersPerCluster+:NumAXIMastersPerCluster]) ); end @@ -282,7 +283,7 @@ module mempool_system .AddrWidth (L2AddrWidth ), .DataWidth (AxiDataWidth ), .IdWidth (AxiTileIdWidth ), - .BufDepth (3 ), + .BufDepth (0 ), .reqrsp_req_t (axi_to_l2_req_t), .reqrsp_rsp_t (axi_to_l2_rsp_t) ) i_axi_to_reqrsp ( @@ -309,7 +310,7 @@ module mempool_system .NumInp (NumAXIMasters ), .NumOut (NumL2Banks ), .payload_t (axi_to_l2_req_chan_t), - .OutSpillReg (1'b1 ), + .OutSpillReg (1'b0 ), .ExtPrio (1'b0 ), .AxiVldRdy (1'b1 ), .LockIn (1'b1 ) @@ -778,7 +779,7 @@ module mempool_system ctrl_registers #( .TCDMBaseAddr (TCDMBaseAddr ), - .TCDMSize (TCDMSize ), + .TCDMSize (L1Size ), .NumCores (NumCores ), .axi_lite_req_t (axi_lite_slv_req_t ), .axi_lite_resp_t(axi_lite_slv_resp_t) diff --git a/hardware/src/mempool_tile.sv b/hardware/src/mempool_tile.sv index 961488bc4..6a5596213 100644 --- a/hardware/src/mempool_tile.sv +++ b/hardware/src/mempool_tile.sv @@ -28,19 +28,19 @@ module mempool_tile // Tile ID input logic [idx_width(NumTiles)-1:0] tile_id_i, // TCDM Master interfaces - output `STRUCT_VECT(tcdm_master_req_t, [NumGroups+NumSubGroupsPerGroup-1-1:0]) tcdm_master_req_o, - output logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tcdm_master_req_valid_o, - input logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tcdm_master_req_ready_i, - input `STRUCT_VECT(tcdm_master_resp_t, [NumGroups+NumSubGroupsPerGroup-1-1:0]) tcdm_master_resp_i, - input logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tcdm_master_resp_valid_i, - output logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tcdm_master_resp_ready_o, + output `STRUCT_VECT(tcdm_master_req_t, [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0]) tcdm_master_req_o, + output logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tcdm_master_req_valid_o, + input logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tcdm_master_req_ready_i, + input `STRUCT_VECT(tcdm_master_resp_t, [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0]) tcdm_master_resp_i, + input logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tcdm_master_resp_valid_i, + output logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tcdm_master_resp_ready_o, // TCDM slave interfaces - input `STRUCT_VECT(tcdm_slave_req_t, [NumGroups+NumSubGroupsPerGroup-1-1:0]) tcdm_slave_req_i, - input logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tcdm_slave_req_valid_i, - output logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tcdm_slave_req_ready_o, - output `STRUCT_VECT(tcdm_slave_resp_t, [NumGroups+NumSubGroupsPerGroup-1-1:0]) tcdm_slave_resp_o, - output logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tcdm_slave_resp_valid_o, - input logic [NumGroups+NumSubGroupsPerGroup-1-1:0] tcdm_slave_resp_ready_i, + input `STRUCT_VECT(tcdm_slave_req_t, [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0]) tcdm_slave_req_i, + input logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tcdm_slave_req_valid_i, + output logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tcdm_slave_req_ready_o, + output `STRUCT_VECT(tcdm_slave_resp_t, [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0]) tcdm_slave_resp_o, + output logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tcdm_slave_resp_valid_o, + input logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] tcdm_slave_resp_ready_i, // TCDM DMA interfaces input `STRUCT_PORT(tcdm_dma_req_t) tcdm_dma_req_i, input logic tcdm_dma_req_valid_i, @@ -69,10 +69,10 @@ module mempool_tile import snitch_pkg::dreq_t; import snitch_pkg::dresp_t; - typedef logic [idx_width(NumGroups)-1:0] group_id_t; + typedef logic [idx_width(NumGroupsPerCluster)-1:0] group_id_t; // Local interconnect address width - typedef logic [idx_width(NumCoresPerTile + NumGroups + NumSubGroupsPerGroup - 1)-1:0] local_req_interco_addr_t; + typedef logic [idx_width(NumCoresPerTile + NumGroupsPerCluster + NumSubGroupsPerGroup - 1)-1:0] local_req_interco_addr_t; /********************* * Control Signals * @@ -81,9 +81,9 @@ module mempool_tile `FF(wake_up_q, wake_up_i, '0, clk_i, rst_ni); // Group ID - logic [idx_width(NumGroups)-1:0] group_id; - if (NumGroups != 1) begin: gen_group_id - assign group_id = tile_id_i[$clog2(NumTiles)-1 -: $clog2(NumGroups)]; + logic [idx_width(NumGroupsPerCluster)-1:0] group_id; + if (NumGroupsPerCluster != 1) begin: gen_group_id + assign group_id = tile_id_i[$clog2(NumTilesPerCluster)-1 -: $clog2(NumGroupsPerCluster)]; end else begin: gen_group_id assign group_id = '0; end: gen_group_id @@ -92,7 +92,7 @@ module mempool_tile // SubGroup ID logic [idx_width(NumSubGroupsPerGroup)-1:0] sub_group_id; if (NumSubGroupsPerGroup != 1) begin: gen_sub_group_id - assign sub_group_id = tile_id_i[$clog2(NumTiles)-$clog2(NumGroups)-1 -: $clog2(NumSubGroupsPerGroup)]; + assign sub_group_id = tile_id_i[$clog2(NumTilesPerCluster)-$clog2(NumGroupsPerCluster)-1 -: $clog2(NumSubGroupsPerGroup)]; end else begin: gen_sub_group_id assign sub_group_id = '0; end: gen_sub_group_id @@ -562,22 +562,22 @@ module mempool_tile // These are required to break dependencies between request and response, establishing a correct // valid/ready handshake. - tcdm_master_req_t [NumGroups+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_master_req; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_master_req_valid; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_master_req_ready; - tcdm_slave_req_t [NumGroups+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_slave_req; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_slave_req_valid; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_slave_req_ready; - tcdm_slave_resp_t [NumGroups+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_slave_resp; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_slave_resp_valid; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_slave_resp_ready; - tcdm_master_resp_t [NumGroups+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_master_resp; - tile_core_id_t [NumGroups+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_master_resp_ini_sel; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_master_resp_valid; - logic [NumGroups+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_master_resp_ready; + tcdm_master_req_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_master_req; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_master_req_valid; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_master_req_ready; + tcdm_slave_req_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_slave_req; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_slave_req_valid; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_slave_req_ready; + tcdm_slave_resp_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_slave_resp; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_slave_resp_valid; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] prereg_tcdm_slave_resp_ready; + tcdm_master_resp_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_master_resp; + tile_core_id_t [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_master_resp_ini_sel; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_master_resp_valid; + logic [NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0] postreg_tcdm_master_resp_ready; // Break paths between request and response with registers - for (genvar h = 0; unsigned'(h) < NumGroups+NumSubGroupsPerGroup-1; h++) begin: gen_tcdm_registers + for (genvar h = 0; unsigned'(h) < NumGroupsPerCluster+NumSubGroupsPerGroup-1; h++) begin: gen_tcdm_registers spill_register #( .T(tcdm_master_req_t) ) i_tcdm_master_req_register ( @@ -659,7 +659,7 @@ module mempool_tile stream_xbar #( .NumInp (NumCoresPerTile ), - .NumOut (NumGroups+NumSubGroupsPerGroup-1), + .NumOut (NumGroupsPerCluster+NumSubGroupsPerGroup-1), .payload_t(tcdm_master_req_t ) ) i_remote_req_interco ( .clk_i (clk_i ), @@ -680,7 +680,7 @@ module mempool_tile ); stream_xbar #( - .NumInp (NumGroups+NumSubGroupsPerGroup-1), + .NumInp (NumGroupsPerCluster+NumSubGroupsPerGroup-1), .NumOut (NumCoresPerTile ), .payload_t(tcdm_master_resp_t ) ) i_remote_resp_interco ( @@ -712,16 +712,16 @@ module mempool_tile logic [NumCoresPerTile-1:0] local_resp_interco_ready; tcdm_slave_resp_t [NumCoresPerTile-1:0] local_resp_interco_payload; - logic [NumCoresPerTile+NumGroups+NumSubGroupsPerGroup-1-1:0][idx_width(NumBanksPerTile)-1:0] local_req_interco_tgt_sel; + logic [NumCoresPerTile+NumGroupsPerCluster+NumSubGroupsPerGroup-1-1:0][idx_width(NumBanksPerTile)-1:0] local_req_interco_tgt_sel; for (genvar j = 0; unsigned'(j) < NumCoresPerTile; j++) begin: gen_local_req_interco_tgt_sel_local assign local_req_interco_tgt_sel[j] = local_req_interco_payload[j].tgt_addr[idx_width(NumBanksPerTile)-1:0]; end: gen_local_req_interco_tgt_sel_local - for (genvar j = 0; unsigned'(j) < NumGroups+NumSubGroupsPerGroup-1; j++) begin: gen_local_req_interco_tgt_sel_remote + for (genvar j = 0; unsigned'(j) < NumGroupsPerCluster+NumSubGroupsPerGroup-1; j++) begin: gen_local_req_interco_tgt_sel_remote assign local_req_interco_tgt_sel[j + NumCoresPerTile] = postreg_tcdm_slave_req[j].tgt_addr[idx_width(NumBanksPerTile)-1:0]; end: gen_local_req_interco_tgt_sel_remote stream_xbar #( - .NumInp (NumCoresPerTile+NumGroups+NumSubGroupsPerGroup-1), + .NumInp (NumCoresPerTile+NumGroupsPerCluster+NumSubGroupsPerGroup-1), .NumOut (NumBanksPerTile ), .payload_t(tcdm_slave_req_t ) ) i_local_req_interco ( @@ -744,7 +744,7 @@ module mempool_tile stream_xbar #( .NumInp (NumBanksPerTile ), - .NumOut (NumCoresPerTile+NumGroups+NumSubGroupsPerGroup-1), + .NumOut (NumCoresPerTile+NumGroupsPerCluster+NumSubGroupsPerGroup-1), .payload_t(tcdm_slave_resp_t ) ) i_local_resp_interco ( .clk_i (clk_i ), @@ -795,7 +795,7 @@ module mempool_tile }, // Highest priority: send request through the local TCDM port '{slave_idx: TCDM_LOCAL, - mask : TCDMMask | ({idx_width(NumTiles){1'b1}} << (ByteOffset + $clog2(NumBanksPerTile))), + mask : TCDMMask | ({idx_width(NumTilesPerCluster){1'b1}} << (ByteOffset + $clog2(NumBanksPerTile))), value : TCDMBaseAddr | (tile_id_i << (ByteOffset + $clog2(NumBanksPerTile))) } }; @@ -805,25 +805,25 @@ module mempool_tile // Remove tile index from local_req_interco_addr_int, since it will not be used for routing. addr_t local_req_interco_addr_int; assign local_req_interco_payload[c].tgt_addr = - tcdm_addr_t'({local_req_interco_addr_int[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTiles) +: TCDMAddrMemWidth], // Bank address + tcdm_addr_t'({local_req_interco_addr_int[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerCluster) +: TCDMAddrMemWidth], // Bank address local_req_interco_addr_int[ByteOffset +: idx_width(NumBanksPerTile)]}); // Bank // Switch tile and bank indexes for correct upper level routing, and remove the group index addr_t prescramble_tcdm_req_tgt_addr; if (NumTilesPerGroup == 1) begin : gen_remote_req_interco_tgt_addr assign remote_req_interco[c].tgt_addr = - tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumGroups) +: TCDMAddrMemWidth], // Bank address + tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumGroupsPerCluster) +: TCDMAddrMemWidth], // Bank address prescramble_tcdm_req_tgt_addr[ByteOffset +: idx_width(NumBanksPerTile)]}); // Tile end else begin : gen_remote_req_interco_tgt_addr always_comb begin if (remote_req_interco_tgt_g_sel_tmp[c] == 'b0) begin remote_req_interco[c].tgt_addr = - tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroups) +: TCDMAddrMemWidth], // Bank address + tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroupsPerCluster) +: TCDMAddrMemWidth], // Bank address prescramble_tcdm_req_tgt_addr[ByteOffset +: idx_width(NumBanksPerTile)], // Bank prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) +: $clog2(NumTilesPerSubGroup)]}); // Tile end else begin remote_req_interco[c].tgt_addr = - tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroups) +: TCDMAddrMemWidth], // Bank address + tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroupsPerCluster) +: TCDMAddrMemWidth], // Bank address prescramble_tcdm_req_tgt_addr[ByteOffset +: idx_width(NumBanksPerTile)], // Bank prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) +: $clog2(NumTilesPerGroup)]}); // Tile end @@ -831,7 +831,7 @@ module mempool_tile end // Remote selection signal - if (NumGroups == 1) begin : gen_remote_req_interco_tgt_sel + if (NumGroupsPerCluster == 1) begin : gen_remote_req_interco_tgt_sel if (NumSubGroupsPerGroup == 1) begin : gen_const_sel assign remote_req_interco_tgt_sel[c] = 1'b0; end else begin : gen_const_sel @@ -840,9 +840,9 @@ module mempool_tile end else begin : gen_remote_req_interco_tgt_sel // Output port depends on both the target and initiator group and sub-group if (NumSubGroupsPerGroup == 1) begin : gen_remote_group_sel - assign remote_req_interco_tgt_sel[c] = (prescramble_tcdm_req_tgt_addr[ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerGroup) +: $clog2(NumGroups)]) ^ group_id; + assign remote_req_interco_tgt_sel[c] = (prescramble_tcdm_req_tgt_addr[ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerGroup) +: $clog2(NumGroupsPerCluster)]) ^ group_id; end else begin : gen_remote_group_sel - assign remote_req_interco_tgt_g_sel_tmp[c] = (prescramble_tcdm_req_tgt_addr[ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerGroup) +: $clog2(NumGroups)]) ^ group_id; + assign remote_req_interco_tgt_g_sel_tmp[c] = (prescramble_tcdm_req_tgt_addr[ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerGroup) +: $clog2(NumGroupsPerCluster)]) ^ group_id; assign remote_req_interco_tgt_sg_sel_tmp[c] = (prescramble_tcdm_req_tgt_addr[ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerSubGroup) +: $clog2(NumSubGroupsPerGroup)]) ^ sub_group_id; always_comb begin : gen_remote_sub_group_sel if (remote_req_interco_tgt_g_sel_tmp[c] == 'b0) begin: gen_local_group_sel @@ -857,26 +857,26 @@ module mempool_tile // Remove tile index from local_req_interco_addr_int, since it will not be used for routing. addr_t local_req_interco_addr_int; assign local_req_interco_payload[c].tgt_addr = - tcdm_addr_t'({local_req_interco_addr_int[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTiles) +: TCDMAddrMemWidth], // Bank address + tcdm_addr_t'({local_req_interco_addr_int[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerCluster) +: TCDMAddrMemWidth], // Bank address local_req_interco_addr_int[ByteOffset +: idx_width(NumBanksPerTile)]}); // Bank // Switch tile and bank indexes for correct upper level routing, and remove the group index addr_t prescramble_tcdm_req_tgt_addr; if (NumTilesPerGroup == 1) begin : gen_remote_req_interco_tgt_addr assign remote_req_interco[c].tgt_addr = - tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumGroups) +: TCDMAddrMemWidth], // Bank address + tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumGroupsPerCluster) +: TCDMAddrMemWidth], // Bank address prescramble_tcdm_req_tgt_addr[ByteOffset +: idx_width(NumBanksPerTile)]}); // Tile end else begin : gen_remote_req_interco_tgt_addr assign remote_req_interco[c].tgt_addr = - tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroups) +: TCDMAddrMemWidth], // Bank address + tcdm_addr_t'({prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) + $clog2(NumTilesPerGroup) + $clog2(NumGroupsPerCluster) +: TCDMAddrMemWidth], // Bank address prescramble_tcdm_req_tgt_addr[ByteOffset +: idx_width(NumBanksPerTile)], // Bank prescramble_tcdm_req_tgt_addr[ByteOffset + idx_width(NumBanksPerTile) +: $clog2(NumTilesPerGroup)]}); // Tile end - if (NumGroups == 1) begin : gen_remote_req_interco_tgt_sel + if (NumGroupsPerCluster == 1) begin : gen_remote_req_interco_tgt_sel assign remote_req_interco_tgt_sel[c] = 1'b0; end else begin : gen_remote_req_interco_tgt_sel // Output port depends on both the target and initiator group - assign remote_req_interco_tgt_sel[c] = (prescramble_tcdm_req_tgt_addr[ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerGroup) +: $clog2(NumGroups)]) ^ group_id; + assign remote_req_interco_tgt_sel[c] = (prescramble_tcdm_req_tgt_addr[ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerGroup) +: $clog2(NumGroupsPerCluster)]) ^ group_id; end `endif @@ -891,12 +891,13 @@ module mempool_tile // Scramble address before entering TCDM shim for sequential+interleaved memory map addr_t snitch_data_qaddr_scrambled; address_scrambler #( - .AddrWidth (AddrWidth ), - .ByteOffset (ByteOffset ), - .NumTiles (NumTiles ), - .NumBanksPerTile (NumBanksPerTile ), - .Bypass (0 ), - .SeqMemSizePerTile (SeqMemSizePerTile) + .AddrWidth (AddrWidth ), + .ByteOffset (ByteOffset ), + .NumTiles (NumTilesPerCluster), + .NumBanksPerTile (NumBanksPerTile ), + .Bypass (0 ), + .SeqMemSizePerTile (SeqMemSizePerTile ), + .BaseAddr (TCDMBaseAddr ) ) i_address_scrambler ( .address_i (snitch_data_qaddr[c] ), .address_o (snitch_data_qaddr_scrambled) diff --git a/hardware/src/tcdm_adapter.sv b/hardware/src/tcdm_adapter.sv index 72c3cb2c3..9001096d3 100644 --- a/hardware/src/tcdm_adapter.sv +++ b/hardware/src/tcdm_adapter.sv @@ -45,8 +45,8 @@ module tcdm_adapter #( input logic [DataWidth-1:0] out_rdata_i // Read data ); - import mempool_pkg::NumCores; - import mempool_pkg::NumGroups; + import mempool_pkg::NumCoresPerCluster; + import mempool_pkg::NumGroupsPerCluster; import mempool_pkg::NumCoresPerTile; import cf_math_pkg::idx_width; @@ -135,8 +135,8 @@ module tcdm_adapter #( .pop_i (pop_resp && !rdata_empty) ); - localparam int unsigned CoreIdWidth = idx_width(NumCores); - localparam int unsigned IniAddrWidth = idx_width(NumCoresPerTile + NumGroups); + localparam int unsigned CoreIdWidth = idx_width(NumCoresPerCluster); + localparam int unsigned IniAddrWidth = idx_width(NumCoresPerTile + NumGroupsPerCluster); logic sc_successful_d, sc_successful_q; logic sc_q; From e9b5c49ee3339aced64f08c68775400faa1595de Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 8 Apr 2024 15:24:42 +0200 Subject: [PATCH 10/14] [software] Fix stack initialization for multi-cluster MemPool --- software/runtime/crt0.S | 9 ++++++++- software/runtime/runtime.mk | 6 ++++++ software/runtime/synchronization.c | 17 ++++++++--------- 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/software/runtime/crt0.S b/software/runtime/crt0.S index 4de3d2b70..0871bb674 100644 --- a/software/runtime/crt0.S +++ b/software/runtime/crt0.S @@ -57,9 +57,16 @@ _reset_vector: li x31, 0 la sp, __stack_start // load stack csrr a0, mhartid // get hart id + // Calculate L1 offset for our cluster + srli t1, a0, LOG2_NUM_CORES_PER_CLUSTER // cluster_id = id / NUM_CORES_PER_CLUSTER + slli t1, t1, LOG2_L1_SIZE_PER_CLUSTER // cluster_offset = cluster_id * NUM_CORES_PER_CLUSTER * BANKING_FACTOR * BANK_SIZE // Calculate sequential region offset for our tile srli t0, a0, LOG2_NUM_CORES_PER_TILE // tile_id = id / NUM_CORES_PER_TILE - slli t0, t0, (LOG2_NUM_CORES_PER_TILE+LOG2_SEQ_MEM_SIZE) // tile_offset = tile_id * NUM_CORES_PER_TILE * SEQ_MEM_SIZE + li t2, NUM_TILES_PER_CLUSTER // NUM_TILES_PER_CLUSTER + addi t2, t2, -1 // Create mask for NUM_TILES_PER_CLUSTER + and t0, t0, t2 // tile_cluster_id = tile_id % NUM_TILES_PER_CLUSTER + slli t0, t0, (LOG2_NUM_CORES_PER_TILE+LOG2_SEQ_MEM_SIZE) // tile_offset = tile_cluster_id * NUM_CORES_PER_TILE * SEQ_MEM_SIZE + add t0, t0, t1 // offset = cluster_offset + tile_offset // Calculate stack offset within tile li t1, NUM_CORES_PER_TILE // NUM_CORES_PER_TILE addi t1, t1, -1 // Create mask for NUM_CORES_PER_TILE diff --git a/software/runtime/runtime.mk b/software/runtime/runtime.mk index 69d309158..3dc0666bc 100644 --- a/software/runtime/runtime.mk +++ b/software/runtime/runtime.mk @@ -89,13 +89,19 @@ RISCV_STRIP ?= $(RISCV_PREFIX)strip DEFINES += -DPRINTF_DISABLE_SUPPORT_FLOAT -DPRINTF_DISABLE_SUPPORT_LONG_LONG -DPRINTF_DISABLE_SUPPORT_PTRDIFF_T DEFINES += -DNUM_CORES=$(num_cores) DEFINES += -DNUM_GROUPS=$(num_groups) +DEFINES += -DNUM_CLUSTERS=$(num_clusters) DEFINES += -DNUM_CORES_PER_TILE=$(num_cores_per_tile) DEFINES += -DBANKING_FACTOR=$(banking_factor) +DEFINES += -DNUM_CORES_PER_CLUSTER=$(shell awk 'BEGIN{print $(num_cores)/$(num_clusters)}') +DEFINES += -DNUM_TILES_PER_CLUSTER=$(shell awk 'BEGIN{print ($(num_cores)/$(num_clusters))/$(num_cores_per_tile)}') DEFINES += -DNUM_CORES_PER_GROUP=$(shell awk 'BEGIN{print $(num_cores)/$(num_groups)}') DEFINES += -DNUM_TILES_PER_GROUP=$(shell awk 'BEGIN{print ($(num_cores)/$(num_groups))/$(num_cores_per_tile)}') DEFINES += -DLOG2_NUM_CORES_PER_TILE=$(shell awk 'BEGIN{print log($(num_cores_per_tile))/log(2)}') +DEFINES += -DLOG2_NUM_CORES_PER_GROUP=$(shell awk 'BEGIN{print log($(num_cores)/$(num_groups))/log(2)}') +DEFINES += -DLOG2_NUM_CORES_PER_CLUSTER=$(shell awk 'BEGIN{print log($(num_cores)/$(num_clusters))/log(2)}') DEFINES += -DBOOT_ADDR=$(boot_addr) DEFINES += -DL1_BANK_SIZE=$(l1_bank_size) +DEFINES += -DLOG2_L1_SIZE_PER_CLUSTER=$(shell awk 'BEGIN{print log($(l1_bank_size)*$(banking_factor)*$(num_cores)/$(num_clusters))/log(2)}') DEFINES += -DL2_BASE=$(l2_base) DEFINES += -DL2_SIZE=$(l2_size) DEFINES += -DSEQ_MEM_SIZE=$(seq_mem_size) diff --git a/software/runtime/synchronization.c b/software/runtime/synchronization.c index 88627b4d6..97500a699 100644 --- a/software/runtime/synchronization.c +++ b/software/runtime/synchronization.c @@ -10,13 +10,18 @@ #include "runtime.h" #include "synchronization.h" -uint32_t volatile barrier __attribute__((section(".l1"))); +uint32_t volatile barrier __attribute__((section(".l2"))); uint32_t volatile log_barrier[NUM_CORES * 4] - __attribute__((aligned(NUM_CORES * 4), section(".l1"))); + __attribute__((aligned(NUM_CORES * 4), section(".l2"))); uint32_t volatile partial_barrier[NUM_CORES * 4] - __attribute__((aligned(NUM_CORES * 4), section(".l1"))); + __attribute__((aligned(NUM_CORES * 4), section(".l2"))); void mempool_barrier_init(uint32_t core_id) { + // Initialize log-barriers synch variables in parallel + for (uint32_t i = core_id; i < NUM_CORES * 4; i += NUM_CORES) { + log_barrier[i] = 0; + partial_barrier[i] = 0; + } if (core_id == 0) { // Initialize the barrier barrier = 0; @@ -25,12 +30,6 @@ void mempool_barrier_init(uint32_t core_id) { } else { mempool_wfi(); } - // Initialize log-barriers synch variables in parallel - for (uint32_t i = core_id; i < NUM_CORES * 4; i += NUM_CORES) { - log_barrier[i] = 0; - partial_barrier[i] = 0; - } - mempool_barrier(NUM_CORES); } void mempool_barrier(uint32_t num_cores) { From e9573543236360e0493dba1f3e6b393fd75e014b Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 10 Jun 2024 12:19:51 +0200 Subject: [PATCH 11/14] [hardware] Extend control register --- hardware/Makefile | 4 + .../control_registers/control_registers.hjson | 9 +- .../control_registers_reg_pkg.sv | 267 +- .../control_registers_reg_top.sv | 2221 ++++++++++++++++- hardware/src/ctrl_registers.sv | 14 + software/runtime/control_registers.h | 203 +- 6 files changed, 2600 insertions(+), 118 deletions(-) diff --git a/hardware/Makefile b/hardware/Makefile index 3ce1ea784..4f373aad1 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -414,6 +414,10 @@ src/bootrom.sv: $(MEMPOOL_DIR)/software/runtime/bootrom.img $(config_mk) Makefil $(MEMPOOL_DIR)/software/runtime/bootrom.img: make -C $(MEMPOOL_DIR)/software runtime/bootrom.img +# Control Registers +src/control_registers/control_registers_reg_top.sv: src/control_registers/control_registers.hjson + make -C src/control_registers all + # Clean targets .PHONY: clean clean-dasm clean-trace update_opcodes diff --git a/hardware/src/control_registers/control_registers.hjson b/hardware/src/control_registers/control_registers.hjson index dc1aebe42..486097f02 100644 --- a/hardware/src/control_registers/control_registers.hjson +++ b/hardware/src/control_registers/control_registers.hjson @@ -20,7 +20,7 @@ { name: "MAX_NumGroups", desc: "Maximum number of groups that we support in any configuration", type: "int", - default: "8" + default: "64" } ], regwidth: 32 @@ -57,6 +57,13 @@ hwqe: "true" fields: [{ bits: "31:0" }] }, + { name: "wake_up_cluster" + desc: "Wake Up Cluster Register" + swaccess: "wo" + hwaccess: "hro" + hwqe: "true" + fields: [{ bits: "31:0" }] + }, { name: "tcdm_start_address" desc: "TCDM Start Address Register" swaccess: "ro" diff --git a/hardware/src/control_registers/control_registers_reg_pkg.sv b/hardware/src/control_registers/control_registers_reg_pkg.sv index 3a44033a3..25fad6e7b 100644 --- a/hardware/src/control_registers/control_registers_reg_pkg.sv +++ b/hardware/src/control_registers/control_registers_reg_pkg.sv @@ -8,10 +8,10 @@ package control_registers_reg_pkg; // Param list parameter int ROCacheNumAddrRules = 4; - parameter int MAX_NumGroups = 8; + parameter int MAX_NumGroups = 64; // Address widths within the block - parameter int BlockAw = 7; + parameter int BlockAw = 9; //////////////////////////// // Typedefs for registers // @@ -36,6 +36,11 @@ package control_registers_reg_pkg; logic qe; } control_registers_reg2hw_wake_up_group_reg_t; + typedef struct packed { + logic [31:0] q; + logic qe; + } control_registers_reg2hw_wake_up_cluster_reg_t; + typedef struct packed { logic [31:0] q; } control_registers_reg2hw_ro_cache_enable_reg_t; @@ -76,10 +81,11 @@ package control_registers_reg_pkg; // Register -> HW type typedef struct packed { - control_registers_reg2hw_eoc_reg_t eoc; // [689:658] - control_registers_reg2hw_wake_up_reg_t wake_up; // [657:625] - control_registers_reg2hw_wake_up_tile_mreg_t [7:0] wake_up_tile; // [624:361] - control_registers_reg2hw_wake_up_group_reg_t wake_up_group; // [360:328] + control_registers_reg2hw_eoc_reg_t eoc; // [2570:2539] + control_registers_reg2hw_wake_up_reg_t wake_up; // [2538:2506] + control_registers_reg2hw_wake_up_tile_mreg_t [63:0] wake_up_tile; // [2505:394] + control_registers_reg2hw_wake_up_group_reg_t wake_up_group; // [393:361] + control_registers_reg2hw_wake_up_cluster_reg_t wake_up_cluster; // [360:328] control_registers_reg2hw_ro_cache_enable_reg_t ro_cache_enable; // [327:296] control_registers_reg2hw_ro_cache_flush_reg_t ro_cache_flush; // [295:264] control_registers_reg2hw_ro_cache_start_mreg_t [3:0] ro_cache_start; // [263:132] @@ -96,30 +102,87 @@ package control_registers_reg_pkg; } control_registers_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_EOC_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_0_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_1_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_2_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_3_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_4_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_5_OFFSET = 7'h 1c; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_6_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_7_OFFSET = 7'h 24; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_GROUP_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_TCDM_START_ADDRESS_OFFSET = 7'h 2c; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_TCDM_END_ADDRESS_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_NR_CORES_REG_OFFSET = 7'h 34; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_ENABLE_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_FLUSH_OFFSET = 7'h 3c; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_0_OFFSET = 7'h 40; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_1_OFFSET = 7'h 44; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_2_OFFSET = 7'h 48; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_3_OFFSET = 7'h 4c; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_0_OFFSET = 7'h 50; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_1_OFFSET = 7'h 54; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_2_OFFSET = 7'h 58; - parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_3_OFFSET = 7'h 5c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_EOC_OFFSET = 9'h 0; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_OFFSET = 9'h 4; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_0_OFFSET = 9'h 8; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_1_OFFSET = 9'h c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_2_OFFSET = 9'h 10; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_3_OFFSET = 9'h 14; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_4_OFFSET = 9'h 18; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_5_OFFSET = 9'h 1c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_6_OFFSET = 9'h 20; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_7_OFFSET = 9'h 24; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_8_OFFSET = 9'h 28; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_9_OFFSET = 9'h 2c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_10_OFFSET = 9'h 30; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_11_OFFSET = 9'h 34; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_12_OFFSET = 9'h 38; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_13_OFFSET = 9'h 3c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_14_OFFSET = 9'h 40; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_15_OFFSET = 9'h 44; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_16_OFFSET = 9'h 48; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_17_OFFSET = 9'h 4c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_18_OFFSET = 9'h 50; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_19_OFFSET = 9'h 54; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_20_OFFSET = 9'h 58; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_21_OFFSET = 9'h 5c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_22_OFFSET = 9'h 60; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_23_OFFSET = 9'h 64; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_24_OFFSET = 9'h 68; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_25_OFFSET = 9'h 6c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_26_OFFSET = 9'h 70; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_27_OFFSET = 9'h 74; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_28_OFFSET = 9'h 78; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_29_OFFSET = 9'h 7c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_30_OFFSET = 9'h 80; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_31_OFFSET = 9'h 84; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_32_OFFSET = 9'h 88; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_33_OFFSET = 9'h 8c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_34_OFFSET = 9'h 90; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_35_OFFSET = 9'h 94; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_36_OFFSET = 9'h 98; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_37_OFFSET = 9'h 9c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_38_OFFSET = 9'h a0; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_39_OFFSET = 9'h a4; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_40_OFFSET = 9'h a8; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_41_OFFSET = 9'h ac; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_42_OFFSET = 9'h b0; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_43_OFFSET = 9'h b4; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_44_OFFSET = 9'h b8; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_45_OFFSET = 9'h bc; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_46_OFFSET = 9'h c0; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_47_OFFSET = 9'h c4; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_48_OFFSET = 9'h c8; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_49_OFFSET = 9'h cc; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_50_OFFSET = 9'h d0; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_51_OFFSET = 9'h d4; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_52_OFFSET = 9'h d8; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_53_OFFSET = 9'h dc; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_54_OFFSET = 9'h e0; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_55_OFFSET = 9'h e4; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_56_OFFSET = 9'h e8; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_57_OFFSET = 9'h ec; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_58_OFFSET = 9'h f0; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_59_OFFSET = 9'h f4; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_60_OFFSET = 9'h f8; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_61_OFFSET = 9'h fc; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_62_OFFSET = 9'h 100; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_TILE_63_OFFSET = 9'h 104; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_GROUP_OFFSET = 9'h 108; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_WAKE_UP_CLUSTER_OFFSET = 9'h 10c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_TCDM_START_ADDRESS_OFFSET = 9'h 110; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_TCDM_END_ADDRESS_OFFSET = 9'h 114; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_NR_CORES_REG_OFFSET = 9'h 118; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_ENABLE_OFFSET = 9'h 11c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_FLUSH_OFFSET = 9'h 120; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_0_OFFSET = 9'h 124; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_1_OFFSET = 9'h 128; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_2_OFFSET = 9'h 12c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_START_3_OFFSET = 9'h 130; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_0_OFFSET = 9'h 134; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_1_OFFSET = 9'h 138; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_2_OFFSET = 9'h 13c; + parameter logic [BlockAw-1:0] CONTROL_REGISTERS_RO_CACHE_END_3_OFFSET = 9'h 140; // Reset values for hwext registers and their fields parameter logic [31:0] CONTROL_REGISTERS_TCDM_START_ADDRESS_RESVAL = 32'h 0; @@ -146,7 +209,64 @@ package control_registers_reg_pkg; CONTROL_REGISTERS_WAKE_UP_TILE_5, CONTROL_REGISTERS_WAKE_UP_TILE_6, CONTROL_REGISTERS_WAKE_UP_TILE_7, + CONTROL_REGISTERS_WAKE_UP_TILE_8, + CONTROL_REGISTERS_WAKE_UP_TILE_9, + CONTROL_REGISTERS_WAKE_UP_TILE_10, + CONTROL_REGISTERS_WAKE_UP_TILE_11, + CONTROL_REGISTERS_WAKE_UP_TILE_12, + CONTROL_REGISTERS_WAKE_UP_TILE_13, + CONTROL_REGISTERS_WAKE_UP_TILE_14, + CONTROL_REGISTERS_WAKE_UP_TILE_15, + CONTROL_REGISTERS_WAKE_UP_TILE_16, + CONTROL_REGISTERS_WAKE_UP_TILE_17, + CONTROL_REGISTERS_WAKE_UP_TILE_18, + CONTROL_REGISTERS_WAKE_UP_TILE_19, + CONTROL_REGISTERS_WAKE_UP_TILE_20, + CONTROL_REGISTERS_WAKE_UP_TILE_21, + CONTROL_REGISTERS_WAKE_UP_TILE_22, + CONTROL_REGISTERS_WAKE_UP_TILE_23, + CONTROL_REGISTERS_WAKE_UP_TILE_24, + CONTROL_REGISTERS_WAKE_UP_TILE_25, + CONTROL_REGISTERS_WAKE_UP_TILE_26, + CONTROL_REGISTERS_WAKE_UP_TILE_27, + CONTROL_REGISTERS_WAKE_UP_TILE_28, + CONTROL_REGISTERS_WAKE_UP_TILE_29, + CONTROL_REGISTERS_WAKE_UP_TILE_30, + CONTROL_REGISTERS_WAKE_UP_TILE_31, + CONTROL_REGISTERS_WAKE_UP_TILE_32, + CONTROL_REGISTERS_WAKE_UP_TILE_33, + CONTROL_REGISTERS_WAKE_UP_TILE_34, + CONTROL_REGISTERS_WAKE_UP_TILE_35, + CONTROL_REGISTERS_WAKE_UP_TILE_36, + CONTROL_REGISTERS_WAKE_UP_TILE_37, + CONTROL_REGISTERS_WAKE_UP_TILE_38, + CONTROL_REGISTERS_WAKE_UP_TILE_39, + CONTROL_REGISTERS_WAKE_UP_TILE_40, + CONTROL_REGISTERS_WAKE_UP_TILE_41, + CONTROL_REGISTERS_WAKE_UP_TILE_42, + CONTROL_REGISTERS_WAKE_UP_TILE_43, + CONTROL_REGISTERS_WAKE_UP_TILE_44, + CONTROL_REGISTERS_WAKE_UP_TILE_45, + CONTROL_REGISTERS_WAKE_UP_TILE_46, + CONTROL_REGISTERS_WAKE_UP_TILE_47, + CONTROL_REGISTERS_WAKE_UP_TILE_48, + CONTROL_REGISTERS_WAKE_UP_TILE_49, + CONTROL_REGISTERS_WAKE_UP_TILE_50, + CONTROL_REGISTERS_WAKE_UP_TILE_51, + CONTROL_REGISTERS_WAKE_UP_TILE_52, + CONTROL_REGISTERS_WAKE_UP_TILE_53, + CONTROL_REGISTERS_WAKE_UP_TILE_54, + CONTROL_REGISTERS_WAKE_UP_TILE_55, + CONTROL_REGISTERS_WAKE_UP_TILE_56, + CONTROL_REGISTERS_WAKE_UP_TILE_57, + CONTROL_REGISTERS_WAKE_UP_TILE_58, + CONTROL_REGISTERS_WAKE_UP_TILE_59, + CONTROL_REGISTERS_WAKE_UP_TILE_60, + CONTROL_REGISTERS_WAKE_UP_TILE_61, + CONTROL_REGISTERS_WAKE_UP_TILE_62, + CONTROL_REGISTERS_WAKE_UP_TILE_63, CONTROL_REGISTERS_WAKE_UP_GROUP, + CONTROL_REGISTERS_WAKE_UP_CLUSTER, CONTROL_REGISTERS_TCDM_START_ADDRESS, CONTROL_REGISTERS_TCDM_END_ADDRESS, CONTROL_REGISTERS_NR_CORES_REG, @@ -163,7 +283,7 @@ package control_registers_reg_pkg; } control_registers_id_e; // Register width information to check illegal writes - parameter logic [3:0] CONTROL_REGISTERS_PERMIT [24] = '{ + parameter logic [3:0] CONTROL_REGISTERS_PERMIT [81] = '{ 4'b 1111, // index[ 0] CONTROL_REGISTERS_EOC 4'b 1111, // index[ 1] CONTROL_REGISTERS_WAKE_UP 4'b 1111, // index[ 2] CONTROL_REGISTERS_WAKE_UP_TILE_0 @@ -174,20 +294,77 @@ package control_registers_reg_pkg; 4'b 1111, // index[ 7] CONTROL_REGISTERS_WAKE_UP_TILE_5 4'b 1111, // index[ 8] CONTROL_REGISTERS_WAKE_UP_TILE_6 4'b 1111, // index[ 9] CONTROL_REGISTERS_WAKE_UP_TILE_7 - 4'b 1111, // index[10] CONTROL_REGISTERS_WAKE_UP_GROUP - 4'b 1111, // index[11] CONTROL_REGISTERS_TCDM_START_ADDRESS - 4'b 1111, // index[12] CONTROL_REGISTERS_TCDM_END_ADDRESS - 4'b 1111, // index[13] CONTROL_REGISTERS_NR_CORES_REG - 4'b 1111, // index[14] CONTROL_REGISTERS_RO_CACHE_ENABLE - 4'b 1111, // index[15] CONTROL_REGISTERS_RO_CACHE_FLUSH - 4'b 1111, // index[16] CONTROL_REGISTERS_RO_CACHE_START_0 - 4'b 1111, // index[17] CONTROL_REGISTERS_RO_CACHE_START_1 - 4'b 1111, // index[18] CONTROL_REGISTERS_RO_CACHE_START_2 - 4'b 1111, // index[19] CONTROL_REGISTERS_RO_CACHE_START_3 - 4'b 1111, // index[20] CONTROL_REGISTERS_RO_CACHE_END_0 - 4'b 1111, // index[21] CONTROL_REGISTERS_RO_CACHE_END_1 - 4'b 1111, // index[22] CONTROL_REGISTERS_RO_CACHE_END_2 - 4'b 1111 // index[23] CONTROL_REGISTERS_RO_CACHE_END_3 + 4'b 1111, // index[10] CONTROL_REGISTERS_WAKE_UP_TILE_8 + 4'b 1111, // index[11] CONTROL_REGISTERS_WAKE_UP_TILE_9 + 4'b 1111, // index[12] CONTROL_REGISTERS_WAKE_UP_TILE_10 + 4'b 1111, // index[13] CONTROL_REGISTERS_WAKE_UP_TILE_11 + 4'b 1111, // index[14] CONTROL_REGISTERS_WAKE_UP_TILE_12 + 4'b 1111, // index[15] CONTROL_REGISTERS_WAKE_UP_TILE_13 + 4'b 1111, // index[16] CONTROL_REGISTERS_WAKE_UP_TILE_14 + 4'b 1111, // index[17] CONTROL_REGISTERS_WAKE_UP_TILE_15 + 4'b 1111, // index[18] CONTROL_REGISTERS_WAKE_UP_TILE_16 + 4'b 1111, // index[19] CONTROL_REGISTERS_WAKE_UP_TILE_17 + 4'b 1111, // index[20] CONTROL_REGISTERS_WAKE_UP_TILE_18 + 4'b 1111, // index[21] CONTROL_REGISTERS_WAKE_UP_TILE_19 + 4'b 1111, // index[22] CONTROL_REGISTERS_WAKE_UP_TILE_20 + 4'b 1111, // index[23] CONTROL_REGISTERS_WAKE_UP_TILE_21 + 4'b 1111, // index[24] CONTROL_REGISTERS_WAKE_UP_TILE_22 + 4'b 1111, // index[25] CONTROL_REGISTERS_WAKE_UP_TILE_23 + 4'b 1111, // index[26] CONTROL_REGISTERS_WAKE_UP_TILE_24 + 4'b 1111, // index[27] CONTROL_REGISTERS_WAKE_UP_TILE_25 + 4'b 1111, // index[28] CONTROL_REGISTERS_WAKE_UP_TILE_26 + 4'b 1111, // index[29] CONTROL_REGISTERS_WAKE_UP_TILE_27 + 4'b 1111, // index[30] CONTROL_REGISTERS_WAKE_UP_TILE_28 + 4'b 1111, // index[31] CONTROL_REGISTERS_WAKE_UP_TILE_29 + 4'b 1111, // index[32] CONTROL_REGISTERS_WAKE_UP_TILE_30 + 4'b 1111, // index[33] CONTROL_REGISTERS_WAKE_UP_TILE_31 + 4'b 1111, // index[34] CONTROL_REGISTERS_WAKE_UP_TILE_32 + 4'b 1111, // index[35] CONTROL_REGISTERS_WAKE_UP_TILE_33 + 4'b 1111, // index[36] CONTROL_REGISTERS_WAKE_UP_TILE_34 + 4'b 1111, // index[37] CONTROL_REGISTERS_WAKE_UP_TILE_35 + 4'b 1111, // index[38] CONTROL_REGISTERS_WAKE_UP_TILE_36 + 4'b 1111, // index[39] CONTROL_REGISTERS_WAKE_UP_TILE_37 + 4'b 1111, // index[40] CONTROL_REGISTERS_WAKE_UP_TILE_38 + 4'b 1111, // index[41] CONTROL_REGISTERS_WAKE_UP_TILE_39 + 4'b 1111, // index[42] CONTROL_REGISTERS_WAKE_UP_TILE_40 + 4'b 1111, // index[43] CONTROL_REGISTERS_WAKE_UP_TILE_41 + 4'b 1111, // index[44] CONTROL_REGISTERS_WAKE_UP_TILE_42 + 4'b 1111, // index[45] CONTROL_REGISTERS_WAKE_UP_TILE_43 + 4'b 1111, // index[46] CONTROL_REGISTERS_WAKE_UP_TILE_44 + 4'b 1111, // index[47] CONTROL_REGISTERS_WAKE_UP_TILE_45 + 4'b 1111, // index[48] CONTROL_REGISTERS_WAKE_UP_TILE_46 + 4'b 1111, // index[49] CONTROL_REGISTERS_WAKE_UP_TILE_47 + 4'b 1111, // index[50] CONTROL_REGISTERS_WAKE_UP_TILE_48 + 4'b 1111, // index[51] CONTROL_REGISTERS_WAKE_UP_TILE_49 + 4'b 1111, // index[52] CONTROL_REGISTERS_WAKE_UP_TILE_50 + 4'b 1111, // index[53] CONTROL_REGISTERS_WAKE_UP_TILE_51 + 4'b 1111, // index[54] CONTROL_REGISTERS_WAKE_UP_TILE_52 + 4'b 1111, // index[55] CONTROL_REGISTERS_WAKE_UP_TILE_53 + 4'b 1111, // index[56] CONTROL_REGISTERS_WAKE_UP_TILE_54 + 4'b 1111, // index[57] CONTROL_REGISTERS_WAKE_UP_TILE_55 + 4'b 1111, // index[58] CONTROL_REGISTERS_WAKE_UP_TILE_56 + 4'b 1111, // index[59] CONTROL_REGISTERS_WAKE_UP_TILE_57 + 4'b 1111, // index[60] CONTROL_REGISTERS_WAKE_UP_TILE_58 + 4'b 1111, // index[61] CONTROL_REGISTERS_WAKE_UP_TILE_59 + 4'b 1111, // index[62] CONTROL_REGISTERS_WAKE_UP_TILE_60 + 4'b 1111, // index[63] CONTROL_REGISTERS_WAKE_UP_TILE_61 + 4'b 1111, // index[64] CONTROL_REGISTERS_WAKE_UP_TILE_62 + 4'b 1111, // index[65] CONTROL_REGISTERS_WAKE_UP_TILE_63 + 4'b 1111, // index[66] CONTROL_REGISTERS_WAKE_UP_GROUP + 4'b 1111, // index[67] CONTROL_REGISTERS_WAKE_UP_CLUSTER + 4'b 1111, // index[68] CONTROL_REGISTERS_TCDM_START_ADDRESS + 4'b 1111, // index[69] CONTROL_REGISTERS_TCDM_END_ADDRESS + 4'b 1111, // index[70] CONTROL_REGISTERS_NR_CORES_REG + 4'b 1111, // index[71] CONTROL_REGISTERS_RO_CACHE_ENABLE + 4'b 1111, // index[72] CONTROL_REGISTERS_RO_CACHE_FLUSH + 4'b 1111, // index[73] CONTROL_REGISTERS_RO_CACHE_START_0 + 4'b 1111, // index[74] CONTROL_REGISTERS_RO_CACHE_START_1 + 4'b 1111, // index[75] CONTROL_REGISTERS_RO_CACHE_START_2 + 4'b 1111, // index[76] CONTROL_REGISTERS_RO_CACHE_START_3 + 4'b 1111, // index[77] CONTROL_REGISTERS_RO_CACHE_END_0 + 4'b 1111, // index[78] CONTROL_REGISTERS_RO_CACHE_END_1 + 4'b 1111, // index[79] CONTROL_REGISTERS_RO_CACHE_END_2 + 4'b 1111 // index[80] CONTROL_REGISTERS_RO_CACHE_END_3 }; endpackage diff --git a/hardware/src/control_registers/control_registers_reg_top.sv b/hardware/src/control_registers/control_registers_reg_top.sv index 76e9e07cb..31b8f562a 100644 --- a/hardware/src/control_registers/control_registers_reg_top.sv +++ b/hardware/src/control_registers/control_registers_reg_top.sv @@ -10,7 +10,7 @@ module control_registers_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 7 + parameter int AW = 9 ) ( input logic clk_i, input logic rst_ni, @@ -89,8 +89,122 @@ module control_registers_reg_top #( logic wake_up_tile_6_we; logic [31:0] wake_up_tile_7_wd; logic wake_up_tile_7_we; + logic [31:0] wake_up_tile_8_wd; + logic wake_up_tile_8_we; + logic [31:0] wake_up_tile_9_wd; + logic wake_up_tile_9_we; + logic [31:0] wake_up_tile_10_wd; + logic wake_up_tile_10_we; + logic [31:0] wake_up_tile_11_wd; + logic wake_up_tile_11_we; + logic [31:0] wake_up_tile_12_wd; + logic wake_up_tile_12_we; + logic [31:0] wake_up_tile_13_wd; + logic wake_up_tile_13_we; + logic [31:0] wake_up_tile_14_wd; + logic wake_up_tile_14_we; + logic [31:0] wake_up_tile_15_wd; + logic wake_up_tile_15_we; + logic [31:0] wake_up_tile_16_wd; + logic wake_up_tile_16_we; + logic [31:0] wake_up_tile_17_wd; + logic wake_up_tile_17_we; + logic [31:0] wake_up_tile_18_wd; + logic wake_up_tile_18_we; + logic [31:0] wake_up_tile_19_wd; + logic wake_up_tile_19_we; + logic [31:0] wake_up_tile_20_wd; + logic wake_up_tile_20_we; + logic [31:0] wake_up_tile_21_wd; + logic wake_up_tile_21_we; + logic [31:0] wake_up_tile_22_wd; + logic wake_up_tile_22_we; + logic [31:0] wake_up_tile_23_wd; + logic wake_up_tile_23_we; + logic [31:0] wake_up_tile_24_wd; + logic wake_up_tile_24_we; + logic [31:0] wake_up_tile_25_wd; + logic wake_up_tile_25_we; + logic [31:0] wake_up_tile_26_wd; + logic wake_up_tile_26_we; + logic [31:0] wake_up_tile_27_wd; + logic wake_up_tile_27_we; + logic [31:0] wake_up_tile_28_wd; + logic wake_up_tile_28_we; + logic [31:0] wake_up_tile_29_wd; + logic wake_up_tile_29_we; + logic [31:0] wake_up_tile_30_wd; + logic wake_up_tile_30_we; + logic [31:0] wake_up_tile_31_wd; + logic wake_up_tile_31_we; + logic [31:0] wake_up_tile_32_wd; + logic wake_up_tile_32_we; + logic [31:0] wake_up_tile_33_wd; + logic wake_up_tile_33_we; + logic [31:0] wake_up_tile_34_wd; + logic wake_up_tile_34_we; + logic [31:0] wake_up_tile_35_wd; + logic wake_up_tile_35_we; + logic [31:0] wake_up_tile_36_wd; + logic wake_up_tile_36_we; + logic [31:0] wake_up_tile_37_wd; + logic wake_up_tile_37_we; + logic [31:0] wake_up_tile_38_wd; + logic wake_up_tile_38_we; + logic [31:0] wake_up_tile_39_wd; + logic wake_up_tile_39_we; + logic [31:0] wake_up_tile_40_wd; + logic wake_up_tile_40_we; + logic [31:0] wake_up_tile_41_wd; + logic wake_up_tile_41_we; + logic [31:0] wake_up_tile_42_wd; + logic wake_up_tile_42_we; + logic [31:0] wake_up_tile_43_wd; + logic wake_up_tile_43_we; + logic [31:0] wake_up_tile_44_wd; + logic wake_up_tile_44_we; + logic [31:0] wake_up_tile_45_wd; + logic wake_up_tile_45_we; + logic [31:0] wake_up_tile_46_wd; + logic wake_up_tile_46_we; + logic [31:0] wake_up_tile_47_wd; + logic wake_up_tile_47_we; + logic [31:0] wake_up_tile_48_wd; + logic wake_up_tile_48_we; + logic [31:0] wake_up_tile_49_wd; + logic wake_up_tile_49_we; + logic [31:0] wake_up_tile_50_wd; + logic wake_up_tile_50_we; + logic [31:0] wake_up_tile_51_wd; + logic wake_up_tile_51_we; + logic [31:0] wake_up_tile_52_wd; + logic wake_up_tile_52_we; + logic [31:0] wake_up_tile_53_wd; + logic wake_up_tile_53_we; + logic [31:0] wake_up_tile_54_wd; + logic wake_up_tile_54_we; + logic [31:0] wake_up_tile_55_wd; + logic wake_up_tile_55_we; + logic [31:0] wake_up_tile_56_wd; + logic wake_up_tile_56_we; + logic [31:0] wake_up_tile_57_wd; + logic wake_up_tile_57_we; + logic [31:0] wake_up_tile_58_wd; + logic wake_up_tile_58_we; + logic [31:0] wake_up_tile_59_wd; + logic wake_up_tile_59_we; + logic [31:0] wake_up_tile_60_wd; + logic wake_up_tile_60_we; + logic [31:0] wake_up_tile_61_wd; + logic wake_up_tile_61_we; + logic [31:0] wake_up_tile_62_wd; + logic wake_up_tile_62_we; + logic [31:0] wake_up_tile_63_wd; + logic wake_up_tile_63_we; logic [31:0] wake_up_group_wd; logic wake_up_group_we; + logic [31:0] wake_up_cluster_wd; + logic wake_up_cluster_we; logic [31:0] tcdm_start_address_qs; logic tcdm_start_address_re; logic [31:0] tcdm_end_address_qs; @@ -399,6 +513,1462 @@ module control_registers_reg_top #( .qs () ); + // Subregister 8 of Multireg wake_up_tile + // R[wake_up_tile_8]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_8_we), + .wd (wake_up_tile_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[8].qe), + .q (reg2hw.wake_up_tile[8].q ), + + .qs () + ); + + // Subregister 9 of Multireg wake_up_tile + // R[wake_up_tile_9]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_9_we), + .wd (wake_up_tile_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[9].qe), + .q (reg2hw.wake_up_tile[9].q ), + + .qs () + ); + + // Subregister 10 of Multireg wake_up_tile + // R[wake_up_tile_10]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_10_we), + .wd (wake_up_tile_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[10].qe), + .q (reg2hw.wake_up_tile[10].q ), + + .qs () + ); + + // Subregister 11 of Multireg wake_up_tile + // R[wake_up_tile_11]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_11_we), + .wd (wake_up_tile_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[11].qe), + .q (reg2hw.wake_up_tile[11].q ), + + .qs () + ); + + // Subregister 12 of Multireg wake_up_tile + // R[wake_up_tile_12]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_12_we), + .wd (wake_up_tile_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[12].qe), + .q (reg2hw.wake_up_tile[12].q ), + + .qs () + ); + + // Subregister 13 of Multireg wake_up_tile + // R[wake_up_tile_13]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_13_we), + .wd (wake_up_tile_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[13].qe), + .q (reg2hw.wake_up_tile[13].q ), + + .qs () + ); + + // Subregister 14 of Multireg wake_up_tile + // R[wake_up_tile_14]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_14_we), + .wd (wake_up_tile_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[14].qe), + .q (reg2hw.wake_up_tile[14].q ), + + .qs () + ); + + // Subregister 15 of Multireg wake_up_tile + // R[wake_up_tile_15]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_15_we), + .wd (wake_up_tile_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[15].qe), + .q (reg2hw.wake_up_tile[15].q ), + + .qs () + ); + + // Subregister 16 of Multireg wake_up_tile + // R[wake_up_tile_16]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_16_we), + .wd (wake_up_tile_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[16].qe), + .q (reg2hw.wake_up_tile[16].q ), + + .qs () + ); + + // Subregister 17 of Multireg wake_up_tile + // R[wake_up_tile_17]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_17_we), + .wd (wake_up_tile_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[17].qe), + .q (reg2hw.wake_up_tile[17].q ), + + .qs () + ); + + // Subregister 18 of Multireg wake_up_tile + // R[wake_up_tile_18]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_18_we), + .wd (wake_up_tile_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[18].qe), + .q (reg2hw.wake_up_tile[18].q ), + + .qs () + ); + + // Subregister 19 of Multireg wake_up_tile + // R[wake_up_tile_19]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_19_we), + .wd (wake_up_tile_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[19].qe), + .q (reg2hw.wake_up_tile[19].q ), + + .qs () + ); + + // Subregister 20 of Multireg wake_up_tile + // R[wake_up_tile_20]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_20_we), + .wd (wake_up_tile_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[20].qe), + .q (reg2hw.wake_up_tile[20].q ), + + .qs () + ); + + // Subregister 21 of Multireg wake_up_tile + // R[wake_up_tile_21]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_21_we), + .wd (wake_up_tile_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[21].qe), + .q (reg2hw.wake_up_tile[21].q ), + + .qs () + ); + + // Subregister 22 of Multireg wake_up_tile + // R[wake_up_tile_22]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_22_we), + .wd (wake_up_tile_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[22].qe), + .q (reg2hw.wake_up_tile[22].q ), + + .qs () + ); + + // Subregister 23 of Multireg wake_up_tile + // R[wake_up_tile_23]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_23_we), + .wd (wake_up_tile_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[23].qe), + .q (reg2hw.wake_up_tile[23].q ), + + .qs () + ); + + // Subregister 24 of Multireg wake_up_tile + // R[wake_up_tile_24]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_24_we), + .wd (wake_up_tile_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[24].qe), + .q (reg2hw.wake_up_tile[24].q ), + + .qs () + ); + + // Subregister 25 of Multireg wake_up_tile + // R[wake_up_tile_25]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_25_we), + .wd (wake_up_tile_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[25].qe), + .q (reg2hw.wake_up_tile[25].q ), + + .qs () + ); + + // Subregister 26 of Multireg wake_up_tile + // R[wake_up_tile_26]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_26_we), + .wd (wake_up_tile_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[26].qe), + .q (reg2hw.wake_up_tile[26].q ), + + .qs () + ); + + // Subregister 27 of Multireg wake_up_tile + // R[wake_up_tile_27]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_27_we), + .wd (wake_up_tile_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[27].qe), + .q (reg2hw.wake_up_tile[27].q ), + + .qs () + ); + + // Subregister 28 of Multireg wake_up_tile + // R[wake_up_tile_28]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_28_we), + .wd (wake_up_tile_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[28].qe), + .q (reg2hw.wake_up_tile[28].q ), + + .qs () + ); + + // Subregister 29 of Multireg wake_up_tile + // R[wake_up_tile_29]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_29_we), + .wd (wake_up_tile_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[29].qe), + .q (reg2hw.wake_up_tile[29].q ), + + .qs () + ); + + // Subregister 30 of Multireg wake_up_tile + // R[wake_up_tile_30]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_30_we), + .wd (wake_up_tile_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[30].qe), + .q (reg2hw.wake_up_tile[30].q ), + + .qs () + ); + + // Subregister 31 of Multireg wake_up_tile + // R[wake_up_tile_31]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_31_we), + .wd (wake_up_tile_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[31].qe), + .q (reg2hw.wake_up_tile[31].q ), + + .qs () + ); + + // Subregister 32 of Multireg wake_up_tile + // R[wake_up_tile_32]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_32_we), + .wd (wake_up_tile_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[32].qe), + .q (reg2hw.wake_up_tile[32].q ), + + .qs () + ); + + // Subregister 33 of Multireg wake_up_tile + // R[wake_up_tile_33]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_33_we), + .wd (wake_up_tile_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[33].qe), + .q (reg2hw.wake_up_tile[33].q ), + + .qs () + ); + + // Subregister 34 of Multireg wake_up_tile + // R[wake_up_tile_34]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_34_we), + .wd (wake_up_tile_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[34].qe), + .q (reg2hw.wake_up_tile[34].q ), + + .qs () + ); + + // Subregister 35 of Multireg wake_up_tile + // R[wake_up_tile_35]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_35 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_35_we), + .wd (wake_up_tile_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[35].qe), + .q (reg2hw.wake_up_tile[35].q ), + + .qs () + ); + + // Subregister 36 of Multireg wake_up_tile + // R[wake_up_tile_36]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_36 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_36_we), + .wd (wake_up_tile_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[36].qe), + .q (reg2hw.wake_up_tile[36].q ), + + .qs () + ); + + // Subregister 37 of Multireg wake_up_tile + // R[wake_up_tile_37]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_37 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_37_we), + .wd (wake_up_tile_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[37].qe), + .q (reg2hw.wake_up_tile[37].q ), + + .qs () + ); + + // Subregister 38 of Multireg wake_up_tile + // R[wake_up_tile_38]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_38 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_38_we), + .wd (wake_up_tile_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[38].qe), + .q (reg2hw.wake_up_tile[38].q ), + + .qs () + ); + + // Subregister 39 of Multireg wake_up_tile + // R[wake_up_tile_39]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_39 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_39_we), + .wd (wake_up_tile_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[39].qe), + .q (reg2hw.wake_up_tile[39].q ), + + .qs () + ); + + // Subregister 40 of Multireg wake_up_tile + // R[wake_up_tile_40]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_40 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_40_we), + .wd (wake_up_tile_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[40].qe), + .q (reg2hw.wake_up_tile[40].q ), + + .qs () + ); + + // Subregister 41 of Multireg wake_up_tile + // R[wake_up_tile_41]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_41 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_41_we), + .wd (wake_up_tile_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[41].qe), + .q (reg2hw.wake_up_tile[41].q ), + + .qs () + ); + + // Subregister 42 of Multireg wake_up_tile + // R[wake_up_tile_42]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_42 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_42_we), + .wd (wake_up_tile_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[42].qe), + .q (reg2hw.wake_up_tile[42].q ), + + .qs () + ); + + // Subregister 43 of Multireg wake_up_tile + // R[wake_up_tile_43]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_43 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_43_we), + .wd (wake_up_tile_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[43].qe), + .q (reg2hw.wake_up_tile[43].q ), + + .qs () + ); + + // Subregister 44 of Multireg wake_up_tile + // R[wake_up_tile_44]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_44 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_44_we), + .wd (wake_up_tile_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[44].qe), + .q (reg2hw.wake_up_tile[44].q ), + + .qs () + ); + + // Subregister 45 of Multireg wake_up_tile + // R[wake_up_tile_45]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_45 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_45_we), + .wd (wake_up_tile_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[45].qe), + .q (reg2hw.wake_up_tile[45].q ), + + .qs () + ); + + // Subregister 46 of Multireg wake_up_tile + // R[wake_up_tile_46]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_46 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_46_we), + .wd (wake_up_tile_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[46].qe), + .q (reg2hw.wake_up_tile[46].q ), + + .qs () + ); + + // Subregister 47 of Multireg wake_up_tile + // R[wake_up_tile_47]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_47 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_47_we), + .wd (wake_up_tile_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[47].qe), + .q (reg2hw.wake_up_tile[47].q ), + + .qs () + ); + + // Subregister 48 of Multireg wake_up_tile + // R[wake_up_tile_48]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_48 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_48_we), + .wd (wake_up_tile_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[48].qe), + .q (reg2hw.wake_up_tile[48].q ), + + .qs () + ); + + // Subregister 49 of Multireg wake_up_tile + // R[wake_up_tile_49]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_49 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_49_we), + .wd (wake_up_tile_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[49].qe), + .q (reg2hw.wake_up_tile[49].q ), + + .qs () + ); + + // Subregister 50 of Multireg wake_up_tile + // R[wake_up_tile_50]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_50 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_50_we), + .wd (wake_up_tile_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[50].qe), + .q (reg2hw.wake_up_tile[50].q ), + + .qs () + ); + + // Subregister 51 of Multireg wake_up_tile + // R[wake_up_tile_51]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_51 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_51_we), + .wd (wake_up_tile_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[51].qe), + .q (reg2hw.wake_up_tile[51].q ), + + .qs () + ); + + // Subregister 52 of Multireg wake_up_tile + // R[wake_up_tile_52]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_52 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_52_we), + .wd (wake_up_tile_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[52].qe), + .q (reg2hw.wake_up_tile[52].q ), + + .qs () + ); + + // Subregister 53 of Multireg wake_up_tile + // R[wake_up_tile_53]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_53 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_53_we), + .wd (wake_up_tile_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[53].qe), + .q (reg2hw.wake_up_tile[53].q ), + + .qs () + ); + + // Subregister 54 of Multireg wake_up_tile + // R[wake_up_tile_54]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_54 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_54_we), + .wd (wake_up_tile_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[54].qe), + .q (reg2hw.wake_up_tile[54].q ), + + .qs () + ); + + // Subregister 55 of Multireg wake_up_tile + // R[wake_up_tile_55]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_55 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_55_we), + .wd (wake_up_tile_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[55].qe), + .q (reg2hw.wake_up_tile[55].q ), + + .qs () + ); + + // Subregister 56 of Multireg wake_up_tile + // R[wake_up_tile_56]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_56 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_56_we), + .wd (wake_up_tile_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[56].qe), + .q (reg2hw.wake_up_tile[56].q ), + + .qs () + ); + + // Subregister 57 of Multireg wake_up_tile + // R[wake_up_tile_57]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_57 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_57_we), + .wd (wake_up_tile_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[57].qe), + .q (reg2hw.wake_up_tile[57].q ), + + .qs () + ); + + // Subregister 58 of Multireg wake_up_tile + // R[wake_up_tile_58]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_58 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_58_we), + .wd (wake_up_tile_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[58].qe), + .q (reg2hw.wake_up_tile[58].q ), + + .qs () + ); + + // Subregister 59 of Multireg wake_up_tile + // R[wake_up_tile_59]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_59 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_59_we), + .wd (wake_up_tile_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[59].qe), + .q (reg2hw.wake_up_tile[59].q ), + + .qs () + ); + + // Subregister 60 of Multireg wake_up_tile + // R[wake_up_tile_60]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_60 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_60_we), + .wd (wake_up_tile_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[60].qe), + .q (reg2hw.wake_up_tile[60].q ), + + .qs () + ); + + // Subregister 61 of Multireg wake_up_tile + // R[wake_up_tile_61]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_61 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_61_we), + .wd (wake_up_tile_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[61].qe), + .q (reg2hw.wake_up_tile[61].q ), + + .qs () + ); + + // Subregister 62 of Multireg wake_up_tile + // R[wake_up_tile_62]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_62 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_62_we), + .wd (wake_up_tile_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[62].qe), + .q (reg2hw.wake_up_tile[62].q ), + + .qs () + ); + + // Subregister 63 of Multireg wake_up_tile + // R[wake_up_tile_63]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_tile_63 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_tile_63_we), + .wd (wake_up_tile_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_tile[63].qe), + .q (reg2hw.wake_up_tile[63].q ), + + .qs () + ); + // R[wake_up_group]: V(False) @@ -411,16 +1981,42 @@ module control_registers_reg_top #( .rst_ni (rst_ni ), // from register interface - .we (wake_up_group_we), - .wd (wake_up_group_wd), + .we (wake_up_group_we), + .wd (wake_up_group_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (reg2hw.wake_up_group.qe), + .q (reg2hw.wake_up_group.q ), + + .qs () + ); + + + // R[wake_up_cluster]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("WO"), + .RESVAL (32'h0) + ) u_wake_up_cluster ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_up_cluster_we), + .wd (wake_up_cluster_wd), // from internal hardware .de (1'b0), .d ('0 ), // to internal hardware - .qe (reg2hw.wake_up_group.qe), - .q (reg2hw.wake_up_group.q ), + .qe (reg2hw.wake_up_cluster.qe), + .q (reg2hw.wake_up_cluster.q ), .qs () ); @@ -662,7 +2258,7 @@ module control_registers_reg_top #( - logic [23:0] addr_hit; + logic [80:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CONTROL_REGISTERS_EOC_OFFSET); @@ -675,20 +2271,77 @@ module control_registers_reg_top #( addr_hit[ 7] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_5_OFFSET); addr_hit[ 8] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_6_OFFSET); addr_hit[ 9] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_7_OFFSET); - addr_hit[10] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_GROUP_OFFSET); - addr_hit[11] = (reg_addr == CONTROL_REGISTERS_TCDM_START_ADDRESS_OFFSET); - addr_hit[12] = (reg_addr == CONTROL_REGISTERS_TCDM_END_ADDRESS_OFFSET); - addr_hit[13] = (reg_addr == CONTROL_REGISTERS_NR_CORES_REG_OFFSET); - addr_hit[14] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_ENABLE_OFFSET); - addr_hit[15] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_FLUSH_OFFSET); - addr_hit[16] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_0_OFFSET); - addr_hit[17] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_1_OFFSET); - addr_hit[18] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_2_OFFSET); - addr_hit[19] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_3_OFFSET); - addr_hit[20] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_0_OFFSET); - addr_hit[21] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_1_OFFSET); - addr_hit[22] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_2_OFFSET); - addr_hit[23] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_3_OFFSET); + addr_hit[10] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_8_OFFSET); + addr_hit[11] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_9_OFFSET); + addr_hit[12] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_10_OFFSET); + addr_hit[13] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_11_OFFSET); + addr_hit[14] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_12_OFFSET); + addr_hit[15] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_13_OFFSET); + addr_hit[16] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_14_OFFSET); + addr_hit[17] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_15_OFFSET); + addr_hit[18] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_16_OFFSET); + addr_hit[19] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_17_OFFSET); + addr_hit[20] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_18_OFFSET); + addr_hit[21] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_19_OFFSET); + addr_hit[22] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_20_OFFSET); + addr_hit[23] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_21_OFFSET); + addr_hit[24] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_22_OFFSET); + addr_hit[25] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_23_OFFSET); + addr_hit[26] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_24_OFFSET); + addr_hit[27] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_25_OFFSET); + addr_hit[28] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_26_OFFSET); + addr_hit[29] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_27_OFFSET); + addr_hit[30] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_28_OFFSET); + addr_hit[31] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_29_OFFSET); + addr_hit[32] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_30_OFFSET); + addr_hit[33] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_31_OFFSET); + addr_hit[34] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_32_OFFSET); + addr_hit[35] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_33_OFFSET); + addr_hit[36] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_34_OFFSET); + addr_hit[37] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_35_OFFSET); + addr_hit[38] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_36_OFFSET); + addr_hit[39] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_37_OFFSET); + addr_hit[40] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_38_OFFSET); + addr_hit[41] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_39_OFFSET); + addr_hit[42] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_40_OFFSET); + addr_hit[43] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_41_OFFSET); + addr_hit[44] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_42_OFFSET); + addr_hit[45] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_43_OFFSET); + addr_hit[46] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_44_OFFSET); + addr_hit[47] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_45_OFFSET); + addr_hit[48] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_46_OFFSET); + addr_hit[49] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_47_OFFSET); + addr_hit[50] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_48_OFFSET); + addr_hit[51] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_49_OFFSET); + addr_hit[52] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_50_OFFSET); + addr_hit[53] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_51_OFFSET); + addr_hit[54] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_52_OFFSET); + addr_hit[55] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_53_OFFSET); + addr_hit[56] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_54_OFFSET); + addr_hit[57] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_55_OFFSET); + addr_hit[58] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_56_OFFSET); + addr_hit[59] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_57_OFFSET); + addr_hit[60] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_58_OFFSET); + addr_hit[61] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_59_OFFSET); + addr_hit[62] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_60_OFFSET); + addr_hit[63] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_61_OFFSET); + addr_hit[64] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_62_OFFSET); + addr_hit[65] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_TILE_63_OFFSET); + addr_hit[66] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_GROUP_OFFSET); + addr_hit[67] = (reg_addr == CONTROL_REGISTERS_WAKE_UP_CLUSTER_OFFSET); + addr_hit[68] = (reg_addr == CONTROL_REGISTERS_TCDM_START_ADDRESS_OFFSET); + addr_hit[69] = (reg_addr == CONTROL_REGISTERS_TCDM_END_ADDRESS_OFFSET); + addr_hit[70] = (reg_addr == CONTROL_REGISTERS_NR_CORES_REG_OFFSET); + addr_hit[71] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_ENABLE_OFFSET); + addr_hit[72] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_FLUSH_OFFSET); + addr_hit[73] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_0_OFFSET); + addr_hit[74] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_1_OFFSET); + addr_hit[75] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_2_OFFSET); + addr_hit[76] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_START_3_OFFSET); + addr_hit[77] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_0_OFFSET); + addr_hit[78] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_1_OFFSET); + addr_hit[79] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_2_OFFSET); + addr_hit[80] = (reg_addr == CONTROL_REGISTERS_RO_CACHE_END_3_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -719,7 +2372,64 @@ module control_registers_reg_top #( (addr_hit[20] & (|(CONTROL_REGISTERS_PERMIT[20] & ~reg_be))) | (addr_hit[21] & (|(CONTROL_REGISTERS_PERMIT[21] & ~reg_be))) | (addr_hit[22] & (|(CONTROL_REGISTERS_PERMIT[22] & ~reg_be))) | - (addr_hit[23] & (|(CONTROL_REGISTERS_PERMIT[23] & ~reg_be))))); + (addr_hit[23] & (|(CONTROL_REGISTERS_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(CONTROL_REGISTERS_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(CONTROL_REGISTERS_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(CONTROL_REGISTERS_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(CONTROL_REGISTERS_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(CONTROL_REGISTERS_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(CONTROL_REGISTERS_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(CONTROL_REGISTERS_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(CONTROL_REGISTERS_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(CONTROL_REGISTERS_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(CONTROL_REGISTERS_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(CONTROL_REGISTERS_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(CONTROL_REGISTERS_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(CONTROL_REGISTERS_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(CONTROL_REGISTERS_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(CONTROL_REGISTERS_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(CONTROL_REGISTERS_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(CONTROL_REGISTERS_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(CONTROL_REGISTERS_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(CONTROL_REGISTERS_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(CONTROL_REGISTERS_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(CONTROL_REGISTERS_PERMIT[44] & ~reg_be))) | + (addr_hit[45] & (|(CONTROL_REGISTERS_PERMIT[45] & ~reg_be))) | + (addr_hit[46] & (|(CONTROL_REGISTERS_PERMIT[46] & ~reg_be))) | + (addr_hit[47] & (|(CONTROL_REGISTERS_PERMIT[47] & ~reg_be))) | + (addr_hit[48] & (|(CONTROL_REGISTERS_PERMIT[48] & ~reg_be))) | + (addr_hit[49] & (|(CONTROL_REGISTERS_PERMIT[49] & ~reg_be))) | + (addr_hit[50] & (|(CONTROL_REGISTERS_PERMIT[50] & ~reg_be))) | + (addr_hit[51] & (|(CONTROL_REGISTERS_PERMIT[51] & ~reg_be))) | + (addr_hit[52] & (|(CONTROL_REGISTERS_PERMIT[52] & ~reg_be))) | + (addr_hit[53] & (|(CONTROL_REGISTERS_PERMIT[53] & ~reg_be))) | + (addr_hit[54] & (|(CONTROL_REGISTERS_PERMIT[54] & ~reg_be))) | + (addr_hit[55] & (|(CONTROL_REGISTERS_PERMIT[55] & ~reg_be))) | + (addr_hit[56] & (|(CONTROL_REGISTERS_PERMIT[56] & ~reg_be))) | + (addr_hit[57] & (|(CONTROL_REGISTERS_PERMIT[57] & ~reg_be))) | + (addr_hit[58] & (|(CONTROL_REGISTERS_PERMIT[58] & ~reg_be))) | + (addr_hit[59] & (|(CONTROL_REGISTERS_PERMIT[59] & ~reg_be))) | + (addr_hit[60] & (|(CONTROL_REGISTERS_PERMIT[60] & ~reg_be))) | + (addr_hit[61] & (|(CONTROL_REGISTERS_PERMIT[61] & ~reg_be))) | + (addr_hit[62] & (|(CONTROL_REGISTERS_PERMIT[62] & ~reg_be))) | + (addr_hit[63] & (|(CONTROL_REGISTERS_PERMIT[63] & ~reg_be))) | + (addr_hit[64] & (|(CONTROL_REGISTERS_PERMIT[64] & ~reg_be))) | + (addr_hit[65] & (|(CONTROL_REGISTERS_PERMIT[65] & ~reg_be))) | + (addr_hit[66] & (|(CONTROL_REGISTERS_PERMIT[66] & ~reg_be))) | + (addr_hit[67] & (|(CONTROL_REGISTERS_PERMIT[67] & ~reg_be))) | + (addr_hit[68] & (|(CONTROL_REGISTERS_PERMIT[68] & ~reg_be))) | + (addr_hit[69] & (|(CONTROL_REGISTERS_PERMIT[69] & ~reg_be))) | + (addr_hit[70] & (|(CONTROL_REGISTERS_PERMIT[70] & ~reg_be))) | + (addr_hit[71] & (|(CONTROL_REGISTERS_PERMIT[71] & ~reg_be))) | + (addr_hit[72] & (|(CONTROL_REGISTERS_PERMIT[72] & ~reg_be))) | + (addr_hit[73] & (|(CONTROL_REGISTERS_PERMIT[73] & ~reg_be))) | + (addr_hit[74] & (|(CONTROL_REGISTERS_PERMIT[74] & ~reg_be))) | + (addr_hit[75] & (|(CONTROL_REGISTERS_PERMIT[75] & ~reg_be))) | + (addr_hit[76] & (|(CONTROL_REGISTERS_PERMIT[76] & ~reg_be))) | + (addr_hit[77] & (|(CONTROL_REGISTERS_PERMIT[77] & ~reg_be))) | + (addr_hit[78] & (|(CONTROL_REGISTERS_PERMIT[78] & ~reg_be))) | + (addr_hit[79] & (|(CONTROL_REGISTERS_PERMIT[79] & ~reg_be))) | + (addr_hit[80] & (|(CONTROL_REGISTERS_PERMIT[80] & ~reg_be))))); end assign eoc_we = addr_hit[0] & reg_we & !reg_error; @@ -752,52 +2462,223 @@ module control_registers_reg_top #( assign wake_up_tile_7_we = addr_hit[9] & reg_we & !reg_error; assign wake_up_tile_7_wd = reg_wdata[31:0]; - assign wake_up_group_we = addr_hit[10] & reg_we & !reg_error; + assign wake_up_tile_8_we = addr_hit[10] & reg_we & !reg_error; + assign wake_up_tile_8_wd = reg_wdata[31:0]; + + assign wake_up_tile_9_we = addr_hit[11] & reg_we & !reg_error; + assign wake_up_tile_9_wd = reg_wdata[31:0]; + + assign wake_up_tile_10_we = addr_hit[12] & reg_we & !reg_error; + assign wake_up_tile_10_wd = reg_wdata[31:0]; + + assign wake_up_tile_11_we = addr_hit[13] & reg_we & !reg_error; + assign wake_up_tile_11_wd = reg_wdata[31:0]; + + assign wake_up_tile_12_we = addr_hit[14] & reg_we & !reg_error; + assign wake_up_tile_12_wd = reg_wdata[31:0]; + + assign wake_up_tile_13_we = addr_hit[15] & reg_we & !reg_error; + assign wake_up_tile_13_wd = reg_wdata[31:0]; + + assign wake_up_tile_14_we = addr_hit[16] & reg_we & !reg_error; + assign wake_up_tile_14_wd = reg_wdata[31:0]; + + assign wake_up_tile_15_we = addr_hit[17] & reg_we & !reg_error; + assign wake_up_tile_15_wd = reg_wdata[31:0]; + + assign wake_up_tile_16_we = addr_hit[18] & reg_we & !reg_error; + assign wake_up_tile_16_wd = reg_wdata[31:0]; + + assign wake_up_tile_17_we = addr_hit[19] & reg_we & !reg_error; + assign wake_up_tile_17_wd = reg_wdata[31:0]; + + assign wake_up_tile_18_we = addr_hit[20] & reg_we & !reg_error; + assign wake_up_tile_18_wd = reg_wdata[31:0]; + + assign wake_up_tile_19_we = addr_hit[21] & reg_we & !reg_error; + assign wake_up_tile_19_wd = reg_wdata[31:0]; + + assign wake_up_tile_20_we = addr_hit[22] & reg_we & !reg_error; + assign wake_up_tile_20_wd = reg_wdata[31:0]; + + assign wake_up_tile_21_we = addr_hit[23] & reg_we & !reg_error; + assign wake_up_tile_21_wd = reg_wdata[31:0]; + + assign wake_up_tile_22_we = addr_hit[24] & reg_we & !reg_error; + assign wake_up_tile_22_wd = reg_wdata[31:0]; + + assign wake_up_tile_23_we = addr_hit[25] & reg_we & !reg_error; + assign wake_up_tile_23_wd = reg_wdata[31:0]; + + assign wake_up_tile_24_we = addr_hit[26] & reg_we & !reg_error; + assign wake_up_tile_24_wd = reg_wdata[31:0]; + + assign wake_up_tile_25_we = addr_hit[27] & reg_we & !reg_error; + assign wake_up_tile_25_wd = reg_wdata[31:0]; + + assign wake_up_tile_26_we = addr_hit[28] & reg_we & !reg_error; + assign wake_up_tile_26_wd = reg_wdata[31:0]; + + assign wake_up_tile_27_we = addr_hit[29] & reg_we & !reg_error; + assign wake_up_tile_27_wd = reg_wdata[31:0]; + + assign wake_up_tile_28_we = addr_hit[30] & reg_we & !reg_error; + assign wake_up_tile_28_wd = reg_wdata[31:0]; + + assign wake_up_tile_29_we = addr_hit[31] & reg_we & !reg_error; + assign wake_up_tile_29_wd = reg_wdata[31:0]; + + assign wake_up_tile_30_we = addr_hit[32] & reg_we & !reg_error; + assign wake_up_tile_30_wd = reg_wdata[31:0]; + + assign wake_up_tile_31_we = addr_hit[33] & reg_we & !reg_error; + assign wake_up_tile_31_wd = reg_wdata[31:0]; + + assign wake_up_tile_32_we = addr_hit[34] & reg_we & !reg_error; + assign wake_up_tile_32_wd = reg_wdata[31:0]; + + assign wake_up_tile_33_we = addr_hit[35] & reg_we & !reg_error; + assign wake_up_tile_33_wd = reg_wdata[31:0]; + + assign wake_up_tile_34_we = addr_hit[36] & reg_we & !reg_error; + assign wake_up_tile_34_wd = reg_wdata[31:0]; + + assign wake_up_tile_35_we = addr_hit[37] & reg_we & !reg_error; + assign wake_up_tile_35_wd = reg_wdata[31:0]; + + assign wake_up_tile_36_we = addr_hit[38] & reg_we & !reg_error; + assign wake_up_tile_36_wd = reg_wdata[31:0]; + + assign wake_up_tile_37_we = addr_hit[39] & reg_we & !reg_error; + assign wake_up_tile_37_wd = reg_wdata[31:0]; + + assign wake_up_tile_38_we = addr_hit[40] & reg_we & !reg_error; + assign wake_up_tile_38_wd = reg_wdata[31:0]; + + assign wake_up_tile_39_we = addr_hit[41] & reg_we & !reg_error; + assign wake_up_tile_39_wd = reg_wdata[31:0]; + + assign wake_up_tile_40_we = addr_hit[42] & reg_we & !reg_error; + assign wake_up_tile_40_wd = reg_wdata[31:0]; + + assign wake_up_tile_41_we = addr_hit[43] & reg_we & !reg_error; + assign wake_up_tile_41_wd = reg_wdata[31:0]; + + assign wake_up_tile_42_we = addr_hit[44] & reg_we & !reg_error; + assign wake_up_tile_42_wd = reg_wdata[31:0]; + + assign wake_up_tile_43_we = addr_hit[45] & reg_we & !reg_error; + assign wake_up_tile_43_wd = reg_wdata[31:0]; + + assign wake_up_tile_44_we = addr_hit[46] & reg_we & !reg_error; + assign wake_up_tile_44_wd = reg_wdata[31:0]; + + assign wake_up_tile_45_we = addr_hit[47] & reg_we & !reg_error; + assign wake_up_tile_45_wd = reg_wdata[31:0]; + + assign wake_up_tile_46_we = addr_hit[48] & reg_we & !reg_error; + assign wake_up_tile_46_wd = reg_wdata[31:0]; + + assign wake_up_tile_47_we = addr_hit[49] & reg_we & !reg_error; + assign wake_up_tile_47_wd = reg_wdata[31:0]; + + assign wake_up_tile_48_we = addr_hit[50] & reg_we & !reg_error; + assign wake_up_tile_48_wd = reg_wdata[31:0]; + + assign wake_up_tile_49_we = addr_hit[51] & reg_we & !reg_error; + assign wake_up_tile_49_wd = reg_wdata[31:0]; + + assign wake_up_tile_50_we = addr_hit[52] & reg_we & !reg_error; + assign wake_up_tile_50_wd = reg_wdata[31:0]; + + assign wake_up_tile_51_we = addr_hit[53] & reg_we & !reg_error; + assign wake_up_tile_51_wd = reg_wdata[31:0]; + + assign wake_up_tile_52_we = addr_hit[54] & reg_we & !reg_error; + assign wake_up_tile_52_wd = reg_wdata[31:0]; + + assign wake_up_tile_53_we = addr_hit[55] & reg_we & !reg_error; + assign wake_up_tile_53_wd = reg_wdata[31:0]; + + assign wake_up_tile_54_we = addr_hit[56] & reg_we & !reg_error; + assign wake_up_tile_54_wd = reg_wdata[31:0]; + + assign wake_up_tile_55_we = addr_hit[57] & reg_we & !reg_error; + assign wake_up_tile_55_wd = reg_wdata[31:0]; + + assign wake_up_tile_56_we = addr_hit[58] & reg_we & !reg_error; + assign wake_up_tile_56_wd = reg_wdata[31:0]; + + assign wake_up_tile_57_we = addr_hit[59] & reg_we & !reg_error; + assign wake_up_tile_57_wd = reg_wdata[31:0]; + + assign wake_up_tile_58_we = addr_hit[60] & reg_we & !reg_error; + assign wake_up_tile_58_wd = reg_wdata[31:0]; + + assign wake_up_tile_59_we = addr_hit[61] & reg_we & !reg_error; + assign wake_up_tile_59_wd = reg_wdata[31:0]; + + assign wake_up_tile_60_we = addr_hit[62] & reg_we & !reg_error; + assign wake_up_tile_60_wd = reg_wdata[31:0]; + + assign wake_up_tile_61_we = addr_hit[63] & reg_we & !reg_error; + assign wake_up_tile_61_wd = reg_wdata[31:0]; + + assign wake_up_tile_62_we = addr_hit[64] & reg_we & !reg_error; + assign wake_up_tile_62_wd = reg_wdata[31:0]; + + assign wake_up_tile_63_we = addr_hit[65] & reg_we & !reg_error; + assign wake_up_tile_63_wd = reg_wdata[31:0]; + + assign wake_up_group_we = addr_hit[66] & reg_we & !reg_error; assign wake_up_group_wd = reg_wdata[31:0]; - assign tcdm_start_address_re = addr_hit[11] & reg_re & !reg_error; + assign wake_up_cluster_we = addr_hit[67] & reg_we & !reg_error; + assign wake_up_cluster_wd = reg_wdata[31:0]; - assign tcdm_end_address_re = addr_hit[12] & reg_re & !reg_error; + assign tcdm_start_address_re = addr_hit[68] & reg_re & !reg_error; - assign nr_cores_reg_re = addr_hit[13] & reg_re & !reg_error; + assign tcdm_end_address_re = addr_hit[69] & reg_re & !reg_error; - assign ro_cache_enable_we = addr_hit[14] & reg_we & !reg_error; + assign nr_cores_reg_re = addr_hit[70] & reg_re & !reg_error; + + assign ro_cache_enable_we = addr_hit[71] & reg_we & !reg_error; assign ro_cache_enable_wd = reg_wdata[31:0]; - assign ro_cache_flush_we = addr_hit[15] & reg_we & !reg_error; + assign ro_cache_flush_we = addr_hit[72] & reg_we & !reg_error; assign ro_cache_flush_wd = reg_wdata[31:0]; - assign ro_cache_start_0_we = addr_hit[16] & reg_we & !reg_error; + assign ro_cache_start_0_we = addr_hit[73] & reg_we & !reg_error; assign ro_cache_start_0_wd = reg_wdata[31:0]; - assign ro_cache_start_0_re = addr_hit[16] & reg_re & !reg_error; + assign ro_cache_start_0_re = addr_hit[73] & reg_re & !reg_error; - assign ro_cache_start_1_we = addr_hit[17] & reg_we & !reg_error; + assign ro_cache_start_1_we = addr_hit[74] & reg_we & !reg_error; assign ro_cache_start_1_wd = reg_wdata[31:0]; - assign ro_cache_start_1_re = addr_hit[17] & reg_re & !reg_error; + assign ro_cache_start_1_re = addr_hit[74] & reg_re & !reg_error; - assign ro_cache_start_2_we = addr_hit[18] & reg_we & !reg_error; + assign ro_cache_start_2_we = addr_hit[75] & reg_we & !reg_error; assign ro_cache_start_2_wd = reg_wdata[31:0]; - assign ro_cache_start_2_re = addr_hit[18] & reg_re & !reg_error; + assign ro_cache_start_2_re = addr_hit[75] & reg_re & !reg_error; - assign ro_cache_start_3_we = addr_hit[19] & reg_we & !reg_error; + assign ro_cache_start_3_we = addr_hit[76] & reg_we & !reg_error; assign ro_cache_start_3_wd = reg_wdata[31:0]; - assign ro_cache_start_3_re = addr_hit[19] & reg_re & !reg_error; + assign ro_cache_start_3_re = addr_hit[76] & reg_re & !reg_error; - assign ro_cache_end_0_we = addr_hit[20] & reg_we & !reg_error; + assign ro_cache_end_0_we = addr_hit[77] & reg_we & !reg_error; assign ro_cache_end_0_wd = reg_wdata[31:0]; - assign ro_cache_end_0_re = addr_hit[20] & reg_re & !reg_error; + assign ro_cache_end_0_re = addr_hit[77] & reg_re & !reg_error; - assign ro_cache_end_1_we = addr_hit[21] & reg_we & !reg_error; + assign ro_cache_end_1_we = addr_hit[78] & reg_we & !reg_error; assign ro_cache_end_1_wd = reg_wdata[31:0]; - assign ro_cache_end_1_re = addr_hit[21] & reg_re & !reg_error; + assign ro_cache_end_1_re = addr_hit[78] & reg_re & !reg_error; - assign ro_cache_end_2_we = addr_hit[22] & reg_we & !reg_error; + assign ro_cache_end_2_we = addr_hit[79] & reg_we & !reg_error; assign ro_cache_end_2_wd = reg_wdata[31:0]; - assign ro_cache_end_2_re = addr_hit[22] & reg_re & !reg_error; + assign ro_cache_end_2_re = addr_hit[79] & reg_re & !reg_error; - assign ro_cache_end_3_we = addr_hit[23] & reg_we & !reg_error; + assign ro_cache_end_3_we = addr_hit[80] & reg_we & !reg_error; assign ro_cache_end_3_wd = reg_wdata[31:0]; - assign ro_cache_end_3_re = addr_hit[23] & reg_re & !reg_error; + assign ro_cache_end_3_re = addr_hit[80] & reg_re & !reg_error; // Read data return always_comb begin @@ -848,54 +2729,282 @@ module control_registers_reg_top #( end addr_hit[11]: begin - reg_rdata_next[31:0] = tcdm_start_address_qs; + reg_rdata_next[31:0] = '0; end addr_hit[12]: begin - reg_rdata_next[31:0] = tcdm_end_address_qs; + reg_rdata_next[31:0] = '0; end addr_hit[13]: begin - reg_rdata_next[31:0] = nr_cores_reg_qs; + reg_rdata_next[31:0] = '0; end addr_hit[14]: begin - reg_rdata_next[31:0] = ro_cache_enable_qs; + reg_rdata_next[31:0] = '0; end addr_hit[15]: begin - reg_rdata_next[31:0] = ro_cache_flush_qs; + reg_rdata_next[31:0] = '0; end addr_hit[16]: begin - reg_rdata_next[31:0] = ro_cache_start_0_qs; + reg_rdata_next[31:0] = '0; end addr_hit[17]: begin - reg_rdata_next[31:0] = ro_cache_start_1_qs; + reg_rdata_next[31:0] = '0; end addr_hit[18]: begin - reg_rdata_next[31:0] = ro_cache_start_2_qs; + reg_rdata_next[31:0] = '0; end addr_hit[19]: begin - reg_rdata_next[31:0] = ro_cache_start_3_qs; + reg_rdata_next[31:0] = '0; end addr_hit[20]: begin - reg_rdata_next[31:0] = ro_cache_end_0_qs; + reg_rdata_next[31:0] = '0; end addr_hit[21]: begin - reg_rdata_next[31:0] = ro_cache_end_1_qs; + reg_rdata_next[31:0] = '0; end addr_hit[22]: begin - reg_rdata_next[31:0] = ro_cache_end_2_qs; + reg_rdata_next[31:0] = '0; end addr_hit[23]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[24]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[25]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[26]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[27]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[28]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[29]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[30]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[31]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[32]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[33]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[34]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[35]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[36]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[37]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[38]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[39]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[40]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[41]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[42]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[43]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[44]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[45]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[46]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[47]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[48]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[49]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[50]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[51]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[52]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[53]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[54]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[55]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[56]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[57]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[58]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[59]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[60]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[61]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[62]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[63]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[64]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[65]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[66]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[67]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[68]: begin + reg_rdata_next[31:0] = tcdm_start_address_qs; + end + + addr_hit[69]: begin + reg_rdata_next[31:0] = tcdm_end_address_qs; + end + + addr_hit[70]: begin + reg_rdata_next[31:0] = nr_cores_reg_qs; + end + + addr_hit[71]: begin + reg_rdata_next[31:0] = ro_cache_enable_qs; + end + + addr_hit[72]: begin + reg_rdata_next[31:0] = ro_cache_flush_qs; + end + + addr_hit[73]: begin + reg_rdata_next[31:0] = ro_cache_start_0_qs; + end + + addr_hit[74]: begin + reg_rdata_next[31:0] = ro_cache_start_1_qs; + end + + addr_hit[75]: begin + reg_rdata_next[31:0] = ro_cache_start_2_qs; + end + + addr_hit[76]: begin + reg_rdata_next[31:0] = ro_cache_start_3_qs; + end + + addr_hit[77]: begin + reg_rdata_next[31:0] = ro_cache_end_0_qs; + end + + addr_hit[78]: begin + reg_rdata_next[31:0] = ro_cache_end_1_qs; + end + + addr_hit[79]: begin + reg_rdata_next[31:0] = ro_cache_end_2_qs; + end + + addr_hit[80]: begin reg_rdata_next[31:0] = ro_cache_end_3_qs; end @@ -922,7 +3031,7 @@ endmodule /* verilator lint_off DECLFILENAME */ module control_registers_reg_top_intf #( - parameter int AW = 7, + parameter int AW = 9, localparam int DW = 32 ) ( input logic clk_i, diff --git a/hardware/src/ctrl_registers.sv b/hardware/src/ctrl_registers.sv index 3e35434a4..daf112743 100644 --- a/hardware/src/ctrl_registers.sv +++ b/hardware/src/ctrl_registers.sv @@ -101,9 +101,11 @@ module ctrl_registers /************************ * Wakeup Pulse Logic * ************************/ + import mempool_pkg::NumCoresPerCluster; import mempool_pkg::NumCoresPerGroup; import mempool_pkg::NumCoresPerTile; import mempool_pkg::NumTilesPerGroup; + import mempool_pkg::NumClusters; import mempool_pkg::NumGroups; // Delay the write-enable signal by one cycle so it arrives @@ -111,12 +113,14 @@ module ctrl_registers logic wake_up_pulse; logic [MAX_NumGroups-1:0] wake_up_tile_pulse; logic wake_up_group_pulse; + logic wake_up_cluster_pulse; `FF(wake_up_pulse, ctrl_reg2hw.wake_up.qe, '0) for (genvar i = 0; i < MAX_NumGroups; i++) begin : gen_wake_up_tile_reg `FF(wake_up_tile_pulse[i], ctrl_reg2hw.wake_up_tile[i].qe, '0) end `FF(wake_up_group_pulse, ctrl_reg2hw.wake_up_group.qe, '0) + `FF(wake_up_cluster_pulse, ctrl_reg2hw.wake_up_cluster.qe, '0) always_comb begin wake_up_o = '0; @@ -148,6 +152,16 @@ module ctrl_registers wake_up_o = {NumCores{1'b1}}; end end + // converts 32-bit cluster wake-up mask into a 'NumCores'-bit mask + if (wake_up_cluster_pulse) begin + if (ctrl_reg2hw.wake_up_cluster.q <= {NumClusters{1'b1}}) begin + for(int i = 0; i < NumClusters; i = i + 1) begin + wake_up_o[NumCoresPerCluster * i +: NumCoresPerCluster] = {NumCoresPerCluster{ctrl_reg2hw.wake_up_cluster.q[i]}}; + end + end else if (ctrl_reg2hw.wake_up_cluster.q == {DataWidth{1'b1}}) begin + wake_up_o = {NumCores{1'b1}}; + end + end end /*********************** diff --git a/software/runtime/control_registers.h b/software/runtime/control_registers.h index 95bd21e45..fd7c68fa7 100644 --- a/software/runtime/control_registers.h +++ b/software/runtime/control_registers.h @@ -17,7 +17,7 @@ extern "C" { #define CONTROL_REGISTERS_PARAM_R_O_CACHE_NUM_ADDR_RULES 4 // Maximum number of groups that we support in any configuration -#define CONTROL_REGISTERS_PARAM_MAX_NUMGROUPS 8 +#define CONTROL_REGISTERS_PARAM_MAX_NUMGROUPS 64 // Register width #define CONTROL_REGISTERS_PARAM_REG_WIDTH 32 @@ -31,7 +31,7 @@ extern "C" { // Wake Up Tile Register (common parameters) #define CONTROL_REGISTERS_WAKE_UP_TILE_WAKE_UP_TILE_FIELD_WIDTH 32 #define CONTROL_REGISTERS_WAKE_UP_TILE_WAKE_UP_TILE_FIELDS_PER_REG 1 -#define CONTROL_REGISTERS_WAKE_UP_TILE_MULTIREG_COUNT 8 +#define CONTROL_REGISTERS_WAKE_UP_TILE_MULTIREG_COUNT 64 // Wake Up Tile Register #define CONTROL_REGISTERS_WAKE_UP_TILE_0_REG_OFFSET 0x8 @@ -57,23 +57,194 @@ extern "C" { // Wake Up Tile Register #define CONTROL_REGISTERS_WAKE_UP_TILE_7_REG_OFFSET 0x24 +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_8_REG_OFFSET 0x28 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_9_REG_OFFSET 0x2c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_10_REG_OFFSET 0x30 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_11_REG_OFFSET 0x34 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_12_REG_OFFSET 0x38 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_13_REG_OFFSET 0x3c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_14_REG_OFFSET 0x40 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_15_REG_OFFSET 0x44 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_16_REG_OFFSET 0x48 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_17_REG_OFFSET 0x4c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_18_REG_OFFSET 0x50 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_19_REG_OFFSET 0x54 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_20_REG_OFFSET 0x58 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_21_REG_OFFSET 0x5c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_22_REG_OFFSET 0x60 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_23_REG_OFFSET 0x64 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_24_REG_OFFSET 0x68 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_25_REG_OFFSET 0x6c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_26_REG_OFFSET 0x70 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_27_REG_OFFSET 0x74 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_28_REG_OFFSET 0x78 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_29_REG_OFFSET 0x7c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_30_REG_OFFSET 0x80 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_31_REG_OFFSET 0x84 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_32_REG_OFFSET 0x88 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_33_REG_OFFSET 0x8c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_34_REG_OFFSET 0x90 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_35_REG_OFFSET 0x94 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_36_REG_OFFSET 0x98 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_37_REG_OFFSET 0x9c + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_38_REG_OFFSET 0xa0 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_39_REG_OFFSET 0xa4 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_40_REG_OFFSET 0xa8 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_41_REG_OFFSET 0xac + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_42_REG_OFFSET 0xb0 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_43_REG_OFFSET 0xb4 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_44_REG_OFFSET 0xb8 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_45_REG_OFFSET 0xbc + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_46_REG_OFFSET 0xc0 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_47_REG_OFFSET 0xc4 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_48_REG_OFFSET 0xc8 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_49_REG_OFFSET 0xcc + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_50_REG_OFFSET 0xd0 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_51_REG_OFFSET 0xd4 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_52_REG_OFFSET 0xd8 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_53_REG_OFFSET 0xdc + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_54_REG_OFFSET 0xe0 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_55_REG_OFFSET 0xe4 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_56_REG_OFFSET 0xe8 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_57_REG_OFFSET 0xec + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_58_REG_OFFSET 0xf0 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_59_REG_OFFSET 0xf4 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_60_REG_OFFSET 0xf8 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_61_REG_OFFSET 0xfc + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_62_REG_OFFSET 0x100 + +// Wake Up Tile Register +#define CONTROL_REGISTERS_WAKE_UP_TILE_63_REG_OFFSET 0x104 + // Wake Up Group Register -#define CONTROL_REGISTERS_WAKE_UP_GROUP_REG_OFFSET 0x28 +#define CONTROL_REGISTERS_WAKE_UP_GROUP_REG_OFFSET 0x108 + +// Wake Up Cluster Register +#define CONTROL_REGISTERS_WAKE_UP_CLUSTER_REG_OFFSET 0x10c // TCDM Start Address Register -#define CONTROL_REGISTERS_TCDM_START_ADDRESS_REG_OFFSET 0x2c +#define CONTROL_REGISTERS_TCDM_START_ADDRESS_REG_OFFSET 0x110 // TCDM End Address Register -#define CONTROL_REGISTERS_TCDM_END_ADDRESS_REG_OFFSET 0x30 +#define CONTROL_REGISTERS_TCDM_END_ADDRESS_REG_OFFSET 0x114 // Number of Cores Register -#define CONTROL_REGISTERS_NR_CORES_REG_REG_OFFSET 0x34 +#define CONTROL_REGISTERS_NR_CORES_REG_REG_OFFSET 0x118 // Read-only cache Enable -#define CONTROL_REGISTERS_RO_CACHE_ENABLE_REG_OFFSET 0x38 +#define CONTROL_REGISTERS_RO_CACHE_ENABLE_REG_OFFSET 0x11c // Read-only cache Flush -#define CONTROL_REGISTERS_RO_CACHE_FLUSH_REG_OFFSET 0x3c +#define CONTROL_REGISTERS_RO_CACHE_FLUSH_REG_OFFSET 0x120 // Read-only cache Region Start (common parameters) #define CONTROL_REGISTERS_RO_CACHE_START_RO_CACHE_START_FIELD_WIDTH 32 @@ -81,16 +252,16 @@ extern "C" { #define CONTROL_REGISTERS_RO_CACHE_START_MULTIREG_COUNT 4 // Read-only cache Region Start -#define CONTROL_REGISTERS_RO_CACHE_START_0_REG_OFFSET 0x40 +#define CONTROL_REGISTERS_RO_CACHE_START_0_REG_OFFSET 0x124 // Read-only cache Region Start -#define CONTROL_REGISTERS_RO_CACHE_START_1_REG_OFFSET 0x44 +#define CONTROL_REGISTERS_RO_CACHE_START_1_REG_OFFSET 0x128 // Read-only cache Region Start -#define CONTROL_REGISTERS_RO_CACHE_START_2_REG_OFFSET 0x48 +#define CONTROL_REGISTERS_RO_CACHE_START_2_REG_OFFSET 0x12c // Read-only cache Region Start -#define CONTROL_REGISTERS_RO_CACHE_START_3_REG_OFFSET 0x4c +#define CONTROL_REGISTERS_RO_CACHE_START_3_REG_OFFSET 0x130 // Read-only cache Region End (common parameters) #define CONTROL_REGISTERS_RO_CACHE_END_RO_CACHE_END_FIELD_WIDTH 32 @@ -98,16 +269,16 @@ extern "C" { #define CONTROL_REGISTERS_RO_CACHE_END_MULTIREG_COUNT 4 // Read-only cache Region End -#define CONTROL_REGISTERS_RO_CACHE_END_0_REG_OFFSET 0x50 +#define CONTROL_REGISTERS_RO_CACHE_END_0_REG_OFFSET 0x134 // Read-only cache Region End -#define CONTROL_REGISTERS_RO_CACHE_END_1_REG_OFFSET 0x54 +#define CONTROL_REGISTERS_RO_CACHE_END_1_REG_OFFSET 0x138 // Read-only cache Region End -#define CONTROL_REGISTERS_RO_CACHE_END_2_REG_OFFSET 0x58 +#define CONTROL_REGISTERS_RO_CACHE_END_2_REG_OFFSET 0x13c // Read-only cache Region End -#define CONTROL_REGISTERS_RO_CACHE_END_3_REG_OFFSET 0x5c +#define CONTROL_REGISTERS_RO_CACHE_END_3_REG_OFFSET 0x140 #ifdef __cplusplus } // extern "C" From db5b2753cb87639a3baa0c0ca4e7c99198e054d1 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 10 Jun 2024 12:19:10 +0200 Subject: [PATCH 12/14] [hardware] Fix L2 interconnect for multicluster --- config/mempool.mk | 5 +- config/minpool.mk | 5 +- config/systolic.mk | 3 + config/terapool.mk | 5 +- hardware/Makefile | 1 + .../idma/src/frontends/mempool/mempool_dma.sv | 23 ++++ hardware/src/mempool_pkg.sv | 7 +- hardware/src/mempool_system.sv | 109 +++++++++++++----- hardware/src/mempool_tile.sv | 2 +- hardware/tb/mempool_tb.sv | 14 +-- 10 files changed, 129 insertions(+), 45 deletions(-) diff --git a/config/mempool.mk b/config/mempool.mk index 87d616afd..918a2661c 100644 --- a/config/mempool.mk +++ b/config/mempool.mk @@ -30,9 +30,12 @@ axi_hier_radix ?= 17 # Number of AXI masters per group axi_masters_per_group ?= 1 +# Numer of AXI masters for all clusters +axi_masters_all_clusters ?= 4 + # Number of DMA backends in each group dmas_per_group ?= 1 # Brust Length = 16 # L2 Banks/Channels l2_size ?= 4194304 # 400000 -l2_banks ?= 4 \ No newline at end of file +l2_banks ?= 4 diff --git a/config/minpool.mk b/config/minpool.mk index f6394f448..d421318b5 100644 --- a/config/minpool.mk +++ b/config/minpool.mk @@ -39,9 +39,12 @@ axi_hier_radix ?= 2 # Number of AXI masters per group axi_masters_per_group ?= 1 +# Numer of AXI masters for all clusters +axi_masters_all_clusters ?= 4 + # Number of DMA backends in each group dmas_per_group ?= 1 # Brust Length = 16 # L2 Banks/Channels l2_size ?= 4194304 # 400000 -l2_banks ?= 4 \ No newline at end of file +l2_banks ?= 4 diff --git a/config/systolic.mk b/config/systolic.mk index 502df9bac..6f9189a69 100644 --- a/config/systolic.mk +++ b/config/systolic.mk @@ -28,6 +28,9 @@ axi_hier_radix ?= 20 # Number of AXI masters per group axi_masters_per_group ?= 1 +# Numer of AXI masters for all clusters +axi_masters_all_clusters ?= 4 + # Size of sequential memory per core (in bytes) # (must be a power of two) seq_mem_size ?= 1024 diff --git a/config/terapool.mk b/config/terapool.mk index 0f1c264f8..04a6d7abd 100644 --- a/config/terapool.mk +++ b/config/terapool.mk @@ -40,9 +40,12 @@ axi_hier_radix ?= 9 # Number of AXI masters per group axi_masters_per_group ?= 4 +# Numer of AXI masters for all clusters +axi_masters_all_clusters ?= 16 + # Number of DMA backends in each group dmas_per_group ?= 4 # Brust Length = 16 # L2 Banks/Channels l2_banks = 16 -l2_size ?= 16777216 # 1000000 \ No newline at end of file +l2_size ?= 16777216 # 1000000 diff --git a/hardware/Makefile b/hardware/Makefile index 4f373aad1..0cfba2506 100644 --- a/hardware/Makefile +++ b/hardware/Makefile @@ -132,6 +132,7 @@ vlog_defs += -DRO_LINE_WIDTH=$(ro_line_width) vlog_defs += -DDMAS_PER_GROUP=$(dmas_per_group) vlog_defs += -DAXI_HIER_RADIX=$(axi_hier_radix) vlog_defs += -DAXI_MASTERS_PER_GROUP=$(axi_masters_per_group) +vlog_defs += -DAXI_MASTERS_ALL_CLUSTERS=$(axi_masters_all_clusters) # Systolic configurations vlog_defs += -DSEQ_MEM_SIZE=$(seq_mem_size) vlog_defs += -DXQUEUE_SIZE=$(xqueue_size) diff --git a/hardware/deps/idma/src/frontends/mempool/mempool_dma.sv b/hardware/deps/idma/src/frontends/mempool/mempool_dma.sv index 0b0c4c06b..f77f9035a 100644 --- a/hardware/deps/idma/src/frontends/mempool/mempool_dma.sv +++ b/hardware/deps/idma/src/frontends/mempool/mempool_dma.sv @@ -11,6 +11,7 @@ module mempool_dma #( parameter int unsigned AddrWidth = 32, parameter int unsigned DataWidth = 32, parameter int unsigned NumBackends = 1, + parameter int unsigned DmaReportID = 0, /// AXI4+ATOP request struct definition. parameter type axi_lite_req_t = logic, /// AXI4+ATOP response struct definition. @@ -137,6 +138,7 @@ module mempool_dma #( assign dma_id_o = '0; // pragma translate_off + integer poll; integer cycle; integer transfer; integer size; @@ -144,6 +146,27 @@ module mempool_dma #( string str; /* verilator lint_off BLKSEQ */ + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + poll = 0; + end else begin + if (valid_o && ready_i) begin + $timeformat(-9, 0, " ns", 0); + $display("[DMA %d] Launch %t", DmaReportID, $time); + poll = 0; + end + if (trans_complete_i) begin + $timeformat(-9, 0, " ns", 0); + $display("[DMA %d] Complete %t", DmaReportID, $time); + end + if (config_req_i.ar_valid && config_res_o.ar_ready && poll == 0) begin + $timeformat(-9, 0, " ns", 0); + $display("[DMA %d] Poll %t", DmaReportID, $time); + poll = 1; + end + end + end + always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin cycle = 0; diff --git a/hardware/src/mempool_pkg.sv b/hardware/src/mempool_pkg.sv index d45a0bd08..7e2de62d9 100644 --- a/hardware/src/mempool_pkg.sv +++ b/hardware/src/mempool_pkg.sv @@ -19,7 +19,7 @@ package mempool_pkg; localparam integer unsigned NumDivsqrtPerTile = `ifdef NUM_DIVSQRT_PER_TILE `NUM_DIVSQRT_PER_TILE `else (snitch_pkg::XDIVSQRT) `endif; localparam integer unsigned NumGroups = `ifdef NUM_GROUPS `NUM_GROUPS `else 0 `endif; localparam integer unsigned NumClusters = `ifdef NUM_CLUSTERS `NUM_CLUSTERS `else 0 `endif; - localparam integer unsigned MAX_NumGroups = 32; + localparam integer unsigned MAX_NumGroups = 64; localparam integer unsigned NumGroupsPerCluster = NumGroups / NumClusters; localparam integer unsigned NumTiles = NumCores / NumCoresPerTile; localparam integer unsigned NumTilesPerCluster = NumTiles / NumClusters; @@ -106,10 +106,11 @@ package mempool_pkg; endfunction `endif - localparam integer unsigned NumAXIMastersPerGroup = `ifdef AXI_MASTERS_PER_GROUP `AXI_MASTERS_PER_GROUP `else 1 `endif;; + localparam integer unsigned NumAXIMastersPerGroup = `ifdef AXI_MASTERS_PER_GROUP `AXI_MASTERS_PER_GROUP `else 1 `endif; localparam integer unsigned NumAXIMastersPerCluster = NumAXIMastersPerGroup * NumGroupsPerCluster; + localparam integer unsigned NumAXIMastersAllClusters = `ifdef AXI_MASTERS_ALL_CLUSTERS `AXI_MASTERS_ALL_CLUSTERS `else 1 `endif; - localparam NumSystemXbarMasters = (NumGroups * NumAXIMastersPerGroup) + 1; // +1 because the external host is also a master + localparam NumSystemXbarMasters = (NumAXIMastersAllClusters) + 1; // +1 because the external host is also a master localparam AxiSystemIdWidth = $clog2(NumSystemXbarMasters) + AxiTileIdWidth; typedef logic [AxiSystemIdWidth-1:0] axi_system_id_t; diff --git a/hardware/src/mempool_system.sv b/hardware/src/mempool_system.sv index b4afb6b4c..4522f6461 100644 --- a/hardware/src/mempool_system.sv +++ b/hardware/src/mempool_system.sv @@ -29,6 +29,7 @@ module mempool_system import axi_pkg::xbar_cfg_t; import axi_pkg::xbar_rule_32_t; + import cf_math_pkg::idx_width; `include "reqrsp_interface/typedef.svh" @@ -79,6 +80,8 @@ module mempool_system L2Memory = 1 } axi_mst_demux_slave_target; + axi_tile_req_t [NumClusters*NumAXIMastersPerCluster-1:0] axi_cluster_req; + axi_tile_resp_t [NumClusters*NumAXIMastersPerCluster-1:0] axi_cluster_resp; axi_tile_req_t [NumAXIMasters-1:0] axi_mst_req; axi_tile_resp_t [NumAXIMasters-1:0] axi_mst_resp; axi_tile_req_t [NumAXIMasters-1:0] axi_l2_req; @@ -133,34 +136,63 @@ module mempool_system * MemPool Cluster * ********************/ for (genvar i = 0; i < NumClusters; i++) begin : gen_clusters + logic [idx_width(NumClusters)-1:0] cluster_id = i; mempool_cluster #( .TCDMBaseAddr(i*L1SizePerCluster), // TODO: i*L1SizePerCluster .BootAddr (BootAddr ) ) i_mempool_cluster ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .cluster_id_i (i ), - .wake_up_i (wake_up[i*NumCoresPerCluster+:NumCoresPerCluster] ), - .testmode_i (1'b0 ), - .scan_enable_i (1'b0 ), - .scan_data_i (1'b0 ), - .scan_data_o (/* Unused */ ), - .ro_cache_ctrl_i(ro_cache_ctrl ), - .dma_req_i (dma_req[i] ), - .dma_req_valid_i(dma_req_valid[i] ), - .dma_req_ready_o(dma_req_ready[i] ), - .dma_meta_o (dma_meta[i] ), - .axi_mst_req_o (axi_mst_req[i*NumAXIMastersPerCluster+:NumAXIMastersPerCluster] ), - .axi_mst_resp_i (axi_mst_resp[i*NumAXIMastersPerCluster+:NumAXIMastersPerCluster]) + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .cluster_id_i (cluster_id ), + .wake_up_i (wake_up[i*NumCoresPerCluster+:NumCoresPerCluster] ), + .testmode_i (1'b0 ), + .scan_enable_i (1'b0 ), + .scan_data_i (1'b0 ), + .scan_data_o (/* Unused */ ), + .ro_cache_ctrl_i(ro_cache_ctrl ), + .dma_req_i (dma_req[i] ), + .dma_req_valid_i(dma_req_valid[i] ), + .dma_req_ready_o(dma_req_ready[i] ), + .dma_meta_o (dma_meta[i] ), + .axi_mst_req_o (axi_cluster_req[i*NumAXIMastersPerCluster+:NumAXIMastersPerCluster] ), + .axi_mst_resp_i (axi_cluster_resp[i*NumAXIMastersPerCluster+:NumAXIMastersPerCluster]) ); end + axi_hier_interco #( + .NumSlvPorts (NumAXIMastersPerCluster*NumClusters ), + .NumMstPorts (NumAXIMastersAllClusters ), + .Radix ((NumAXIMastersPerCluster*NumClusters)/NumAXIMastersAllClusters), + .EnableCache (32'h00000000 ), + .CacheLineWidth (ROCacheLineWidth ), + .CacheSizeByte (ROCacheSizeByte ), + .CacheSets (ROCacheSets ), + .AddrWidth (AddrWidth ), + .DataWidth (AxiDataWidth ), + .SlvIdWidth (AxiTileIdWidth ), + .MstIdWidth (AxiTileIdWidth ), + .UserWidth (1 ), + .slv_req_t (axi_tile_req_t ), + .slv_resp_t (axi_tile_resp_t ), + .mst_req_t (axi_tile_req_t ), + .mst_resp_t (axi_tile_resp_t ) + ) i_axi_interco ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .test_i (1'b0 ), + .ro_cache_ctrl_i (ro_cache_ctrl ), + .slv_req_i (axi_cluster_req ), + .slv_resp_o (axi_cluster_resp ), + .mst_req_o (axi_mst_req[NumAXIMastersAllClusters-1:0] ), + .mst_resp_i (axi_mst_resp[NumAXIMastersAllClusters-1:0]) + ); + /********************** * AXI Interconnect * **********************/ localparam addr_t PeripheralsBaseAddr = 32'h4000_0000; - localparam addr_t PeripheralsEndAddr = 32'h4002_0000; + localparam addr_t PeripheralsEndAddr = 32'h6000_0000; localparam addr_t L2MemoryBaseAddr = `ifdef L2_BASE `L2_BASE `else 32'h8000_0000 `endif; localparam addr_t L2MemoryEndAddr = L2MemoryBaseAddr + L2Size; localparam addr_t BootromBaseAddr = 32'hA000_0000; @@ -254,6 +286,8 @@ module mempool_system typedef logic [NumL2BanksWidth-1:0] l2_bank_idx_t; axi_to_l2_req_chan_t [NumAXIMasters-1:0] axi_to_l2_req_chan; axi_to_l2_rsp_chan_t [NumAXIMasters-1:0] axi_to_l2_rsp_chan; + logic [NumAXIMasters-1:0] axi_to_l2_q_throttle_valid; + logic [NumAXIMasters-1:0] axi_to_l2_q_throttle_ready; logic [NumAXIMasters-1:0] axi_to_l2_q_valid; logic [NumAXIMasters-1:0] axi_to_l2_q_ready; l2_bank_idx_t [NumAXIMasters-1:0] axi_to_l2_q_sel; @@ -283,7 +317,7 @@ module mempool_system .AddrWidth (L2AddrWidth ), .DataWidth (AxiDataWidth ), .IdWidth (AxiTileIdWidth ), - .BufDepth (0 ), + .BufDepth (2 ), .reqrsp_req_t (axi_to_l2_req_t), .reqrsp_rsp_t (axi_to_l2_rsp_t) ) i_axi_to_reqrsp ( @@ -304,6 +338,20 @@ module mempool_system assign axi_to_l2_p_ready[i] = axi_to_l2_req[i].p_ready; // Generate the selection signal assign axi_to_l2_q_sel[i] = axi_to_l2_req_chan[i].addr[$clog2(L2BankBeWidth)+:NumL2BanksWidth]; + // Throttle the to one oustanding transaction to avoid reordering without a ROB + stream_throttle #( + .MaxNumPending (1) + ) i_stream_throttle ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .req_valid_i (axi_to_l2_q_valid[i] ), + .req_valid_o (axi_to_l2_q_throttle_valid[i]), + .req_ready_i (axi_to_l2_q_throttle_ready[i]), + .req_ready_o (axi_to_l2_q_ready[i] ), + .rsp_valid_i (axi_to_l2_p_valid[i] ), + .rsp_ready_i (axi_to_l2_p_ready[i] ), + .credit_i (1'b1 ) + ); end stream_xbar #( @@ -315,18 +363,18 @@ module mempool_system .AxiVldRdy (1'b1 ), .LockIn (1'b1 ) ) i_l2_req_xbar ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .flush_i (1'b0 ), - .rr_i ('0 ), - .data_i (axi_to_l2_req_chan), - .sel_i (axi_to_l2_q_sel ), - .valid_i (axi_to_l2_q_valid ), - .ready_o (axi_to_l2_q_ready ), - .data_o (mem_req_chan ), - .idx_o (axi_to_l2_q_idx ), - .valid_o (mem_req_valid ), - .ready_i (mem_req_ready ) + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .flush_i (1'b0 ), + .rr_i ('0 ), + .data_i (axi_to_l2_req_chan ), + .sel_i (axi_to_l2_q_sel ), + .valid_i (axi_to_l2_q_throttle_valid), + .ready_o (axi_to_l2_q_throttle_ready), + .data_o (mem_req_chan ), + .idx_o (axi_to_l2_q_idx ), + .valid_o (mem_req_valid ), + .ready_i (mem_req_ready ) ); stream_xbar #( @@ -773,7 +821,7 @@ module mempool_system .mst_ports_req_o (axi_lite_slv_req ), .mst_ports_resp_i (axi_lite_slv_resp ), .addr_map_i (axi_lite_xbar_rules), - .en_default_mst_port_i('1 ), + .en_default_mst_port_i(1'b1 ), .default_mst_port_i (CtrlRegisters ) ); @@ -796,6 +844,7 @@ module mempool_system for (genvar i = 0; i < NumClusters; i++) begin : gen_mempool_dma mempool_dma #( + .DmaReportID (i ), .axi_lite_req_t(axi_lite_slv_req_t ), .axi_lite_rsp_t(axi_lite_slv_resp_t ), .burst_req_t (dma_req_t ), diff --git a/hardware/src/mempool_tile.sv b/hardware/src/mempool_tile.sv index 6a5596213..479c8123c 100644 --- a/hardware/src/mempool_tile.sv +++ b/hardware/src/mempool_tile.sv @@ -796,7 +796,7 @@ module mempool_tile // Highest priority: send request through the local TCDM port '{slave_idx: TCDM_LOCAL, mask : TCDMMask | ({idx_width(NumTilesPerCluster){1'b1}} << (ByteOffset + $clog2(NumBanksPerTile))), - value : TCDMBaseAddr | (tile_id_i << (ByteOffset + $clog2(NumBanksPerTile))) + value : TCDMBaseAddr | (tile_id_i[idx_width(NumTilesPerCluster)-1:0] << (ByteOffset + $clog2(NumBanksPerTile))) } }; diff --git a/hardware/tb/mempool_tb.sv b/hardware/tb/mempool_tb.sv index 8c9a50663..282782874 100644 --- a/hardware/tb/mempool_tb.sv +++ b/hardware/tb/mempool_tb.sv @@ -492,17 +492,15 @@ module mempool_tb; end // AXI - logic [NumGroups*NumAXIMastersPerGroup-1:0] w_valid, w_ready, r_ready, r_valid; + logic [NumAXIMastersAllClusters-1:0] w_valid, w_ready, r_ready, r_valid; int unsigned axi_w_utilization, axi_r_utilization; assign axi_w_utilization = $countones(w_valid & w_ready); assign axi_r_utilization = $countones(r_ready & r_valid); - for (genvar cl = 0; cl < NumClusters; cl++) begin - for (genvar a = 0; a < NumGroupsPerCluster*NumAXIMastersPerGroup; a++) begin - assign w_valid[cl*NumGroupsPerCluster*NumAXIMastersPerGroup+a] = dut.gen_clusters[cl].i_mempool_cluster.axi_mst_req_o[a].w_valid; - assign w_ready[cl*NumGroupsPerCluster*NumAXIMastersPerGroup+a] = dut.gen_clusters[cl].i_mempool_cluster.axi_mst_resp_i[a].w_ready; - assign r_ready[cl*NumGroupsPerCluster*NumAXIMastersPerGroup+a] = dut.gen_clusters[cl].i_mempool_cluster.axi_mst_req_o[a].r_ready; - assign r_valid[cl*NumGroupsPerCluster*NumAXIMastersPerGroup+a] = dut.gen_clusters[cl].i_mempool_cluster.axi_mst_resp_i[a].r_valid; - end + for (genvar a = 0; a < NumAXIMastersAllClusters; a++) begin + assign w_valid[a] = dut.axi_mst_req[a].w_valid; + assign w_ready[a] = dut.axi_mst_resp[a].w_ready; + assign r_ready[a] = dut.axi_mst_req[a].r_ready; + assign r_valid[a] = dut.axi_mst_resp[a].r_valid; end `endif From 2b0d0ef18bed648ce34fae2a8ea41e3fdfb785d2 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 10 Jun 2024 12:20:48 +0200 Subject: [PATCH 13/14] [hardware] Extend waves for multicluster --- hardware/scripts/questa/wave.tcl | 37 +- hardware/scripts/questa/wave_core.tcl | 508 +++++++++----------------- 2 files changed, 192 insertions(+), 353 deletions(-) diff --git a/hardware/scripts/questa/wave.tcl b/hardware/scripts/questa/wave.tcl index 5b10c1483..640b13420 100644 --- a/hardware/scripts/questa/wave.tcl +++ b/hardware/scripts/questa/wave.tcl @@ -20,7 +20,7 @@ if {[examine -radix dec /snitch_pkg::XPULPIMG]} { add wave -noupdate -group Utilization -color {Cornflower Blue} -format Analog-Step -height 84 -max $num_cores -radix unsigned /mempool_tb/gen_utilization/mac_utilization add wave -noupdate -group Utilization /mempool_tb/gen_utilization/dspu_mac } -set axi_channels [expr [examine -radix dec mempool_pkg::NumGroups] * [examine -radix dec mempool_pkg::NumAXIMastersPerGroup]] +set axi_channels [examine -radix dec mempool_pkg::NumAXIMastersAllClusters] add wave -noupdate -group Utilization -color {Cornflower Blue} -format Analog-Step -height 84 -max $axi_channels -radix unsigned /mempool_tb/axi_w_utilization add wave -noupdate -group Utilization -color {Cornflower Blue} -format Analog-Step -height 84 -max $axi_channels -radix unsigned /mempool_tb/axi_r_utilization @@ -28,39 +28,27 @@ add wave -noupdate -group Utilization -color {Cornflower Blue} -format Analog-St # Add a vector of the core's wfi signal to quickly see which cores are active add wave /mempool_tb/wfi -# Add all cores from group 0 tile 0 -for {set core 0} {$core < [examine -radix dec mempool_pkg::NumCoresPerTile]} {incr core} { - if {$config == {terapool}} { - do ../scripts/questa/wave_core.tcl 0 0 0 0 $core - } else { - do ../scripts/questa/wave_core.tcl 0 0 0 $core - } -} - -# Add specific cores from different tiles -if {$config == {terapool}} { - do ../scripts/questa/wave_core.tcl 0 1 0 0 0 -} else { - do ../scripts/questa/wave_core.tcl 0 1 0 0 -} - # Add groups for {set cluster 0} {$cluster < [examine -radix dec /mempool_pkg::NumClusters]} {incr cluster} { # Add cluster do ../scripts/questa/wave_cluster.tcl $cluster - add wave -Group cluster_[$cluster] -Group dma /mempool_tb/dut/gen_mempool_dma[$cluster]/i_mempool_dma/* - add wave -Group cluster_[$cluster] -Group dma -Group reg /mempool_tb/dut/gen_mempool_dma[$cluster]/i_mempool_dma/i_mempool_dma_frontend_reg_top/* # Add groups for {set group 0} {$group < [examine -radix dec /mempool_pkg::NumGroupsPerCluster]} {incr group} { # Add tiles if {$config == {terapool}} { for {set subgroup 0} {$subgroup < [expr min(4,[examine -radix dec /mempool_pkg::NumSubGroupsPerGroup])]} {incr subgroup} { for {set tile 0} {$tile < [expr min(4,[examine -radix dec /mempool_pkg::NumTilesPerSubGroup])]} {incr tile} { + for {set core 0} {$core < [expr min(4,[examine -radix dec /mempool_pkg::NumCoresPerTile])]} {incr core} { + do ../scripts/questa/wave_core.tcl $cluster $group $subgroup $tile $core + } do ../scripts/questa/wave_tile.tcl $cluster $group $subgroup $tile } } } else { for {set tile 0} {$tile < [expr min(4,[examine -radix dec /mempool_pkg::NumTilesPerGroup])]} {incr tile} { + for {set core 0} {$core < [expr min(4,[examine -radix dec /mempool_pkg::NumCoresPerTile])]} {incr core} { + do ../scripts/questa/wave_core.tcl $cluster $group $tile $core + } do ../scripts/questa/wave_tile.tcl $cluster $group $tile } } @@ -80,10 +68,21 @@ for {set cluster 0} {$cluster < [examine -radix dec /mempool_pkg::NumClusters]} add wave -group cluster_[$cluster] -group group_[$group] -group interconnect_local /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/i_group/i_local_interco/* } } + add wave -Group cluster_[$cluster] -Group dma /mempool_tb/dut/gen_mempool_dma[$cluster]/i_mempool_dma/* + add wave -Group cluster_[$cluster] -Group dma -Group reg /mempool_tb/dut/gen_mempool_dma[$cluster]/i_mempool_dma/i_mempool_dma_frontend_reg_top/* } add wave -Group Control_Registers /mempool_tb/dut/i_ctrl_registers/* +add wave -Group hier_interco /mempool_tb/dut/i_axi_interco/clk_i +add wave -Group hier_interco /mempool_tb/dut/i_axi_interco/rst_ni +add wave -Group hier_interco /mempool_tb/dut/i_axi_interco/test_i +add wave -Group hier_interco /mempool_tb/dut/i_axi_interco/ro_cache_ctrl_i +add wave -Group hier_interco /mempool_tb/dut/i_axi_interco/slv_req_i +add wave -Group hier_interco /mempool_tb/dut/i_axi_interco/slv_resp_o +add wave -Group hier_interco /mempool_tb/dut/i_axi_interco/mst_req_o +add wave -Group hier_interco /mempool_tb/dut/i_axi_interco/mst_resp_i + # for {set group 0} {$group < [examine -radix dec /mempool_pkg::NumGroups]} {incr group} { # if {$config == {terapool}} { # add wave -Group DMA_midend_${group} /mempool_tb/dut/gen_clusters[$cluster]/i_mempool_cluster/gen_groups[$group]/gen_rtl_group/i_group/i_idma_distributed_midend/NoMstPorts diff --git a/hardware/scripts/questa/wave_core.tcl b/hardware/scripts/questa/wave_core.tcl index 8776f74f0..b277ff8f6 100644 --- a/hardware/scripts/questa/wave_core.tcl +++ b/hardware/scripts/questa/wave_core.tcl @@ -4,339 +4,179 @@ # Create group for core $3 from group $1 tile $2 (core_id=NUM_CORES_PER_group*$1+NUM_CORES_PER_TILE*$2+$3) if {$config == {terapool}} { - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/BootAddr - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/MTVEC - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RVE - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RVM - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RegisterOffloadReq - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RegisterOffloadResp - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RegisterTCDMReq - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/RegisterTCDMResp - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/clk_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rst_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] -radix unsigned /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/hart_id_i - - add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider Instructions - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/inst_addr_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/inst_data_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/inst_valid_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/inst_ready_i - - add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider Load/Store - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qaddr_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qwrite_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qamo_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qdata_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qstrb_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qvalid_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_qready_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_pdata_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_perror_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_pvalid_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/data_pready_o - - add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider Accelerator - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qaddr_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qid_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_op_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_arga_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argb_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argc_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qvalid_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_qready_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_pdata_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_pid_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_perror_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_pvalid_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_pready_o - - add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider FPSS - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_valid_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_ready_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_valid_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_ready_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] -divider FPU - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/operands_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/rnd_mode_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_mod_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/src_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/dst_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/int_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/vectorial_op_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_valid_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_ready_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/result_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/status_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_valid_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_ready_i - - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/illegal_inst - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/stall - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_stall - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_stall - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/fence_stall - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/zero_lsb - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/pc_d - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/pc_q - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wfi_d - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wfi_q - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wake_up_sync_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wake_up_d - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/wake_up_q - - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal -divider LSU - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ls_size - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ls_amo - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ld_result - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_qready - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_qvalid - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_pvalid - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_pready - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_rd - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/lsu_empty - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/retire_load - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/retire_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/retire_acc - - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal -divider Register - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/raddr_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/waddr_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/wdata_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/we_i - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/rdata_o - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/mem - - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal -divider ALU - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opa - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opb - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/iimm - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/uimm - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/jimm - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/bimm - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/simm - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/adder_result - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_result - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rd - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rs1 - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rs2 - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_raddr - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_rdata - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_waddr - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_wdata - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/gpr_we - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/consec_pc - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/sb_d - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/sb_q - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_load - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_store - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_signed - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_fp_load - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_fp_store - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ls_misaligned - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/ld_addr_misaligned - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/st_addr_misaligned - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/valid_instr - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/exception - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_op - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opa_select - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opb_select - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/write_rd - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/uses_rd - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/next_pc - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rd_select - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/rd_bypass - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/is_branch - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/csr_rvalue - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/csr_en - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/cycle_q - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/instret_q - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/acc_register_rd - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/operands_ready - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/dst_ready - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opa_ready - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/opb_ready - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_opa - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_reversed - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_left_result - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_ext - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result_ext - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_left - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/shift_arithmetic - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_opa - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_opb - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/alu_writeback - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_q - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_en - add wave -noupdate -group core[$1][$2][$3][$4][$5] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core/i_snitch/core_events_o + set path "/mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/gen_rtl_group/i_group/gen_sub_groups[$3]/gen_rtl_sg/i_sub_group/gen_tiles[$4]/i_tile/gen_cores[$5]/gen_mempool_cc/riscv_core" + set group "-group cluster_[$1] -group group_[$2] -group sub_group_[$3] -group tile_[$4] -group core_[$5]" + set WhyDoesModelsimSpamTheLastVariableIDefine "" } else { - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/BootAddr - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/MTVEC - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RVE - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RVM - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterOffloadReq - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterOffloadResp - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterTCDMReq - add wave -noupdate -group core[$1][$2][$3][$4] -group Params /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/RegisterTCDMResp - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/clk_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rst_i - add wave -noupdate -group core[$1][$2][$3][$4] -radix unsigned /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/hart_id_i - - add wave -noupdate -group core[$1][$2][$3][$4] -divider Instructions - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_addr_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_data_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_valid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/inst_ready_i - - add wave -noupdate -group core[$1][$2][$3][$4] -divider Load/Store - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qaddr_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qwrite_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qamo_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qdata_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qstrb_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qvalid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_qready_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pdata_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_perror_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pvalid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/data_pready_o - - add wave -noupdate -group core[$1][$2][$3][$4] -divider Accelerator - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qaddr_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_op_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_arga_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argb_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qdata_argc_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qvalid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_qready_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pdata_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_perror_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pvalid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_pready_o - - add wave -noupdate -group core[$1][$2][$3][$4] -divider FPSS - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_valid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_req_ready_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_valid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/acc_resp_ready_i - add wave -noupdate -group core[$1][$2][$3][$4] -divider FPU - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/operands_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/rnd_mode_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/op_mod_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/src_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/dst_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/int_fmt_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/vectorial_op_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_valid_i - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/in_ready_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/result_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/status_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/tag_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_valid_o - add wave -noupdate -group core[$1][$2][$3][$4] /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/gen_fpu/i_snitch_fp_ss/i_fpu/out_ready_i - - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/illegal_inst - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/stall - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_stall - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_stall - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/zero_lsb - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/pc_d - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/pc_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wfi_d - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wfi_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_sync_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_d - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/wake_up_q - - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider LSU - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_size - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_amo - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ld_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_qready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_qvalid - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_pvalid - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_pready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/lsu_rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_load - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/retire_acc - - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider Register - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/raddr_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/waddr_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/wdata_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/we_i - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/rdata_o - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/i_snitch_regfile/mem - - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal -divider ALU - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/iimm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/uimm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/jimm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/bimm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/simm - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/adder_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rs1 - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rs2 - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_raddr - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_rdata - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_waddr - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_wdata - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/gpr_we - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/consec_pc - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/sb_d - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/sb_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_load - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_store - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_signed - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_fp_load - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_fp_store - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ls_misaligned - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/ld_addr_misaligned - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/st_addr_misaligned - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/valid_instr - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/exception - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_op - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa_select - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb_select - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/write_rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/uses_rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/next_pc - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd_select - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/rd_bypass - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/is_branch - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_rvalue - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_en - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/cycle_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/instret_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/acc_register_rd - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/operands_ready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/dst_ready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opa_ready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/opb_ready - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_reversed - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_left_result - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_opa_ext - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_right_result_ext - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_left - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/shift_arithmetic - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_opa - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_opb - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/alu_writeback - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_q - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/csr_trace_en - add wave -noupdate -group core[$1][$2][$3][$4] -group Internal /mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core/i_snitch/core_events_o + set prefix "/mempool_tb/dut/gen_clusters[$1]/i_mempool_cluster/gen_groups[$2]/i_group/gen_tiles[$3]/i_tile/gen_cores[$4]/gen_mempool_cc/riscv_core" + set groups "-group cluster_[$1] -group group_[$2] -group tile_[$3] -group core_[$4]" + set WhyDoesModelsimSpamTheLastVariableIDefine "" } + +{*}"add wave -noupdate $groups -group Params $prefix/BootAddr" +{*}"add wave -noupdate $groups -group Params $prefix/MTVEC" +{*}"add wave -noupdate $groups -group Params $prefix/RVE" +{*}"add wave -noupdate $groups -group Params $prefix/RVM" +{*}"add wave -noupdate $groups -group Params $prefix/RegisterOffloadReq" +{*}"add wave -noupdate $groups -group Params $prefix/RegisterOffloadResp" +{*}"add wave -noupdate $groups -group Params $prefix/RegisterTCDMReq" +{*}"add wave -noupdate $groups -group Params $prefix/RegisterTCDMResp" +{*}"add wave -noupdate $groups $prefix/i_snitch/clk_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/rst_i" +{*}"add wave -noupdate $groups -radix unsigned $prefix/i_snitch/hart_id_i" + +{*}"add wave -noupdate $groups -divider Instructions" +{*}"add wave -noupdate $groups $prefix/i_snitch/inst_addr_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/inst_data_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/inst_valid_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/inst_ready_i" + +{*}"add wave -noupdate $groups -divider Load/Store" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_qaddr_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_qwrite_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_qamo_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_qdata_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_qstrb_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_qvalid_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_qready_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_pdata_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_perror_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_pvalid_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/data_pready_o" + +{*}"add wave -noupdate $groups -divider FPSS" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/acc_req_valid_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/acc_req_ready_o" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/acc_resp_valid_o" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/acc_resp_ready_i" + +{*}"add wave -noupdate $groups -divider FPU" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/operands_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/rnd_mode_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/op_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/op_mod_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/src_fmt_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/dst_fmt_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/int_fmt_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/vectorial_op_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/tag_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/in_valid_i" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/in_ready_o" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/result_o" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/status_o" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/tag_o" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/out_valid_o" +{*}"add wave -noupdate $groups $prefix/gen_fpu/i_snitch_fp_ss/i_fpu/out_ready_i" + +{*}"add wave -noupdate $groups -divider Accelerator" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_qaddr_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_qid_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_qdata_op_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_qdata_arga_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_qdata_argb_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_qdata_argc_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_qvalid_o" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_qready_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_pdata_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_pid_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_perror_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_pvalid_i" +{*}"add wave -noupdate $groups $prefix/i_snitch/acc_pready_o" + +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/illegal_inst" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/stall" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/lsu_stall" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/acc_stall" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/zero_lsb" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/pc_d" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/pc_q" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/wfi_d" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/wfi_q" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/wake_up_sync_i" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/wake_up_d" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/wake_up_q" + +{*}"add wave -noupdate $groups -group Internal -divider LSU" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/ls_size" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/ls_amo" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/ld_result" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/lsu_qready" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/lsu_qvalid" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/lsu_pvalid" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/lsu_pready" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/lsu_rd" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/retire_load" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/retire_i" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/retire_acc" + +{*}"add wave -noupdate $groups -group Internal -divider Register" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/i_snitch_regfile/raddr_i" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/i_snitch_regfile/waddr_i" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/i_snitch_regfile/wdata_i" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/i_snitch_regfile/we_i" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/i_snitch_regfile/rdata_o" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/i_snitch_regfile/mem" + +{*}"add wave -noupdate $groups -group Internal -divider ALU" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/opa" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/opb" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/iimm" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/uimm" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/jimm" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/bimm" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/simm" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/adder_result" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/alu_result" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/rd" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/rs1" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/rs2" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/gpr_raddr" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/gpr_rdata" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/gpr_waddr" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/gpr_wdata" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/gpr_we" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/consec_pc" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/sb_d" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/sb_q" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/is_load" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/is_store" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/is_signed" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/is_fp_load" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/is_fp_store" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/ls_misaligned" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/ld_addr_misaligned" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/st_addr_misaligned" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/valid_instr" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/exception" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/alu_op" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/opa_select" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/opb_select" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/write_rd" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/uses_rd" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/next_pc" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/rd_select" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/rd_bypass" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/is_branch" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/csr_rvalue" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/csr_en" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/cycle_q" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/instret_q" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/acc_register_rd" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/operands_ready" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/dst_ready" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/opa_ready" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/opb_ready" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/shift_opa" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/shift_opa_reversed" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/shift_right_result" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/shift_left_result" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/shift_opa_ext" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/shift_right_result_ext" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/shift_left" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/shift_arithmetic" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/alu_opa" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/alu_opb" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/alu_writeback" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/csr_trace_q" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/csr_trace_en" +{*}"add wave -noupdate $groups -group Internal $prefix/i_snitch/core_events_o" From c18aea4a8171106a1b4ba1e1c46821f198c52ef4 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Wed, 28 Aug 2024 18:48:06 +0200 Subject: [PATCH 14/14] [software] Adapt runtime to multicluster --- CHANGELOG.md | 1 + .../apps/baremetal/cfft_radix2_q16/main.c | 8 ++-- .../apps/baremetal/cfft_radix4_q16/main.c | 15 ++++--- software/apps/baremetal/chest_q16/main.c | 5 ++- software/apps/baremetal/matmul_f16/main.c | 7 +++- software/apps/baremetal/matmul_f32/main.c | 7 +++- software/runtime/arch.ld.c | 3 ++ software/runtime/dma.h | 41 +++++++++++-------- software/runtime/runtime.h | 40 +++++++++++++++++- software/tests/baremetal/fence/main.c | 11 +++-- software/tests/baremetal/memcpy/main.c | 6 ++- 11 files changed, 105 insertions(+), 39 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 8b316f598..9425ea8f4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Add support for the `FENCE` instruction - Add support for DRAMsys5.0 co-simulation - Add support for atomics in L2 +- Add support for a multi-cluster MemPool ### Changes - Add physical feasible TeraPool configuration with SubGroup hierarchy. diff --git a/software/apps/baremetal/cfft_radix2_q16/main.c b/software/apps/baremetal/cfft_radix2_q16/main.c index 105cf6370..1a660d567 100644 --- a/software/apps/baremetal/cfft_radix2_q16/main.c +++ b/software/apps/baremetal/cfft_radix2_q16/main.c @@ -39,13 +39,15 @@ int main() { uint32_t core_id = mempool_get_core_id(); uint32_t num_cores = mempool_get_core_count(); + uint32_t cluster_id = mempool_get_cluster_id(); mempool_barrier_init(core_id); if (core_id == 0) { - dma_memcpy_blocking(l1_pSrc, l2_pSrc, N_CSAMPLES * sizeof(int32_t)); - dma_memcpy_blocking(l1_twiddleCoef_q16, l2_twiddleCoef_q16, + dma_memcpy_blocking(cluster_id, l1_pSrc, l2_pSrc, + N_CSAMPLES * sizeof(int32_t)); + dma_memcpy_blocking(cluster_id, l1_twiddleCoef_q16, l2_twiddleCoef_q16, (3 * N_CSAMPLES / 4) * sizeof(int32_t)); - dma_memcpy_blocking(l1_BitRevIndexTable, l2_BitRevIndexTable, + dma_memcpy_blocking(cluster_id, l1_BitRevIndexTable, l2_BitRevIndexTable, BITREVINDEXTABLE_LENGTH * sizeof(uint16_t)); } mempool_barrier(num_cores); diff --git a/software/apps/baremetal/cfft_radix4_q16/main.c b/software/apps/baremetal/cfft_radix4_q16/main.c index 88d7182fa..e14440bc8 100644 --- a/software/apps/baremetal/cfft_radix4_q16/main.c +++ b/software/apps/baremetal/cfft_radix4_q16/main.c @@ -73,6 +73,7 @@ uint16_t l1_BitRevIndexTable[BITREVINDEXTABLE_LENGTH] int main() { uint32_t core_id = mempool_get_core_id(); uint32_t num_cores = mempool_get_core_count(); + uint32_t cluster_id = mempool_get_cluster_id(); int16_t *pRes; // Result pointer mempool_barrier_init(core_id); @@ -80,10 +81,11 @@ int main() { #if (defined(SINGLE) || defined(PARALLEL)) if (core_id == 0) { - dma_memcpy_blocking(l1_pSrc, l2_pSrc, N_CSAMPLES * sizeof(int32_t)); - dma_memcpy_blocking(l1_twiddleCoef_q16_src, l2_twiddleCoef_q16, + dma_memcpy_blocking(cluster_id, l1_pSrc, l2_pSrc, + N_CSAMPLES * sizeof(int32_t)); + dma_memcpy_blocking(cluster_id, l1_twiddleCoef_q16_src, l2_twiddleCoef_q16, 3 * (N_CSAMPLES / 4) * sizeof(int32_t)); - dma_memcpy_blocking(l1_BitRevIndexTable, l2_BitRevIndexTable, + dma_memcpy_blocking(cluster_id, l1_BitRevIndexTable, l2_BitRevIndexTable, BITREVINDEXTABLE_LENGTH * sizeof(int16_t)); printf("01: END INITIALIZATION\n"); } @@ -95,11 +97,12 @@ int main() { if (core_id == 0) { for (uint32_t j = 0; j < N_FFTs_ROW; j++) { for (uint32_t i = 0; i < N_FFTs_COL; i++) { - dma_memcpy_blocking(l1_pSrc + i * 2 * N_CSAMPLES + j * (8 * N_BANKS), + dma_memcpy_blocking(cluster_id, + l1_pSrc + i * 2 * N_CSAMPLES + j * (8 * N_BANKS), l2_pSrc, N_CSAMPLES * sizeof(int32_t)); } } - dma_memcpy_blocking(l1_BitRevIndexTable, l2_BitRevIndexTable, + dma_memcpy_blocking(cluster_id, l1_BitRevIndexTable, l2_BitRevIndexTable, BITREVINDEXTABLE_LENGTH * sizeof(int32_t)); } mempool_barrier(num_cores); @@ -118,7 +121,7 @@ int main() { } #else if (core_id == 0) { - dma_memcpy_blocking(l1_twiddleCoef_q16_src, l2_twiddleCoef_q16, + dma_memcpy_blocking(cluster_id, l1_twiddleCoef_q16_src, l2_twiddleCoef_q16, 3 * (N_CSAMPLES / 4) * sizeof(int32_t)); } #endif diff --git a/software/apps/baremetal/chest_q16/main.c b/software/apps/baremetal/chest_q16/main.c index eecac204a..1bb864d65 100644 --- a/software/apps/baremetal/chest_q16/main.c +++ b/software/apps/baremetal/chest_q16/main.c @@ -32,13 +32,14 @@ int main() { uint32_t core_id = mempool_get_core_id(); uint32_t num_cores = mempool_get_core_count(); + uint32_t cluster_id = mempool_get_cluster_id(); mempool_barrier_init(core_id); /* Initialize matrices */ if (core_id == 0) { - dma_memcpy_blocking(l1_PilotRX, l2_PilotRX, + dma_memcpy_blocking(cluster_id, l1_PilotRX, l2_PilotRX, (N_RX * N_SAMPLES) * sizeof(int32_t)); - dma_memcpy_blocking(l1_PilotTX, l2_PilotTX, + dma_memcpy_blocking(cluster_id, l1_PilotTX, l2_PilotTX, (N_TX * N_SAMPLES) * sizeof(int32_t)); } mempool_barrier(num_cores); diff --git a/software/apps/baremetal/matmul_f16/main.c b/software/apps/baremetal/matmul_f16/main.c index b3b474b1d..a57d892ee 100644 --- a/software/apps/baremetal/matmul_f16/main.c +++ b/software/apps/baremetal/matmul_f16/main.c @@ -29,13 +29,16 @@ __fp16 matrix_c[matrix_M * matrix_P] int main() { uint32_t core_id = mempool_get_core_id(); uint32_t num_cores = mempool_get_core_count(); + uint32_t cluster_id = mempool_get_cluster_id(); // Initialize barrier and synchronize mempool_barrier_init(core_id); // Initialize Matrices 1 if (core_id == 0) { - dma_memcpy_blocking(matrix_a, A, (matrix_M * matrix_N) * sizeof(int16_t)); - dma_memcpy_blocking(matrix_b, B, (matrix_N * matrix_P) * sizeof(int16_t)); + dma_memcpy_blocking(cluster_id, matrix_a, A, + (matrix_M * matrix_N) * sizeof(int16_t)); + dma_memcpy_blocking(cluster_id, matrix_b, B, + (matrix_N * matrix_P) * sizeof(int16_t)); } mempool_barrier(num_cores); diff --git a/software/apps/baremetal/matmul_f32/main.c b/software/apps/baremetal/matmul_f32/main.c index bc391200f..5dc695a0e 100644 --- a/software/apps/baremetal/matmul_f32/main.c +++ b/software/apps/baremetal/matmul_f32/main.c @@ -28,12 +28,15 @@ int main() { uint32_t core_id = mempool_get_core_id(); uint32_t num_cores = mempool_get_core_count(); + uint32_t cluster_id = mempool_get_cluster_id(); mempool_barrier_init(core_id); // Initialize Matrices if (core_id == 0) { - dma_memcpy_blocking(matrix_a, A, matrix_M * matrix_N * sizeof(int32_t)); - dma_memcpy_blocking(matrix_b, B, matrix_N * matrix_P * sizeof(int32_t)); + dma_memcpy_blocking(cluster_id, matrix_a, A, + matrix_M * matrix_N * sizeof(int32_t)); + dma_memcpy_blocking(cluster_id, matrix_b, B, + matrix_N * matrix_P * sizeof(int32_t)); } mempool_barrier(num_cores); diff --git a/software/runtime/arch.ld.c b/software/runtime/arch.ld.c index 1d8de5e57..5d214ccca 100644 --- a/software/runtime/arch.ld.c +++ b/software/runtime/arch.ld.c @@ -3,6 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 /* This file will get processed by the precompiler to expand all macros. */ +#include "addrmap.h" MEMORY { l1 (R) : ORIGIN = 0x00000000, LENGTH = (NUM_CORES * BANKING_FACTOR * L1_BANK_SIZE) @@ -31,5 +32,7 @@ SECTIONS { __heap_start = __l1_start; __heap_end = __l1_end; + // Hardware register location + eoc_reg = CONTROL_REGISTER_OFFSET + CONTROL_REGISTERS_EOC_REG_OFFSET; fake_uart = 0xC0000000; } diff --git a/software/runtime/dma.h b/software/runtime/dma.h index 4aa7f6cec..a012c077a 100644 --- a/software/runtime/dma.h +++ b/software/runtime/dma.h @@ -15,11 +15,13 @@ #include "mempool_dma_frontend.h" #include "runtime.h" -#define DMA_BASE (0x40010000) +#define DMA_BASE(id) (0x40010000 + (id * 0x10000)) -static inline void dma_config(bool decouple, bool deburst, bool serialize) { +static inline void dma_config(uint32_t cluster_id, bool decouple, bool deburst, + bool serialize) { volatile uint32_t *_dma_conf_reg = - (volatile uint32_t *)(DMA_BASE + MEMPOOL_DMA_FRONTEND_CONF_REG_OFFSET); + (volatile uint32_t *)(DMA_BASE(cluster_id) + + MEMPOOL_DMA_FRONTEND_CONF_REG_OFFSET); // Configure the DMA uint32_t config = 0; config |= (uint32_t)decouple << MEMPOOL_DMA_FRONTEND_CONF_DECOUPLE_BIT; @@ -28,35 +30,39 @@ static inline void dma_config(bool decouple, bool deburst, bool serialize) { *_dma_conf_reg = config; } -static inline uint32_t dma_idle() { +static inline uint32_t dma_idle(uint32_t cluster_id) { volatile uint32_t *_dma_status_reg = - (volatile uint32_t *)(DMA_BASE + MEMPOOL_DMA_FRONTEND_STATUS_REG_OFFSET); + (volatile uint32_t *)(DMA_BASE(cluster_id) + + MEMPOOL_DMA_FRONTEND_STATUS_REG_OFFSET); return (*_dma_status_reg) & (0x1 << MEMPOOL_DMA_FRONTEND_STATUS_BUSY_BIT); } -static inline uint32_t dma_done() { +static inline uint32_t dma_done(uint32_t cluster_id) { volatile uint32_t *_dma_done_reg = - (volatile uint32_t *)(DMA_BASE + MEMPOOL_DMA_FRONTEND_DONE_REG_OFFSET); + (volatile uint32_t *)(DMA_BASE(cluster_id) + + MEMPOOL_DMA_FRONTEND_DONE_REG_OFFSET); return *_dma_done_reg; } -static inline void dma_wait() { - while (!dma_done()) +static inline void dma_wait(uint32_t cluster_id) { + while (!dma_done(cluster_id)) ; } -void dma_memcpy_nonblocking(void *dest, const void *src, size_t len) { +void dma_memcpy_nonblocking(uint32_t cluster_id, void *dest, const void *src, + size_t len) { volatile uint32_t *_dma_src_reg = - (volatile uint32_t *)(DMA_BASE + + (volatile uint32_t *)(DMA_BASE(cluster_id) + MEMPOOL_DMA_FRONTEND_SRC_ADDR_REG_OFFSET); volatile uint32_t *_dma_dst_reg = - (volatile uint32_t *)(DMA_BASE + + (volatile uint32_t *)(DMA_BASE(cluster_id) + MEMPOOL_DMA_FRONTEND_DST_ADDR_REG_OFFSET); volatile uint32_t *_dma_len_reg = - (volatile uint32_t *)(DMA_BASE + + (volatile uint32_t *)(DMA_BASE(cluster_id) + MEMPOOL_DMA_FRONTEND_NUM_BYTES_REG_OFFSET); volatile uint32_t *_dma_id_reg = - (volatile uint32_t *)(DMA_BASE + MEMPOOL_DMA_FRONTEND_NEXT_ID_REG_OFFSET); + (volatile uint32_t *)(DMA_BASE(cluster_id) + + MEMPOOL_DMA_FRONTEND_NEXT_ID_REG_OFFSET); // Configure the DMA *_dma_src_reg = (uint32_t)src; *_dma_dst_reg = (uint32_t)dest; @@ -69,8 +75,9 @@ void dma_memcpy_nonblocking(void *dest, const void *src, size_t len) { __sync_synchronize(); } -void dma_memcpy_blocking(void *dest, const void *src, size_t len) { - dma_memcpy_nonblocking(dest, src, len); - dma_wait(); +void dma_memcpy_blocking(uint32_t cluster_id, void *dest, const void *src, + size_t len) { + dma_memcpy_nonblocking(cluster_id, dest, src, len); + dma_wait(cluster_id); } #endif // _DMA_H_ diff --git a/software/runtime/runtime.h b/software/runtime/runtime.h index 958d6775d..697215e9d 100644 --- a/software/runtime/runtime.h +++ b/software/runtime/runtime.h @@ -12,7 +12,28 @@ #include #include -#define NUM_BANKS_PER_TILE NUM_CORES_PER_TILE *BANKING_FACTOR +// Useful defines for common parameters +// The config will define: +// NUM_CORES +// NUM_CORES_PER_TILE +// NUM_GROUPS +// NUM_CLUSTERS +// BANKING_FACTOR +// L1_BANK_SIZE +// NUM_CORES_PER_GROUP +// NUM_CORES_PER_CLUSTER +// NUM_TILES_PER_GROUP +// NUM_TILES_PER_CLUSTER +#define NUM_TILES (NUM_CORES / NUM_CORES_PER_TILE) +#define NUM_GROUPS_PER_CLUSTER (NUM_GROUPS / NUM_CLUSTERS) +#define NUM_BANKS (NUM_CORES * BANKING_FACTOR) +#define NUM_BANKS_PER_TILE (NUM_BANKS / NUM_TILES) +#define NUM_BANKS_PER_GROUP (NUM_BANKS / NUM_GROUPS) +#define NUM_BANKS_PER_CLUSTER (NUM_BANKS / NUM_CLUSTERS) +#define L1_SIZE (NUM_BANKS * L1_BANK_SIZE) +#define L1_SIZE_PER_TILE (L1_SIZE / NUM_TILES) +#define L1_SIZE_PER_GROUP (L1_SIZE / NUM_GROUPS) +#define L1_SIZE_PER_CLUSTER (L1_SIZE / NUM_CLUSTERS) extern char l1_alloc_base; static uint32_t volatile *wake_up_reg = @@ -21,6 +42,9 @@ static uint32_t volatile *wake_up_reg = static uint32_t volatile *wake_up_group_reg = (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + CONTROL_REGISTERS_WAKE_UP_GROUP_REG_OFFSET); +static uint32_t volatile *wake_up_cluster_reg = + (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + + CONTROL_REGISTERS_WAKE_UP_CLUSTER_REG_OFFSET); static uint32_t volatile *wake_up_tile_g0_reg = (uint32_t volatile *)(CONTROL_REGISTER_OFFSET + @@ -78,6 +102,14 @@ static inline uint32_t mempool_get_group_id() { return mempool_get_core_id() / (NUM_CORES / NUM_GROUPS); } +/// Obtain the number of clusters in the current cluster. +static inline uint32_t mempool_get_cluster_count() { return NUM_CLUSTERS; } + +/// Obtain the ID of the cluster the current core is in. +static inline uint32_t mempool_get_cluster_id() { + return mempool_get_core_id() / (NUM_CORES_PER_CLUSTER); +} + /// Obtain the number of cores per tile in the current cluster static inline uint32_t mempool_get_core_count_per_tile() { return NUM_CORES_PER_TILE; @@ -152,6 +184,12 @@ static inline void wake_up_all() { wake_up((uint32_t)-1); } static inline void wake_up_group(uint32_t group_mask) { *wake_up_group_reg = group_mask; } +static inline void wake_up_cluster_mask(uint32_t cluster_mask) { + *wake_up_cluster_reg = cluster_mask; +} +static inline void wake_up_cluster(uint32_t cluster) { + wake_up_cluster_mask((uint32_t)1 << cluster); +} static inline void wake_up_all_group() { wake_up_group((uint32_t)-1); } static inline void wake_up_tile(uint32_t group_id, uint32_t tile_mask) { diff --git a/software/tests/baremetal/fence/main.c b/software/tests/baremetal/fence/main.c index 82f493c12..8aa61ed17 100644 --- a/software/tests/baremetal/fence/main.c +++ b/software/tests/baremetal/fence/main.c @@ -58,6 +58,7 @@ dump(fence, 11); int main() { // uint32_t num_cores_per_group = NUM_CORES / NUM_GROUPS; uint32_t core_id = mempool_get_core_id(); + uint32_t cluster_id = mempool_get_cluster_id(); // Initialize barrier and synchronize mempool_barrier_init(core_id); @@ -76,7 +77,8 @@ int main() { // Program DMA to create pressure on the read channel of the L2 and wait a // few cycles if (core_id == 0) { - dma_memcpy_nonblocking(l1_data, l2_data, SIZE * sizeof(uint32_t)); + dma_memcpy_nonblocking(cluster_id, l1_data, l2_data, + SIZE * sizeof(uint32_t)); wake_up_tile(0, 1); } // Trigger an inconsistency by trying to have a write overtake a read @@ -98,12 +100,13 @@ int main() { // Run the check __atomic_fetch_and(&error_no_fence, read_no_fence != golden, __ATOMIC_RELAXED); - dma_wait(); + dma_wait(cluster_id); // Again but with a fence // Program DMA to create pressure on the read channel of the L2 if (core_id == 0) { - dma_memcpy_nonblocking(l1_data, l2_data, SIZE * sizeof(uint32_t)); + dma_memcpy_nonblocking(cluster_id, l1_data, l2_data, + SIZE * sizeof(uint32_t)); wake_up_tile(0, 1); } // Trigger an inconsistency by trying to have a write overtake a read @@ -124,7 +127,7 @@ int main() { dump_fence(read_fence); // Check and wait __atomic_fetch_and(&error_fence, read_fence != golden, __ATOMIC_RELAXED); - dma_wait(); + dma_wait(cluster_id); // Barrier between core 0 and 1 if (core_id == 0) { diff --git a/software/tests/baremetal/memcpy/main.c b/software/tests/baremetal/memcpy/main.c index 4e07a9a30..8760a9a85 100644 --- a/software/tests/baremetal/memcpy/main.c +++ b/software/tests/baremetal/memcpy/main.c @@ -69,6 +69,7 @@ void verify_dma_parallel(int32_t *addr, uint32_t num_words, uint32_t id, int main() { uint32_t core_id = mempool_get_core_id(); uint32_t num_cores = mempool_get_core_count(); + uint32_t cluster_id = mempool_get_cluster_id(); int32_t error = 0; // Initialize barrier and synchronize @@ -82,7 +83,7 @@ int main() { // Copy in uint32_t time = mempool_get_timer(); - dma_memcpy_blocking(l1_data, l2_data, SIZE * sizeof(int32_t)); + dma_memcpy_blocking(cluster_id, l1_data, l2_data, SIZE * sizeof(int32_t)); time = mempool_get_timer() - time; dump_end(time); } @@ -92,7 +93,8 @@ int main() { if (core_id == 0) { // Copy out uint32_t time = mempool_get_timer(); - dma_memcpy_blocking(l2_data_move_out, l1_data, SIZE * sizeof(int32_t)); + dma_memcpy_blocking(cluster_id, l2_data_move_out, l1_data, + SIZE * sizeof(int32_t)); time = mempool_get_timer() - time; dump_end(time); }