From f89b812026a3feee5b025277185e5537c882ad1d Mon Sep 17 00:00:00 2001 From: Yinrong Li Date: Thu, 24 Oct 2024 20:37:18 +0200 Subject: [PATCH 1/2] [RTL] Fix address mapping issue in processing remote floo request. --- hardware/src/mempool_group_floonoc_wrapper.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/src/mempool_group_floonoc_wrapper.sv b/hardware/src/mempool_group_floonoc_wrapper.sv index 204d43fd8..af3882570 100644 --- a/hardware/src/mempool_group_floonoc_wrapper.sv +++ b/hardware/src/mempool_group_floonoc_wrapper.sv @@ -222,7 +222,7 @@ for (genvar i = 0; i < NumTilesPerGroup; i++) begin : gen_router_req_to_slave_re wen : floo_req_from_router_after_xbar[i][j].payload.wen, be : floo_req_from_router_after_xbar[i][j].payload.be, // row | bank <= row | bank | tile - tgt_addr: floo_req_from_router_after_xbar[i][j].hdr.tgt_addr[(NumTilesPerGroupWidth == 1 ? 0 : NumTilesPerGroupWidth) +: (idx_width(NumBanksPerTile) + TCDMAddrMemWidth)], // For TCDM Bank, remove tile offset, it is selected by "req_tile_sel" + tgt_addr: floo_req_from_router_after_xbar[i][j].hdr.tgt_addr[(NumTilesPerGroup == 1 ? 0 : NumTilesPerGroupWidth) +: (idx_width(NumBanksPerTile) + TCDMAddrMemWidth)], // For TCDM Bank, remove tile offset, it is selected by "req_tile_sel" ini_addr: floo_req_from_router_after_xbar[i][j].hdr.src_tile_id, // For Crossbar when response back src_group_id: group_id_t'(floo_req_from_router_after_xbar[i][j].hdr.src_id) // For NoC Router when response back }; From b43eaf39d5a4c5a3801f8bfcc2d54159463efa32 Mon Sep 17 00:00:00 2001 From: Yinrong Li Date: Thu, 24 Oct 2024 20:38:25 +0200 Subject: [PATCH 2/2] [RTL] Fix ICache set configuration for 2-core mempool tile. --- hardware/src/mempool_pkg.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardware/src/mempool_pkg.sv b/hardware/src/mempool_pkg.sv index 5096c5cbe..4f6c43e31 100644 --- a/hardware/src/mempool_pkg.sv +++ b/hardware/src/mempool_pkg.sv @@ -161,7 +161,7 @@ package mempool_pkg; ***********************/ localparam int unsigned ICacheSizeByte = 512 * NumCoresPerCache; // Total Size of instruction cache in bytes - localparam int unsigned ICacheSets = NumCoresPerCache / 2; // Number of sets + localparam int unsigned ICacheSets = (NumCoresPerCache == 2) ? 2 : NumCoresPerCache / 2; // Number of sets localparam int unsigned ICacheLineWidth = 32 * 2 * NumCoresPerCache; // Size of each cache line in bits /*********************