DMA module with cache coherence

[SMLEric]

Hi, I am working on a project to add a DMA engine right now. I currently have a DMA block module which have been tested to be working on the original cva6. I want to integrate the DMA module and connect it to the CCU module to achieve cache coherent. What are some best ways to do this? How should I change the AXI protocol bus to adapt the ACE protocol and the SNOOP BUS?