From d5c58e1ec311e6105487602801a1dae1423bead2 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Wed, 3 Jul 2024 18:36:36 +0200 Subject: [PATCH 1/3] bender: bump Ara and CVA6 --- Bender.lock | 8 ++++---- Bender.yml | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Bender.lock b/Bender.lock index 065676b9c..de05c4b65 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,10 +15,10 @@ packages: - apb - register_interface ara: - revision: 09142d01d3fd5dedc3f962fe67ac63be999e6ad2 + revision: 1908d334841b70507d1a42e10c281a08f1777419 version: null source: - Git: https://github.com/mp-17/ara.git + Git: https://github.com/pulp-platform/ara.git dependencies: - apb - axi @@ -103,10 +103,10 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: - revision: 2240a61da2cdccf38e2aa932a19180d6faa7a31d + revision: 5614fc9ceeae6db3851e8c721de868355db9476b version: null source: - Git: https://github.com/mp-17/cva6.git + Git: https://github.com/pulp-platform/cva6.git dependencies: - axi - common_cells diff --git a/Bender.yml b/Bender.yml index c8f9a2ed1..906abcb16 100644 --- a/Bender.yml +++ b/Bender.yml @@ -22,8 +22,8 @@ dependencies: clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } - cva6: { git: "https://github.com/mp-17/cva6.git", rev: mp/pulp-v1 } - ara: { git: "https://github.com/mp-17/ara.git", rev: mp/cva6-pulpv1/rebase } + cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: mp/pulp-v1-araOS } + ara: { git: "https://github.com/pulp-platform/ara.git", rev: mp/pulp-v1-os-fpga } iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } From 08310a1c045668f63aba408277ea52efaa878ce1 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Thu, 4 Jul 2024 14:43:23 +0200 Subject: [PATCH 2/3] hw: add MMU interface between Ara and CVA6 --- hw/cheshire_soc.sv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 3d2fa2ef5..2404ef934 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -548,8 +548,8 @@ module cheshire_soc import cheshire_pkg::*; #( // TODO: Implement X interface support // Accelerator ports - acc_pkg::accelerator_req_t acc_req; - acc_pkg::accelerator_resp_t acc_resp; + acc_pkg::cva6_to_acc_t acc_req; + acc_pkg::acc_to_cva6_t acc_resp; // CVA6-Ara memory consistency logic acc_cons_en; @@ -558,13 +558,13 @@ module cheshire_soc import cheshire_pkg::*; #( logic inval_ready; // Pack invalidation interface into acc interface - acc_pkg::accelerator_resp_t acc_resp_pack; + acc_pkg::acc_to_cva6_t acc_resp_pack; always_comb begin : pack_inval - acc_resp_pack = acc_resp; - acc_resp_pack.inval_valid = inval_valid; - acc_resp_pack.inval_addr = inval_addr; - inval_ready = acc_req.inval_ready; - acc_cons_en = acc_req.acc_cons_en; + acc_resp_pack = acc_resp; + acc_resp_pack.acc_resp.inval_valid = inval_valid; + acc_resp_pack.acc_resp.inval_addr = inval_addr; + inval_ready = acc_req.acc_req.inval_ready; + acc_cons_en = acc_req.acc_req.acc_cons_en; end `CHESHIRE_TYPEDEF_AXI_CT(axi_cva6, addr_t, cva6_id_t, axi_data_t, axi_strb_t, axi_user_t) @@ -617,8 +617,8 @@ module cheshire_soc import cheshire_pkg::*; #( .axi_w_chan_t ( axi_cva6_w_chan_t ), .b_chan_t ( axi_cva6_b_chan_t ), .r_chan_t ( axi_cva6_r_chan_t ), - .cvxif_req_t ( acc_pkg::accelerator_req_t ), - .cvxif_resp_t ( acc_pkg::accelerator_resp_t ), + .cvxif_req_t ( acc_pkg::cva6_to_acc_t ), + .cvxif_resp_t ( acc_pkg::acc_to_cva6_t ), .noc_req_t ( axi_cva6_req_t ), .noc_resp_t ( axi_cva6_rsp_t ) ) i_core_cva6 ( From af89948c77e0adb8034168891ea6b1fc4b938ed8 Mon Sep 17 00:00:00 2001 From: mojtaba Date: Fri, 4 Oct 2024 11:18:57 +0200 Subject: [PATCH 3/3] Add VCU118 support to ara-pulpv1-os --- Bender.lock | 2 +- sw/boot/cheshire.dtsi | 2 +- sw/boot/cheshire.vcu118.dts | 20 +++ target/xilinx/constraints/vcu118.xdc | 199 +++++++++++++++++++++++ target/xilinx/scripts/common.tcl | 5 + target/xilinx/scripts/impl_ip.tcl | 75 +++++++++ target/xilinx/src/cheshire_top_xilinx.sv | 4 + target/xilinx/src/dram_wrapper_xilinx.sv | 76 +++++++++ target/xilinx/src/phy_definitions.svh | 29 ++++ target/xilinx/xilinx.mk | 9 +- 10 files changed, 415 insertions(+), 6 deletions(-) create mode 100644 sw/boot/cheshire.vcu118.dts create mode 100644 target/xilinx/constraints/vcu118.xdc diff --git a/Bender.lock b/Bender.lock index de05c4b65..217299b3b 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,7 +15,7 @@ packages: - apb - register_interface ara: - revision: 1908d334841b70507d1a42e10c281a08f1777419 + revision: c3355df5ecf742c4e7a92a428cb7467045b5b163 version: null source: Git: https://github.com/pulp-platform/ara.git diff --git a/sw/boot/cheshire.dtsi b/sw/boot/cheshire.dtsi index 76decc852..5561e8749 100644 --- a/sw/boot/cheshire.dtsi +++ b/sw/boot/cheshire.dtsi @@ -30,7 +30,7 @@ status = "okay"; compatible = "eth,ariane", "riscv"; clock-frequency = <50000000>; // 50 MHz - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdcv"; mmu-type = "riscv,sv39"; tlb-split; reg = <0>; diff --git a/sw/boot/cheshire.vcu118.dts b/sw/boot/cheshire.vcu118.dts new file mode 100644 index 000000000..c9b0f1878 --- /dev/null +++ b/sw/boot/cheshire.vcu118.dts @@ -0,0 +1,20 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig +// Mojtaba Rostami + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; // CS + spi-max-frequency = <25000000>; + voltage-ranges = <3300 3300>; + clock-frequency = <1000000>; + disable-wp; + }; +}; diff --git a/target/xilinx/constraints/vcu118.xdc b/target/xilinx/constraints/vcu118.xdc new file mode 100644 index 000000000..7c398c73f --- /dev/null +++ b/target/xilinx/constraints/vcu118.xdc @@ -0,0 +1,199 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig +# Paul Scheffler + +############# +# Sys Clock # +############# + +# 125 MHz input clock +set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports sys_clk_p] +set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports sys_clk_n] +create_clock -period 8.000 -name clk_125mhz [get_ports sys_clk_p] + +# SoC clock is generated by clock wizard and its constraints +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_clkwiz/inst/clk_50] + + +####### +# MIG # +####### + +# Dram axi clock : 333 MHz (defined by MIG constraints) + +# False-path incoming reset +set_false_path -setup -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_aresetn] + +# Constrain outgoing reset +set_false_path -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +set_max_delay -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] 3.000 + +# Limit delay across DRAM CDC (hold already false-pathed) +# tclint-disable line-length +set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] 3.000 +set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] 3.000 +# tclint-enable line-length + +############### +# Assign Pins # +############### + +# tclint-disable line-length, spacing + +set_property PACKAGE_PIN AW25 [get_ports uart_rx_i] +set_property IOSTANDARD LVCMOS18 [get_ports uart_rx_i] +set_property PACKAGE_PIN BB21 [get_ports uart_tx_o] +set_property IOSTANDARD LVCMOS18 [get_ports uart_tx_o] + + +# Active high reset (GPIO_SW_N) +set_property PACKAGE_PIN BB24 [get_ports sys_reset] +set_property IOSTANDARD LVCMOS18 [get_ports sys_reset] + +# tclint-enable line-length, spacing + +# SD Card +set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS12} [get_ports sd_cd_i] +set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS12} [get_ports sd_cmd_o] +set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[0]}] +set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[1]}] +set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[2]}] +set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[3]}] +set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS12} [get_ports sd_sclk_o] + + +## DDR4 + +set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n] +set_property PACKAGE_PIN E12 [get_ports c0_sys_clk_p] +set_property PACKAGE_PIN D12 [get_ports c0_sys_clk_n] +set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p] + +set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n] +set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}] +set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}] +set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}] +set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}] +set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}] +set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}] +set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}] +set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}] +set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}] +set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}] +set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}] +set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}] +set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}] +set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}] +set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}] +set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}] +set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}] +set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}] +set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}] +set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}] +set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}] +set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}] +set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}] +set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}] +set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}] +set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}] +set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}] +set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}] +set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}] +set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}] +set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}] +set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}] + +set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}] +set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}] +set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}] +set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}] +set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}] +set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}] +set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}] +set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}] +set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}] +set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}] +set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}] +set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}] +set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}] +set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}] +set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}] +set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}] +set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}] +set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}] +set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}] +set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}] +set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}] +set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}] +set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}] +set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}] +set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}] +set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}] +set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}] +set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}] +set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}] +set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}] +set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}] +set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}] +set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}] +set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}] +set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}] +set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}] +set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}] +set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}] +set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}] +set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}] +set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}] +set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}] +set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}] +set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}] +set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}] +set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}] +set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}] +set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}] +set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}] +set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}] +set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}] +set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}] +set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}] +set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}] +set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}] +set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}] +set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}] +set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}] +set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}] +set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}] + +set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}] +set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}] +set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}] +set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}] + +set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}] +set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}] +set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}] +set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}] +set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}] +set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}] +set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}] +set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}] +set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}] +set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}] +set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}] +set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}] +set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}] +set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}] +set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}] +set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}] + +set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}] +set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n] + +########## + + diff --git a/target/xilinx/scripts/common.tcl b/target/xilinx/scripts/common.tcl index 32066b8a1..801fe1112 100644 --- a/target/xilinx/scripts/common.tcl +++ b/target/xilinx/scripts/common.tcl @@ -15,6 +15,11 @@ set fpart(vcu128) "xcvu37p-fsvh2892-2L-e" set hwdev(vcu128) "xcvu37p_0" set cfgmp(vcu128) "mt25qu02g-spi-x1_x2_x4" +# vcu118 board params +set bpart(vcu118) "xilinx.com:vcu118:part0:2.4" +set fpart(vcu118) "xcvu9p-flga2104-2L-e" +set hwdev(vcu118) "xcvu9p_0" + # Initialize an implementation project proc init_impl {xilinx_root argc argv} { diff --git a/target/xilinx/scripts/impl_ip.tcl b/target/xilinx/scripts/impl_ip.tcl index 474787fe7..7ca6090c7 100644 --- a/target/xilinx/scripts/impl_ip.tcl +++ b/target/xilinx/scripts/impl_ip.tcl @@ -77,6 +77,43 @@ switch $proj { CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ ] [get_ips $proj] } + vcu118 { + set_property -dict [list \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_RESET {true} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {125.000} \ + CONFIG.CLKOUT1_USED {true} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100.000} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {48.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {8.000} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {12.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {120} \ + CONFIG.MMCM_CLKOUT4_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {177.983} \ + CONFIG.CLKOUT1_PHASE_ERROR {222.305} \ + CONFIG.CLKOUT2_JITTER {196.543} \ + CONFIG.CLKOUT2_PHASE_ERROR {222.305} \ + CONFIG.CLKOUT3_JITTER {227.146} \ + CONFIG.CLKOUT3_PHASE_ERROR {222.305} \ + CONFIG.CLKOUT4_JITTER {261.444} \ + CONFIG.CLKOUT4_PHASE_ERROR {222.305} \ + ] [get_ips $proj] + } default {nocfgexit $proj $board} } } @@ -106,6 +143,17 @@ switch $proj { CONFIG.C_NUM_PROBE_IN {0} \ ] [get_ips $proj] } + vcu118 { + set_property -dict [list \ + CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $proj] + } default {nocfgexit $proj $board} } } @@ -152,6 +200,33 @@ switch $proj { CONFIG.C0.DDR4_AxiSelection {true} \ ] [get_ips $proj] } + vcu118 { + set_property -dict [list \ + CONFIG.C0.DDR4_Clamshell {false} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \ + CONFIG.System_Clock {Differential} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.DDR4_InputClockPeriod {4000} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \ + CONFIG.C0.DDR4_Ecc {false} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiAddressWidth {31} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.CS_WIDTH {1} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_CasWriteLatency {9} \ + CONFIG.C0.DDR4_TimePeriod {1250} \ + CONFIG.C0.DDR4_Specify_MandD {true} \ + CONFIG.C0.DDR4_CLKFBOUT_MULT {8} \ + CONFIG.C0.DDR4_DIVCLK_DIVIDE {2} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + ] [get_ips $proj] + } default {nocfgexit $proj $board} } } diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index eb2b5b0c8..55196f412 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -52,7 +52,9 @@ module cheshire_top_xilinx ( input logic sd_cd_i, output logic sd_cmd_o, inout wire [3:0] sd_d_io, +`ifndef TARGET_VCU118 output logic sd_reset_o, +`endif output logic sd_sclk_o, `endif @@ -257,8 +259,10 @@ module cheshire_top_xilinx ( logic [3:0] spi_sd_en; `ifdef USE_SD +`ifndef TARGET_VCU118 // Assert reset low => Apply power to the SD Card assign sd_reset_o = 1'b0; +`endif // SCK - SD CLK signal assign sd_sclk_o = spi_sck_en ? spi_sck_soc : 1'b1; // CS - SD DAT3 signal diff --git a/target/xilinx/src/dram_wrapper_xilinx.sv b/target/xilinx/src/dram_wrapper_xilinx.sv index 2a4719a03..0b179744a 100644 --- a/target/xilinx/src/dram_wrapper_xilinx.sv +++ b/target/xilinx/src/dram_wrapper_xilinx.sv @@ -53,6 +53,20 @@ module dram_wrapper_xilinx #( integer MaxTxns; } dram_cfg_t; + +`ifdef TARGET_VCU118 + localparam dram_cfg_t cfg = '{ + EnCdc : 1, // 333 MHz AXI (cf. CdcLogDepth) + CdcLogDepth : 5, + IdWidth : 8, + AddrWidth : 32, + DataWidth : 512, + StrobeWidth : 64, + MaxUniqIds : 8, // TODO: suboptimal, but limited by CVA6/LLC + MaxTxns : 24 // TODO: suboptimal, but limited by CVA6/LLC + }; +`endif + `ifdef TARGET_VCU128 localparam dram_cfg_t cfg = '{ EnCdc : 1, // 333 MHz AXI (cf. CdcLogDepth) @@ -223,6 +237,7 @@ module dram_wrapper_xilinx #( ///////////////////////// `ifdef USE_DDR4 +`ifdef TARGET_VCU128 ddr4 i_dram ( // Reset .sys_rst ( sys_rst_i ), // Active high @@ -296,6 +311,67 @@ module dram_wrapper_xilinx #( // PHY .* ); + +`endif +`ifdef TARGET_VCU118 + ddr4 i_dram ( + // Reset + .sys_rst ( sys_rst_i ), // Active high + .c0_ddr4_aresetn ( soc_resetn_i ), + // Clock and reset out + .c0_sys_clk_p ( c0_sys_clk_p ), + .c0_sys_clk_n ( c0_sys_clk_n ), + + .c0_ddr4_ui_clk ( dram_axi_clk ), + .c0_ddr4_ui_clk_sync_rst ( dram_rst_o ), + // AXI + .c0_ddr4_s_axi_awid ( cdc_dram_req.aw.id ), + .c0_ddr4_s_axi_awaddr ( cdc_dram_req_aw_addr ), + .c0_ddr4_s_axi_awlen ( cdc_dram_req.aw.len ), + .c0_ddr4_s_axi_awsize ( cdc_dram_req.aw.size ), + .c0_ddr4_s_axi_awburst ( cdc_dram_req.aw.burst ), + .c0_ddr4_s_axi_awlock ( cdc_dram_req.aw.lock ), + .c0_ddr4_s_axi_awcache ( cdc_dram_req.aw.cache ), + .c0_ddr4_s_axi_awprot ( cdc_dram_req.aw.prot ), + .c0_ddr4_s_axi_awqos ( cdc_dram_req.aw.qos ), + .c0_ddr4_s_axi_awvalid ( cdc_dram_req.aw_valid ), + .c0_ddr4_s_axi_awready ( cdc_dram_rsp.aw_ready ), + .c0_ddr4_s_axi_wdata ( cdc_dram_req.w.data ), + .c0_ddr4_s_axi_wstrb ( cdc_dram_req.w.strb ), + .c0_ddr4_s_axi_wlast ( cdc_dram_req.w.last ), + .c0_ddr4_s_axi_wvalid ( cdc_dram_req.w_valid ), + .c0_ddr4_s_axi_wready ( cdc_dram_rsp.w_ready ), + .c0_ddr4_s_axi_bready ( cdc_dram_req.b_ready ), + .c0_ddr4_s_axi_bid ( cdc_dram_rsp.b.id ), + .c0_ddr4_s_axi_bresp ( cdc_dram_rsp.b.resp ), + .c0_ddr4_s_axi_bvalid ( cdc_dram_rsp.b_valid ), + .c0_ddr4_s_axi_arid ( cdc_dram_req.ar.id ), + .c0_ddr4_s_axi_araddr ( cdc_dram_req_ar_addr ), + .c0_ddr4_s_axi_arlen ( cdc_dram_req.ar.len ), + .c0_ddr4_s_axi_arsize ( cdc_dram_req.ar.size ), + .c0_ddr4_s_axi_arburst ( cdc_dram_req.ar.burst ), + .c0_ddr4_s_axi_arlock ( cdc_dram_req.ar.lock ), + .c0_ddr4_s_axi_arcache ( cdc_dram_req.ar.cache ), + .c0_ddr4_s_axi_arprot ( cdc_dram_req.ar.prot ), + .c0_ddr4_s_axi_arqos ( cdc_dram_req.ar.qos ), + .c0_ddr4_s_axi_arvalid ( cdc_dram_req.ar_valid ), + .c0_ddr4_s_axi_arready ( cdc_dram_rsp.ar_ready ), + .c0_ddr4_s_axi_rready ( cdc_dram_req.r_ready ), + .c0_ddr4_s_axi_rid ( cdc_dram_rsp.r.id ), + .c0_ddr4_s_axi_rdata ( cdc_dram_rsp.r.data ), + .c0_ddr4_s_axi_rresp ( cdc_dram_rsp.r.resp ), + .c0_ddr4_s_axi_rlast ( cdc_dram_rsp.r.last ), + .c0_ddr4_s_axi_rvalid ( cdc_dram_rsp.r_valid ), + // Others + .c0_init_calib_complete ( ), + .addn_ui_clkout1 ( dram_clk_o ), + .dbg_clk ( ), + .dbg_bus ( ), + // PHY + .* + ); + +`endif `endif ///////////////////////// diff --git a/target/xilinx/src/phy_definitions.svh b/target/xilinx/src/phy_definitions.svh index a4d7798da..0bd792e1e 100644 --- a/target/xilinx/src/phy_definitions.svh +++ b/target/xilinx/src/phy_definitions.svh @@ -4,6 +4,13 @@ // // Cyril Koenig +`ifdef TARGET_VCU118 + `define USE_RESET + `define USE_SD + `define USE_DDR4 + `define USE_VIO +`endif + `ifdef TARGET_VCU128 `define USE_RESET `define USE_JTAG @@ -45,6 +52,27 @@ `define USE_DDR `endif +`ifdef TARGET_VCU118 +`define DDR4_INTF \ + input c0_sys_clk_p, \ + input c0_sys_clk_n, \ + output c0_ddr4_reset_n, \ + output [0:0] c0_ddr4_ck_t, \ + output [0:0] c0_ddr4_ck_c, \ + output c0_ddr4_act_n, \ + output [16:0] c0_ddr4_adr, \ + output [1:0] c0_ddr4_ba, \ + output [0:0] c0_ddr4_bg, \ + output [0:0] c0_ddr4_cke, \ + output [0:0] c0_ddr4_odt, \ + output [0:0] c0_ddr4_cs_n, \ + inout [7:0] c0_ddr4_dm_dbi_n, \ + inout [63:0] c0_ddr4_dq, \ + inout [7:0] c0_ddr4_dqs_c, \ + inout [7:0] c0_ddr4_dqs_t, +`endif + +`ifdef TARGET_VCU128 `define DDR4_INTF \ output c0_ddr4_reset_n, \ output [0:0] c0_ddr4_ck_t, \ @@ -60,6 +88,7 @@ inout [71:0] c0_ddr4_dq, \ inout [8:0] c0_ddr4_dqs_c, \ inout [8:0] c0_ddr4_dqs_t, +`endif `define DDR3_INTF \ output ddr3_ck_p, \ diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index be35b5a9c..6b088246e 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -29,16 +29,17 @@ $(CHS_XILINX_DIR)/build/%/out.xci: \ $$(wildcard $(CHS_XILINX_DIR)/src/ips/$$*.prj) \ | $(CHS_XILINX_DIR)/build/%/ @rm -f $(CHS_XILINX_DIR)/build/$(*)*.log $(CHS_XILINX_DIR)/build/$(*)*.jou - cd $| && $(VIVADO) -mode batch -log ../$*.log -jou ../$*.jou -source $< -tclargs "$(subst ., ,$*)" + cd $| && $(VIVADO) -mode batch -log ../$*.log -jou ../$*.jou -source $< -tclargs $(subst ., ,$*) ############## # Bitstreams # ############## -CHS_XILINX_BOARDS := genesys2 vcu128 +CHS_XILINX_BOARDS := genesys2 vcu128 vcu118 CHS_XILINX_IPS_genesys2 := clkwiz vio mig7s CHS_XILINX_IPS_vcu128 := clkwiz vio ddr4 +CHS_XILINX_IPS_vcu118 := clkwiz vio ddr4 $(CHS_XILINX_DIR)/scripts/add_sources.%.tcl: $(CHS_ROOT)/Bender.yml $(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 -t $* > $@ @@ -52,7 +53,7 @@ $$(CHS_XILINX_DIR)/out/%.$(1).bit: \ | $$(CHS_XILINX_DIR)/build/$(1).%/ @rm -f $$(CHS_XILINX_DIR)/build/$$*.$(1)*.log $$(CHS_XILINX_DIR)/build/$$*.$(1)*.jou cd $$| && $$(VIVADO) -mode batch -log ../$$*.$(1).log -jou ../$$*.$(1).jou -source $$< \ - -tclargs "$(1) $$* $$(CHS_XILINX_IPS_$(1):%=$$(CHS_XILINX_DIR)/build/$(1).%/out.xci)" + -tclargs $(1) $$* $$(CHS_XILINX_IPS_$(1):%=$$(CHS_XILINX_DIR)/build/$(1).%/out.xci) .PHONY: chs-xilinx-$(1) chs-xilinx-$(1): $$(CHS_XILINX_DIR)/out/cheshire.$(1).bit @@ -77,7 +78,7 @@ chs-xilinx-$(1)-%: $$(CHS_XILINX_DIR)/scripts/util/$(1).tcl | $$(CHS_XILINX_DIR) [ -e $(subst %,$$*,$(2)) ] || $$(MAKE) $(subst %,$$*,$(2)) @rm -f $$(CHS_XILINX_DIR)/build/$$(*)*.$(1).log $$(CHS_XILINX_DIR)/build/$$(*)*.$(1).jou cd $$| && $$(VIVADO) -mode batch -log ../$$(*).$(1).log -jou ../$$(*).$(1).jou -source $$< \ - -tclargs "$$(CHS_XILINX_HWS_URL) $$(or $$(CHS_XILINX_HWS_PATH_$$*),*) $$* $(subst %,$$*,$(2)) 0" + -tclargs $$(CHS_XILINX_HWS_URL) $$(or $$(CHS_XILINX_HWS_PATH_$$*),*) $$* $(subst %,$$*,$(2)) 0 endef # Program bitstream onto board