diff --git a/Bender.lock b/Bender.lock
index 1b8a19a1b..a994bbcef 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -14,6 +14,17 @@ packages:
dependencies:
- apb
- register_interface
+ ara:
+ revision: 3dad93de70c6bb20c4c0b20780d96d4243f94136
+ version: null
+ source:
+ Git: https://github.com/pulp-platform/ara.git
+ dependencies:
+ - apb
+ - axi
+ - common_cells
+ - cva6
+ - tech_cells_generic
axi:
revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
version: 0.39.2
@@ -92,7 +103,7 @@ packages:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
cva6:
- revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5
+ revision: 99ae53bde1a94b90c1d9bbbe7fe272a9336200a6
version: null
source:
Git: https://github.com/pulp-platform/cva6.git
diff --git a/Bender.yml b/Bender.yml
index a4ed787b6..d922154b2 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -22,7 +22,8 @@ dependencies:
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
- cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 }
+ cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1 }
+ ara: { git: "https://github.com/pulp-platform/ara.git", rev: mp/cva6-pulpv1/rebase }
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 }
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 }
diff --git a/cheshire.mk b/cheshire.mk
index 033df4532..fc6728906 100644
--- a/cheshire.mk
+++ b/cheshire.mk
@@ -58,7 +58,7 @@ chs-clean-deps:
######################
CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= f731b17
+CHS_NONFREE_COMMIT ?= dc0a4e4c
CHS_PHONY += chs-nonfree-init
chs-nonfree-init:
diff --git a/docs/img/arch.svg b/docs/img/arch.svg
index c3a0a4c67..d24e0b8fb 100644
--- a/docs/img/arch.svg
+++ b/docs/img/arch.svg
@@ -12,7 +12,7 @@
viewBox="0 0 108.49873 63.641592"
version="1.1"
id="svg8"
- inkscape:version="1.0.2 (e86c870879, 2021-01-15)"
+ inkscape:version="0.92.3 (2405546, 2018-03-11)"
sodipodi:docname="arch.svg">
@@ -811,6 +811,21 @@
style="fill:#910569;fill-opacity:1;fill-rule:evenodd;stroke:#910569;stroke-width:1pt;stroke-opacity:1"
transform="scale(0.2)" />
+
+
+
image/svg+xml
-
+
@@ -873,13 +888,12 @@
id="layer1"
transform="translate(5.7798302,-102.39774)">
+ width="107.01112"
+ height="53.505554"
+ x="-5.2553034"
+ y="109.22112" />
+ width="16.605181"
+ height="5.5350599"
+ x="-159.95914"
+ y="21.497478"
+ transform="rotate(-90)" />
CVA6 0
+ x="-155.07829"
+ y="24.491997"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.23599461">CVA6 0
+ width="16.605181"
+ height="5.5350604"
+ x="-159.95914"
+ y="28.877556"
+ transform="rotate(-90)" />
...
+ x="36.20525"
+ y="150.85513"
+ style="font-size:1.95264852px;stroke-width:0.24408038">...
cfg.NumCores
+ x="-150.73448"
+ y="39.459045"
+ style="font-style:italic;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.78992712px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';stroke-width:0.24408038">cfg.NumCores
+ width="7.3800774"
+ height="35.977879"
+ x="-139.66393"
+ y="19.65246"
+ transform="rotate(-90)" />
AXI4+ATOP Crossbar
+ x="41.383137"
+ y="125.85525"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.22411728">AXI4+ATOP Crossbar
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
+ width="16.605181"
+ height="5.5350595"
+ x="-159.95914"
+ y="48.465523"
+ transform="rotate(-90)" />
iDMA
+ x="-151.32834"
+ y="52.345711"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.24408038">iDMA
+ sodipodi:nodetypes="cc" />
+ width="16.605173"
+ height="5.5350595"
+ x="-128.59378"
+ y="19.65246"
+ transform="rotate(-90)" />
JTAG Debug
+ x="-138.22926"
+ y="20.187216"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.21212742">JTAG Debug
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
+ width="16.605173"
+ height="5.5350599"
+ x="-128.59378"
+ y="26.110027"
+ transform="rotate(-90)" />
Serial Link
+ x="-129.4223"
+ y="27.781496"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.22626117">Serial Link
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
+ width="16.605173"
+ height="5.5350604"
+ x="-128.59378"
+ y="32.567596"
+ transform="rotate(-90)" />
VGA
+ x="-129.34341"
+ y="33.743752"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.22626117">VGA
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="ccccc" />
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
+ width="12.915137"
+ height="3.6900384"
+ x="68.506844"
+ y="137.81888" />
Regbus Demux
+ x="-138.12448"
+ y="61.930607"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.24044476">Regbus Demux
+ style="fill:#07b5bd;fill-opacity:1;stroke:none;stroke-width:0.0242061;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:1.58739996;stroke-opacity:1" />
...
+ x="48.051422"
+ y="129.63739"
+ style="font-size:1.95264852px;stroke-width:0.24408038">...
...
+ x="51.741459"
+ y="129.63739"
+ style="font-size:1.95264852px;stroke-width:0.24408038">...
cfg.AxiExtNumMst
+ x="-130.62918"
+ y="44.928909"
+ style="font-style:italic;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.78992712px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';stroke-width:0.22480084">cfg.AxiExtNumMst
cfg.AxiExtNumSlv
+ x="-130.66872"
+ y="48.332306"
+ style="font-style:italic;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.78992712px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';stroke-width:0.22480084">cfg.AxiExtNumSlv
+ sodipodi:nodetypes="cc" />
+ width="12.915137"
+ height="3.6900384"
+ x="68.506844"
+ y="142.43144" />
+ sodipodi:nodetypes="cc" />
+ width="12.915137"
+ height="3.6900384"
+ x="68.506844"
+ y="147.04396" />
IRQ Router
+ x="89.160645"
+ y="126.32343"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.20584606">IRQ Router
CLINT
+ x="75.292648"
+ y="145.38913"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.24408038">CLINT
PLIC
+ x="75.344841"
+ y="140.7301"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.24408038">PLIC
+ sodipodi:nodetypes="cc" />
CVA6 1
+ x="-155.07828"
+ y="31.627577"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.23599461">CVA6 1
+ width="5.5350595"
+ height="2.7675271"
+ x="28.877552"
+ y="157.1916" />
CLIC
+ x="31.219824"
+ y="161.48106"
+ style="font-size:2.13901401px;fill:#ffffff;fill-opacity:1;stroke-width:0.2473968">CLIC
Device configs
+ x="75.027519"
+ y="115.00782"
+ style="font-style:italic;font-size:1.78992712px;fill:#000000;fill-opacity:1;stroke-width:0.2473968">Device configs
+ sodipodi:nodetypes="cc" />
+ width="5.535058"
+ height="23.985254"
+ x="10.427361"
+ y="123.98126" />
Last Level Cache
+ x="-145.79469"
+ y="13.330066"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.22773537">Last Level Cache
+ width="12.915134"
+ height="3.6900401"
+ x="68.516594"
+ y="133.20634" />
GPIO
+ x="75.296661"
+ y="136.11757"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.24408038">GPIO
+ sodipodi:nodetypes="cc" />
+ width="12.915134"
+ height="3.6900401"
+ x="68.516594"
+ y="128.59378" />
SPI Host
+ x="78.091408"
+ y="126.83472"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.23541249">SPI Host
+ sodipodi:nodetypes="cc" />
+ width="12.915134"
+ height="3.6900401"
+ x="68.516594"
+ y="123.98124" />
I2C
+ x="75.296661"
+ y="126.89243"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.24408038">I2C
+ sodipodi:nodetypes="cc" />
+ width="12.915134"
+ height="3.6900401"
+ x="68.516586"
+ y="119.36871" />
UART
+ x="75.296661"
+ y="122.27991"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.24408038">UART
+ sodipodi:nodetypes="cc" />
+ width="12.915138"
+ height="3.6900384"
+ x="68.516594"
+ y="151.65654" />
Boot ROM
+ x="84.214485"
+ y="137.60818"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.21729992">Boot ROM
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
gpio*
+ x="95.304329"
+ y="124.85772"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:start;text-anchor:start;stroke-width:0.22480084">gpio*
spih*
+ x="95.304329"
+ y="120.6095"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:start;text-anchor:start;stroke-width:0.22480084">spih*
i2c*
+ x="95.25605"
+ y="116.54178"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:start;text-anchor:start;stroke-width:0.22480084">i2c*
uart*
+ x="95.25605"
+ y="112.29353"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:start;text-anchor:start;stroke-width:0.22480084">uart*
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
xeip_ext*
+ x="95.319283"
+ y="129.12172"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:start;text-anchor:start;stroke-width:0.22480084">xeip_ext*
m*ip_ext*
+ x="95.360519"
+ y="133.35104"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:start;text-anchor:start;stroke-width:0.22480084">m*ip_ext*
intr_ext*
+ x="95.331551"
+ y="137.59924"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:start;text-anchor:start;stroke-width:0.22480084">intr_ext*
+ transform="matrix(0.9225097,0,0,0.9225097,10.398537,6.82251)">
+ style="fill:none;stroke:#050004;stroke-width:0.40000001;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#TriangleInS-0-8-5-2)" />
+ style="fill:none;stroke:#050004;stroke-width:0.40000001;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:0.2, 0.2;stroke-dashoffset:0;stroke-opacity:1" />
+ transform="matrix(0.9225097,0,0,0.9225097,10.398537,6.82251)">
+ style="fill:none;stroke:#910569;stroke-width:0.40000001;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#TriangleInS-0-8-5-4-4-5-6-6-6-2);marker-end:url(#TriangleOutS-3-4-9-5-9-0-1-7-0-0-0-5-6-9-4)" />
+ style="fill:none;stroke:#910569;stroke-width:0.40000001;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#TriangleInS-0-8-5-4-4-5-6-6-6-2-2);marker-end:url(#TriangleOutS-3-4-9-5-9-0-1-7-0-0-0-5-6-9-4-5)" />
+ sodipodi:nodetypes="cc" />
...
+ x="117.32484"
+ y="-66.191566"
+ style="font-size:1.95264852px;stroke-width:0.24408038">...
cfg.RegExtNumSlv
+ x="81.459312"
+ y="108.69317"
+ style="font-style:italic;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.78992712px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';stroke-width:0.22480084">cfg.RegExtNumSlv
reg_ext_slv*
+ x="95.25605"
+ y="107.19576"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:start;text-anchor:start;stroke-width:0.22480084">reg_ext_slv*
vga*
+ x="38.394199"
+ y="97.195976"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:center;text-anchor:middle;stroke-width:0.22480084">vga*
+ sodipodi:nodetypes="cc" />
slink*
+ x="31.382803"
+ y="97.183899"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:center;text-anchor:middle;stroke-width:0.22480084">slink*
+ sodipodi:nodetypes="cc" />
+ sodipodi:nodetypes="cc" />
jtag*
+ x="23.791754"
+ y="97.166656"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:center;text-anchor:middle;stroke-width:0.22480084">jtag*
axi_ext*
+ x="52.93256"
+ y="97.192886"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:center;text-anchor:middle;stroke-width:0.22480084">axi_ext*
+ sodipodi:nodetypes="ccc" />
+ style="fill:none;stroke:#050004;stroke-width:0.40000001;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#TriangleInS-0-8-5-2-2-6-9)" />
+ style="fill:none;stroke:#050004;stroke-width:0.40000001;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:0.2, 0.2;stroke-dashoffset:0;stroke-opacity:1" />
dbg*
+ x="17.322229"
+ y="97.195709"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:center;text-anchor:middle;stroke-width:0.22480084">dbg*
axi_llc*
+ x="0.31779841"
+ y="125.70911"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:center;text-anchor:middle;stroke-width:0.22480084">axi_llc*
+ sodipodi:nodetypes="cc" />
...
+ x="114.23286"
+ y="-66.184341"
+ style="font-size:1.95264852px;stroke-width:0.24408038">...
(to DRAM)
+ x="0.29872814"
+ y="141.18741"
+ style="font-style:italic;font-size:1.78992712px;fill:#000000;fill-opacity:1;stroke-width:0.2473968">(to DRAM)
+ width="12.915138"
+ height="3.6900384"
+ x="68.516579"
+ y="156.26907" />
SoC Regs
+ x="82.423203"
+ y="144.75549"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.22196229">SoC Regs
+ sodipodi:nodetypes="cc" />
+ width="16.605173"
+ height="5.5350604"
+ x="-128.59378"
+ y="39.025166"
+ transform="rotate(-90)" />
USB 1.1
+ x="-129.34341"
+ y="39.729866"
+ style="fill:#ffffff;fill-opacity:1;stroke-width:0.22626117">USB 1.1
+ sodipodi:nodetypes="cc" />
usb*
+ x="44.664764"
+ y="97.195976"
+ style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:1.79840517px;font-family:'DejaVu Sans Mono';-inkscape-font-specification:'DejaVu Sans Mono';text-align:center;text-anchor:middle;stroke-width:0.22480084">usb*
+ sodipodi:nodetypes="cc" />
+
+
+ Ara
diff --git a/docs/um/arch.md b/docs/um/arch.md
index cc5ea9390..26cf0e9b4 100644
--- a/docs/um/arch.md
+++ b/docs/um/arch.md
@@ -7,6 +7,7 @@ Cheshire is highly configurable; available features and resources depend on its
- **Cores**:
- Up to 31 Linux-capable CVA6 cores with self-invalidation-based coherence
- A RISC-V debug module with JTAG transport
+ - An Ara RISC-V vector accelerator
- **Peripherals**:
- Various standard IO interfaces (UART, I2C, SPI, and GPIOs)
@@ -135,6 +136,19 @@ Cheshire defaults on using CVA6 with hypervisor and CLIC support enabled; RV32 c
Each CVA6 core is a standalone AXI4 manager at the crossbar. Coherence is maintained through a self-invalidation scheme and RISC-V atomics are handled through a custom, user-channel-based AXI4 extension. For the latter, we wrap the cores and other managers to give each a default user channel assignment and, for atomics-capable managers, a unique ID on a slice of user bits.
+### Ara Vector Accelerator
+
+[Ara](https://github.com/pulp-platform/ara) is a RISC-V V vector coprocessor tightly coupled with CVA6. Ara can be instantiated in Cheshire to enable RISC-V V support. Ara exposes the following parameters:
+
+| Parameter | Type / Range | Description |
+| ------------------------ | ------------ | --------------------------------------------------------------- |
+| `Ara` | `bit` | Enable the Ara Vector Accelerator |
+| `AraNrLanes` | `byte_bt` | Number of parallel vector lanes in Ara |
+| `AraVlen` | `word_bt` | RISC-V V VLEN parameter (default vector register length in bit) |
+| `AraParMemReq` | `byte_bt` | Number of possible outstanding memory requests from Ara |
+
+Ara has a private AXI memory port resized to 64-bit to fit the current L2 memory bandwidth. Currently, we tested 2-lane Ara instances with `VLEN = 2048` without performance loss. Higher lane counts will instantiate a memory port with bandwidth greater than 64-bit/cycle. However, this will be bottlenecked by the current memory bandwidth (64-bit/cycle).
+
### Interconnect
The interconnect is composed of a main [AXI4](https://github.com/pulp-platform/axi) crossbar with AXI5 atomic operations (ATOPs) support and an auxiliary [Regbus](https://github.com/pulp-platform/register_interface) demultiplexer providing access to numerous peripherals and configuration interfaces. The Regbus has a static data width of 32 bit.
diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
index 185a06a0b..a4a209650 100644
--- a/hw/cheshire_pkg.sv
+++ b/hw/cheshire_pkg.sv
@@ -138,6 +138,7 @@ package cheshire_pkg;
bit Clic;
bit IrqRouter;
bit BusErr;
+ bit Ara;
// Parameters for Debug Module
jtag_idcode_t DbgIdCode;
dw_bt DbgMaxReqs;
@@ -196,6 +197,10 @@ package cheshire_pkg;
aw_bt AxiRtNumAddrRegions;
bit AxiRtCutPaths;
bit AxiRtEnableChecks;
+ // Parameters for Ara
+ byte_bt AraNrLanes;
+ word_bt AraVlen;
+ byte_bt AraParMemReq;
} cheshire_cfg_t;
//////////////////
@@ -295,6 +300,7 @@ package cheshire_pkg;
typedef struct packed {
aw_bt [2**MaxCoresWidth-1:0] cores;
aw_bt dbg;
+ aw_bt ara;
aw_bt dma;
aw_bt slink;
aw_bt vga;
@@ -308,6 +314,7 @@ package cheshire_pkg;
int unsigned i = 0;
for (int j = 0; j < cfg.NumCores; j++) begin ret.cores[i] = i; i++; end
ret.dbg = i;
+ if (cfg.Ara) begin i++; ret.ara = i; end
if (cfg.Dma) begin i++; ret.dma = i; end
if (cfg.SerialLink) begin i++; ret.slink = i; end
if (cfg.Vga) begin i++; ret.vga = i; end
@@ -499,9 +506,9 @@ package cheshire_pkg;
XF8ALT : 0,
RVA : 1,
RVB : 0,
- RVV : 0,
+ RVV : cfg.Ara,
RVC : 1,
- RVH : 1,
+ RVH : ~cfg.Ara,
RVZCB : 1,
XFVec : 0,
CvxifEn : 0,
@@ -612,6 +619,7 @@ package cheshire_pkg;
Clic : 0,
IrqRouter : 0,
BusErr : 1,
+ Ara : 0,
// Debug
DbgIdCode : CheshireIdCode,
DbgMaxReqs : 4,
@@ -669,6 +677,10 @@ package cheshire_pkg;
AxiRtWBufferDepth : 16,
AxiRtNumAddrRegions : 2,
AxiRtCutPaths : 1,
+ // Ara
+ AraNrLanes : 2,
+ AraVlen : 2048,
+ AraParMemReq : 4,
// All non-set values should be zero
default: '0
};
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index fe0979f6a..3358c56d8 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -556,6 +556,26 @@ module cheshire_soc import cheshire_pkg::*; #(
// TODO: Implement X interface support
+ // Accelerator ports
+ acc_pkg::accelerator_req_t acc_req;
+ acc_pkg::accelerator_resp_t acc_resp;
+
+ // CVA6-Ara memory consistency
+ logic acc_cons_en;
+ logic [Cfg.AddrWidth-1:0] inval_addr;
+ logic inval_valid;
+ logic inval_ready;
+
+ // Pack invalidation interface into acc interface
+ acc_pkg::accelerator_resp_t acc_resp_pack;
+ always_comb begin : pack_inval
+ acc_resp_pack = acc_resp;
+ acc_resp_pack.inval_valid = inval_valid;
+ acc_resp_pack.inval_addr = inval_addr;
+ inval_ready = acc_req.inval_ready;
+ acc_cons_en = acc_req.acc_cons_en;
+ end
+
`CHESHIRE_TYPEDEF_AXI_CT(axi_cva6, addr_t, cva6_id_t, axi_data_t, axi_strb_t, axi_user_t)
localparam config_pkg::cva6_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg);
@@ -606,6 +626,8 @@ module cheshire_soc import cheshire_pkg::*; #(
.axi_w_chan_t ( axi_cva6_w_chan_t ),
.b_chan_t ( axi_cva6_b_chan_t ),
.r_chan_t ( axi_cva6_r_chan_t ),
+ .cvxif_req_t ( acc_pkg::accelerator_req_t ),
+ .cvxif_resp_t ( acc_pkg::accelerator_resp_t ),
.noc_req_t ( axi_cva6_req_t ),
.noc_resp_t ( axi_cva6_rsp_t )
) i_core_cva6 (
@@ -626,8 +648,8 @@ module cheshire_soc import cheshire_pkg::*; #(
.clic_kill_req_i ( clic_irq_kill_req ),
.clic_kill_ack_o ( clic_irq_kill_ack ),
.rvfi_probes_o ( ),
- .cvxif_req_o ( ),
- .cvxif_resp_i ( '0 ),
+ .cvxif_req_o ( acc_req ),
+ .cvxif_resp_i ( acc_resp_pack ),
.noc_req_o ( core_out_req ),
.noc_resp_i ( core_out_rsp )
);
@@ -747,6 +769,105 @@ module cheshire_soc import cheshire_pkg::*; #(
.mst_req_o ( axi_in_req[AxiIn.cores[i]] ),
.mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] )
);
+
+ // Generate Ara RVV vector processor if enabled
+ if (Cfg.Ara) begin : gen_ara
+ // Configure Ara with the right AXI id width
+ typedef logic [Cfg.AxiMstIdWidth-1:0] ara_id_t;
+ // Default Ara AXI data width
+ localparam int unsigned AraDataWideWidth = 32 * Cfg.AraNrLanes;
+ typedef logic [AraDataWideWidth -1 : 0] axi_ara_wide_data_t;
+ typedef logic [AraDataWideWidth/8 -1 : 0] axi_ara_wide_strb_t;
+ `AXI_TYPEDEF_ALL(
+ axi_ara_wide, addr_t, ara_id_t, axi_ara_wide_data_t, axi_ara_wide_strb_t, axi_user_t)
+ axi_ara_wide_req_t axi_ara_wide_req_inval, axi_ara_wide_req;
+ axi_ara_wide_resp_t axi_ara_wide_resp_inval, axi_ara_wide_resp;
+
+ axi_mst_req_t axi_ara_narrow_req;
+ axi_mst_rsp_t axi_ara_narrow_resp;
+
+ ara #(
+ .NrLanes ( Cfg.AraNrLanes ),
+ .VLEN ( Cfg.AraVlen ),
+ .AxiDataWidth ( AraDataWideWidth ),
+ .AxiAddrWidth ( Cfg.AddrWidth ),
+ .axi_ar_t ( axi_ara_wide_ar_chan_t ),
+ .axi_r_t ( axi_ara_wide_r_chan_t ),
+ .axi_aw_t ( axi_ara_wide_aw_chan_t ),
+ .axi_w_t ( axi_ara_wide_w_chan_t ),
+ .axi_b_t ( axi_ara_wide_b_chan_t ),
+ .axi_req_t ( axi_ara_wide_req_t ),
+ .axi_resp_t ( axi_ara_wide_resp_t )
+ ) i_ara (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+ .scan_enable_i ( 1'b0 ),
+ .scan_data_i ( 1'b0 ),
+ .scan_data_o ( /* Unused */ ),
+ .acc_req_i ( acc_req ),
+ .acc_resp_o ( acc_resp ),
+ .axi_req_o ( axi_ara_wide_req ),
+ .axi_resp_i ( axi_ara_wide_resp )
+ );
+
+ // Issue invalidations to CVA6 L1D$
+ axi_inval_filter #(
+ .MaxTxns ( Cfg.AraParMemReq ),
+ .AddrWidth ( Cfg.AddrWidth ),
+ .L1LineWidth( ariane_pkg::DCACHE_LINE_WIDTH/8 ),
+ .aw_chan_t ( axi_ara_wide_aw_chan_t ),
+ .req_t ( axi_ara_wide_req_t ),
+ .resp_t ( axi_ara_wide_resp_t )
+ ) i_ara_axi_inval_filter (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+ .en_i ( acc_cons_en ),
+ .slv_req_i ( axi_ara_wide_req ),
+ .slv_resp_o ( axi_ara_wide_resp ),
+ .mst_req_o ( axi_ara_wide_req_inval ),
+ .mst_resp_i ( axi_ara_wide_resp_inval ),
+ .inval_addr_o ( inval_addr ),
+ .inval_valid_o( inval_valid ),
+ .inval_ready_i( inval_ready )
+ );
+
+ // Convert from AraDataWideWidth (axi_ara_wide) to Cfg.AxiDataWidth (axi_ara_narrow)
+ axi_dw_converter #(
+ .AxiSlvPortDataWidth ( AraDataWideWidth ),
+ .AxiMstPortDataWidth ( Cfg.AxiDataWidth ),
+ .AxiMaxReads ( Cfg.AraParMemReq ),
+ .AxiAddrWidth ( Cfg.AddrWidth ),
+ .AxiIdWidth ( Cfg.AxiMstIdWidth ),
+ .aw_chan_t ( axi_ara_wide_aw_chan_t ),
+ .mst_w_chan_t ( axi_mst_w_chan_t ),
+ .slv_w_chan_t ( axi_ara_wide_w_chan_t ),
+ .b_chan_t ( axi_ara_wide_b_chan_t ),
+ .ar_chan_t ( axi_ara_wide_ar_chan_t ),
+ .mst_r_chan_t ( axi_mst_r_chan_t ),
+ .slv_r_chan_t ( axi_ara_wide_r_chan_t ),
+ .axi_mst_req_t ( axi_mst_req_t ),
+ .axi_mst_resp_t ( axi_mst_rsp_t ),
+ .axi_slv_req_t ( axi_ara_wide_req_t ),
+ .axi_slv_resp_t ( axi_ara_wide_resp_t )
+ ) i_ara_axi_dw_converter (
+ .clk_i ( clk_i ),
+ .rst_ni ( rst_ni ),
+ .slv_req_i ( axi_ara_wide_req_inval ),
+ .slv_resp_o ( axi_ara_wide_resp_inval ),
+ .mst_req_o ( axi_ara_narrow_req ),
+ .mst_resp_i ( axi_ara_narrow_resp )
+ );
+
+ // Assign to crossbar input/master
+ assign axi_in_req[AxiIn.ara] = axi_ara_narrow_req;
+ assign axi_ara_narrow_resp = axi_in_rsp[AxiIn.ara];
+
+ end else begin : gen_no_ara
+ // Tie-to-safe the Ara-related signals
+ assign acc_resp = '0;
+ assign inval_valid = '0;
+ assign inval_addr = '0;
+ end
end
/////////////////////////
@@ -1729,4 +1850,7 @@ module cheshire_soc import cheshire_pkg::*; #(
// TODO: many other things I most likely forgot
// TODO: check that LLC only exists if its output is connected (the reverse is allowed)
+ if (Cfg.Ara && (NumIntHarts > 1))
+ $error("Ara is only compatible with a single-core architecture.");
+
endmodule
diff --git a/target/sim/src/tb_cheshire_pkg.sv b/target/sim/src/tb_cheshire_pkg.sv
index 77ab78a2b..08f2ae01a 100644
--- a/target/sim/src/tb_cheshire_pkg.sv
+++ b/target/sim/src/tb_cheshire_pkg.sv
@@ -16,11 +16,21 @@ package tb_cheshire_pkg;
return ret;
endfunction
+ // A dedicated Ara config
+ function automatic cheshire_cfg_t gen_cheshire_ara_cfg();
+ cheshire_cfg_t ret = DefaultCfg;
+ ret.Ara = 1;
+ ret.AraNrLanes = 2;
+ ret.AraVlen = 2048;
+ return ret;
+ endfunction
+
// Number of Cheshire configurations
- localparam int unsigned NumCheshireConfigs = 32'd2;
+ localparam int unsigned NumCheshireConfigs = 32'd3;
// Assemble a configuration array indexed by a numeric parameter
localparam cheshire_cfg_t [NumCheshireConfigs-1:0] TbCheshireConfigs = {
+ gen_cheshire_ara_cfg(), // 2: Ara-enabled configuration
gen_cheshire_rt_cfg(), // 1: RT-enabled configuration
DefaultCfg // 0: Default configuration
};