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target/xilinx: Clean up and converge top level RTL #41

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paulsc96 opened this issue May 25, 2023 · 2 comments
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target/xilinx: Clean up and converge top level RTL #41

paulsc96 opened this issue May 25, 2023 · 2 comments

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@paulsc96
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Clean up FPGA (Genesys2) top-level RTL and converge to default config (e.g. RTC).
@paulsc96 paulsc96 changed the title target/fpga: Clean up and converge top level RTL target/xilinx: Clean up and converge top level RTL May 25, 2023
@paulsc96 paulsc96 mentioned this issue Oct 3, 2023
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@paulsc96
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paulsc96 commented Mar 1, 2024

#105 Cleans up flow.

Following PRs will (hopefully) reconverge config.

@paulsc96
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Fixed in #105

Aquaticfuller pushed a commit that referenced this issue Jul 16, 2024
@alex96295
Merge pull request #41 from pulp-platform/aottaviano/l2-atomics
e738725 
Add atomics support to shared L2 memory
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