From f1bcd4018c74c937ecdd06f6d81faa61eb7eef9f Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Fri, 5 May 2023 16:26:37 +0200 Subject: [PATCH] fpga: Reworked fully FPGA flow, added support and CI for VCU128, added Vivado IP simulation flow fpga: Added ddr4 and vcu128 flow, added draft of Vivado IP simulation flow fpga: Added VIOs Connect VIO-generated reset signal to dram wrapper fpga: Support of zcu102 fpga: zcu102.xdc constraint file added fpga: zcu102 changed phy and added firsts constraints fpga: Switching to clk_wiz and xilinx.mk fpga: Testing ddr4 fpga: Start working on SPI driver Co-Authored-By: Yann Picod fpga: SD card test fpga: Rolled-back SD fpga: Add vcu128 ci fpga: Debug new CI fpga: Adding artifacts management fpga: Added ID serializer in dram_wrapper and changed a few xdc constraints fpga: Correcting artifacts mngmt and applied new constraints to genesys2 fpga: Corrected vivado sim script fpga: Last review updates fpga: Last review updates 2 fpga: Updated artifact management to take select only useful envvar fpga: Update cva6-sdk, add openocd configs, and update docs fpga: Use https for cva6-sdk fpga: Removed a few phonies/variable defined targets fpga: Moved to flavoured flow --- Bender.yml | 13 +- README.md | 2 + cheshire.mk | 12 +- docs/tg/xilinx.md | 197 +- sw/boot/{cheshire.dts => cheshire.dtsi} | 12 +- sw/boot/cheshire_genesys2_vanilla.dts | 18 + sw/boot/cheshire_vcu128_bd.dts | 27 + sw/boot/cheshire_vcu128_vanilla.dts | 27 + sw/boot/zsl.c | 2 +- sw/deps/cva6-sdk | 2 +- sw/include/params.h | 3 + sw/lib/hal/uart_debug.c | 2 +- sw/sw.mk | 11 +- sw/tests/helloworld.c | 2 +- target/xilinx/Makefile | 71 - target/xilinx/constraints/cheshire.xdc | 153 -- .../flavor_bd/constraints/ooc_cheshire_ip.xdc | 5 + .../xilinx/flavor_bd/constraints/vcu128.xdc | 30 + .../flavor_bd/constraints/vcu128_ext_jtag.xdc | 17 + target/xilinx/flavor_bd/flavor_bd.mk | 50 + .../scripts/cheshire_bd_ext_jtag.tcl | 18 + .../flavor_bd/scripts/cheshire_bd_vcu128.tcl | 526 +++++ target/xilinx/flavor_bd/scripts/run.tcl | 131 ++ .../flavor_bd/scripts/run_cheshire_ip.tcl | 32 + .../flavor_bd/src/cheshire_ip_wrapper.v | 441 ++++ .../flavor_bd/src/cheshire_top_xilinx.sv | 676 ++++++ .../imports/constraints/cheshire.xdc | 93 + .../imports}/constraints/genesys2.xdc | 118 +- .../flavor_vanilla/constraints/cheshire.xdc | 93 + .../flavor_vanilla/constraints/genesys2.xdc | 540 +++++ .../flavor_vanilla/constraints/vcu128.xdc | 1810 +++++++++++++++++ .../xilinx/flavor_vanilla/flavor_vanilla.mk | 62 + target/xilinx/flavor_vanilla/scripts/run.tcl | 141 ++ .../flavor_vanilla/sim/run_simulation.tcl | 48 + .../flavor_vanilla/sim/setup_simulation.tcl | 32 + target/xilinx/flavor_vanilla/sim/sim.mk | 58 + .../src/cheshire_top_xilinx.sv | 490 +++-- .../flavor_vanilla/src/dram_wrapper_xilinx.sv | 377 ++++ .../{ => flavor_vanilla}/src/fan_ctrl.sv | 0 .../flavor_vanilla/src/phy_definitions.svh | 93 + target/xilinx/scripts/flash_spi.tcl | 48 + target/xilinx/scripts/program.tcl | 28 +- target/xilinx/scripts/prologue.tcl | 17 - target/xilinx/scripts/run.tcl | 80 - target/xilinx/xilinx.mk | 113 + target/xilinx/xilinx/common.mk | 27 - .../xilinx/xlnx_protocol_checker/Makefile | 6 - .../xilinx/xlnx_protocol_checker/tcl/run.tcl | 40 - .../xilinx/{xilinx => xilinx_ips}/.gitignore | 0 target/xilinx/xilinx_ips/common.mk | 65 + .../xilinx/xilinx_ips/xlnx_clk_wiz/Makefile | 10 + .../xilinx_ips/xlnx_clk_wiz/tcl/run.tcl | 113 + .../xlnx_mig_7_ddr3/Makefile | 5 +- .../xlnx_mig_7_ddr3/mig_genesys2.prj | 9 +- .../xlnx_mig_7_ddr3/mig_kc705.prj | 0 .../xlnx_mig_7_ddr3/mig_vc707.prj | 0 .../xlnx_mig_7_ddr3/tcl/run.tcl | 4 +- .../xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile | 10 + .../xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl | 62 + target/xilinx/xilinx_ips/xlnx_vio/Makefile | 10 + target/xilinx/xilinx_ips/xlnx_vio/tcl/run.tcl | 41 + util/openocd_genesys2.cfg | 34 + util/openocd_hs2.cfg | 35 + util/openocd_vcu128.cfg | 34 + 64 files changed, 6519 insertions(+), 707 deletions(-) rename sw/boot/{cheshire.dts => cheshire.dtsi} (94%) create mode 100644 sw/boot/cheshire_genesys2_vanilla.dts create mode 100644 sw/boot/cheshire_vcu128_bd.dts create mode 100644 sw/boot/cheshire_vcu128_vanilla.dts delete mode 100644 target/xilinx/Makefile delete mode 100644 target/xilinx/constraints/cheshire.xdc create mode 100644 target/xilinx/flavor_bd/constraints/ooc_cheshire_ip.xdc create mode 100644 target/xilinx/flavor_bd/constraints/vcu128.xdc create mode 100644 target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc create mode 100644 target/xilinx/flavor_bd/flavor_bd.mk create mode 100644 target/xilinx/flavor_bd/scripts/cheshire_bd_ext_jtag.tcl create mode 100644 target/xilinx/flavor_bd/scripts/cheshire_bd_vcu128.tcl create mode 100644 target/xilinx/flavor_bd/scripts/run.tcl create mode 100644 target/xilinx/flavor_bd/scripts/run_cheshire_ip.tcl create mode 100644 target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v create mode 100644 target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv create mode 100644 target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/cheshire.xdc rename target/xilinx/{ => flavor_vanilla/cheshire.srcs/constrs_1/imports}/constraints/genesys2.xdc (92%) create mode 100644 target/xilinx/flavor_vanilla/constraints/cheshire.xdc create mode 100644 target/xilinx/flavor_vanilla/constraints/genesys2.xdc create mode 100644 target/xilinx/flavor_vanilla/constraints/vcu128.xdc create mode 100644 target/xilinx/flavor_vanilla/flavor_vanilla.mk create mode 100644 target/xilinx/flavor_vanilla/scripts/run.tcl create mode 100644 target/xilinx/flavor_vanilla/sim/run_simulation.tcl create mode 100644 target/xilinx/flavor_vanilla/sim/setup_simulation.tcl create mode 100644 target/xilinx/flavor_vanilla/sim/sim.mk rename target/xilinx/{ => flavor_vanilla}/src/cheshire_top_xilinx.sv (51%) create mode 100644 target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv rename target/xilinx/{ => flavor_vanilla}/src/fan_ctrl.sv (100%) create mode 100644 target/xilinx/flavor_vanilla/src/phy_definitions.svh create mode 100644 target/xilinx/scripts/flash_spi.tcl delete mode 100644 target/xilinx/scripts/prologue.tcl delete mode 100644 target/xilinx/scripts/run.tcl create mode 100644 target/xilinx/xilinx.mk delete mode 100644 target/xilinx/xilinx/common.mk delete mode 100644 target/xilinx/xilinx/xlnx_protocol_checker/Makefile delete mode 100644 target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl rename target/xilinx/{xilinx => xilinx_ips}/.gitignore (100%) create mode 100644 target/xilinx/xilinx_ips/common.mk create mode 100644 target/xilinx/xilinx_ips/xlnx_clk_wiz/Makefile create mode 100644 target/xilinx/xilinx_ips/xlnx_clk_wiz/tcl/run.tcl rename target/xilinx/{xilinx => xilinx_ips}/xlnx_mig_7_ddr3/Makefile (54%) rename target/xilinx/{xilinx => xilinx_ips}/xlnx_mig_7_ddr3/mig_genesys2.prj (97%) rename target/xilinx/{xilinx => xilinx_ips}/xlnx_mig_7_ddr3/mig_kc705.prj (100%) rename target/xilinx/{xilinx => xilinx_ips}/xlnx_mig_7_ddr3/mig_vc707.prj (100%) rename target/xilinx/{xilinx => xilinx_ips}/xlnx_mig_7_ddr3/tcl/run.tcl (93%) create mode 100644 target/xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile create mode 100644 target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl create mode 100644 target/xilinx/xilinx_ips/xlnx_vio/Makefile create mode 100644 target/xilinx/xilinx_ips/xlnx_vio/tcl/run.tcl create mode 100644 util/openocd_genesys2.cfg create mode 100644 util/openocd_hs2.cfg create mode 100644 util/openocd_vcu128.cfg diff --git a/Bender.yml b/Bender.yml index 8b2b64e9..f0eb1563 100644 --- a/Bender.yml +++ b/Bender.yml @@ -50,7 +50,14 @@ sources: - target/sim/src/fixture_cheshire_soc.sv - target/sim/src/tb_cheshire_soc.sv - - target: all(fpga, xilinx) + - target: all(fpga, xilinx, xilinx_vanilla) files: - - target/xilinx/src/fan_ctrl.sv - - target/xilinx/src/cheshire_top_xilinx.sv + - target/xilinx/flavor_vanilla/src/fan_ctrl.sv + - target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv + - target/xilinx/flavor_vanilla/src/phy_definitions.svh + - target/xilinx/flavor_vanilla/src/cheshire_top_xilinx.sv + + - target: all(fpga, xilinx, xilinx_bd) + files: + - target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v + - target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv diff --git a/README.md b/README.md index 2cf18f38..90b1215a 100644 --- a/README.md +++ b/README.md @@ -19,6 +19,8 @@ source start.cheshire_soc.tcl run -all ``` +If you have access to our internal servers, you can run `make nonfree-init` to fetch additional resources we cannot make publically accessible. Note that these are *not required* to use anything provided in this repository. + ## License Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license. All hardware sources and tool scripts are licensed under the Solderpad Hardware License 0.51 (see `LICENSE`) with the exception of generated register file code (e.g. `hw/regs/*.sv`), which is generated by a fork of lowRISC's [`regtool`](https://github.com/lowRISC/opentitan/blob/master/util/regtool.py) and licensed under Apache 2.0. All software sources are licensed under Apache 2.0. diff --git a/cheshire.mk b/cheshire.mk index 77663395..e600ebbd 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -53,7 +53,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= dafd3c1 +CHS_NONFREE_COMMIT ?= d31389c3b559e48496b7264a55ae33eda994bded chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree @@ -155,13 +155,10 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl ############# -# FPGA Flow # +# Emulation # ############# -$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml - $(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@ - -CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl +include $(CHS_ROOT)/target/xilinx/xilinx.mk ################################# # Phonies (KEEP AT END OF FILE) # @@ -169,11 +166,10 @@ CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl .PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all -CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) $(CHS_XILINX_ALL) +CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) chs-all: $(CHS_ALL) chs-sw-all: $(CHS_SW_ALL) chs-hw-all: $(CHS_HW_ALL) chs-bootrom-all: $(CHS_BOOTROM_ALL) chs-sim-all: $(CHS_SIM_ALL) -chs-xilinx-all: $(CHS_XILINX_ALL) diff --git a/docs/tg/xilinx.md b/docs/tg/xilinx.md index e6664988..83ef53d0 100644 --- a/docs/tg/xilinx.md +++ b/docs/tg/xilinx.md @@ -7,38 +7,109 @@ This page describes how to map Cheshire on Xilinx FPGAs to *execute baremetal pr We currently provide working setups for: - Digilent Genesys 2 with Vivado `>= 2020.2` +- Xilinx VCU128 with Vivado `>= 2020.2` We are working on support for more boards in the future. -## Implementation +## Building the bistream -Since the implementation steps and available features vary between boards, we provide instructions and document available features for each. +Do to the structure of the Makefile flow. All the following commands are to be executed at the root of the Cheshire repository. If you want to see the targets that you will be using, you can find them in `sw/sw.mk` and `target/xilinx/xilinx.mk`. -### Digilent Genesys 2 +First, make sure that you have generated all the RTL: + +```bash +make chs-hw-all +``` Generate the bitstream `target/xilinx/out/cheshire_top_xilinx.bit` by running: +```bash +make chs-xil-all [VIVADO=version] [BOARD={genesys2,vcu128}] [MODE={batch,gui}] [INT-JTAG={0,1}] ``` -make -C target/xilinx + +See the argument list below: + +| Argument | Relevance | Description | +|----------|-----------|---------------------------------------------------------------------------------------------------------------------------------------| +| VIVADO | all | Vivado command to use **(default "vitis-2020.2 vivado")** | +| BOARD | all | `genesys-2` **(default)**
`vcu128` | +| INT-JTAG | vcu128 | `0` Connect the RV debug module to an external JTAG chain
`1` Connect the RV debug module to the internal JTAG chain **(default)** | +| MODE | all | `batch` Compile in Vivado shell
`gui` Compile in Vivado gui | + +The build time takes a couple of hours. + +The above target used Bender and the file `Bender.yml` to generate the filelist required for Vivado. You can find it in + +## Board specificities + +### Digilent Genesys 2 +> ##### Bootmode and switches +> +> Before flashing the bitstream to your device, take note of the position of onboard switches, which control important functionality: +> +> +> | Switch | Function | +> | ------ | ------------------------------------------------| +> | 1 .. 0 | Boot mode; see [Boot ROM](../um/sw.md#boot-rom) | +> | 5 .. 2 | Fan level; *do not* keep at 0 | +> | 7 | Test mode; *leave at zero* | +> +> The reset, JTAG TAP, UART, I2C, and VGA are all connected to their onboard logic or ports. The UART has *no flow control*. The microSD slot is connected to chip select 0 of the SPI host peripheral. Serial link and GPIOs are currently not available. +> +### Xilinx VCU128 +> #### Bootmode and VIOs +> +> As there are no switches on this board, the CVA6 bootmode (see [Boot ROM](../um/sw.md#boot-rom)) is selected by Xilinx VIOs that can be set in the Vivado GUI (see [Using Vivado GUI](#bringup_vivado_gui)). +> +> #### External JTAG chain +> +> The VCU128 development board only provides one JTAG chain, used by Vivado to program the bitstream, and interact with certain IPs (ILAs, VIOs, ...). The RV64 host also requires a JTAG chain to connect GDB to the debug-module in the bitstream. It is possible to use the same JTAG chain for both by using `INT-JTAG=1`. In this case no external cable is required but it will not be possible to use GDB (to debug the program running on the host) and communicate with the bitstream (to debug signals using ILAs) at the same time. By using `INT-JTAG=0` it is possible to add an external JTAG chain for the RV64 host through GPIOs. Since the VCU128 does not have GPIOs we use we use a Digilent JTAG-HS2 cable connected to the Xilinx XM105 FMC debug card. See the connections in `vcu128.xdc`. + +## Bare-metal bringup + +### Programming the FPGA + +#### Using Vivado GUI + +If you have closed Vivado, or compiled in batch mode, you can open the Vivado GUI with: + +```bash +make chs-xil-gui ``` -Before flashing the bitstream to your device, take note of the position of onboard switches, which control important functionality: +You can now open the Hardware Manager and program the FPGA. Once done, Vivado will give you access the to Virtual Inputs Outputs (VIOs). You can now assert the following signals (on Cheshire top level). + | VIO | Function | + | ----------------- | ----------------------------------------------------------------| + | vio_reset | Positive edge-sensitive reset for the whole system | + | vio_boot_mode | Override the boot-mode switches described above | + | vio_boot_mode_sel | Select between 0: using boot mode switches 1: use boot mode VIO | - | Switch | Function | - | ------ | ------------------------------------------------| - | 1 .. 0 | Boot mode; see [Boot ROM](../um/sw.md#boot-rom) | - | 5 .. 2 | Fan level; *do not* keep at 0 | - | 7 | Test mode; *leave at zero* | +#### Using command line -The reset, JTAG TAP, UART, I2C, and VGA are all connected to their onboard logic or ports. The UART has *no flow control*. The microSD slot is connected to chip select 0 of the SPI host peripheral. Serial link and GPIOs are currently not available. +A script `program.tcl` is available to flash the bitstream without opening Vivado GUI. You will need to give the following variable to access your board (see `target/xilinx/xilinx.mk`). -## Debugging with OpenOCD +- `XILINX_PORT`: Vivado opened port (**default 3121**) +- `FPGA_PATH`: Vivado path to your FPGA (**default xilinx_tcf/Xilinx/[serial_id]**) +- `XILINX_HOST`: Path to your Vivado server (**default localhost**) -To establish a debug bridge over JTAG, ensure the target is in a debuggable state (for example by resetting into the idle boot mode 0) and launch OpenOCD with: +Change the values to the appropriate ones (can be found in the Vivado GUI) and programm the board: +```bash +make chs-xil-program MODE=batch BOARD=vcu128 ``` -openocd -f $(bender path ariane)/corev_apu/fpga/ariane.cfg + +### Loading binary and debugging with OpenOCD + +To establish a debug bridge over JTAG, ensure the target is in a debuggable state (for example by setting the boot mode to 0 before resetting) then launch OpenOCD with: + +```bash +# VCU128 : Internal JTAG +openocd -f util/openocd_vcu128.cfg +# Genesys2 : Internal JTAG +oprnocd -f util/openocd_genesys2.cfg +# All boards : External JTAG (Digilent HS2) +openocd -f util/openocd_hs2.cfg ``` In another shell, launch a RISC-V GDB session attaching to OpenOCD: @@ -78,7 +149,7 @@ continue You should see `Hello World!` output printed on the UART. -### Boot from SD Card +### Load from SD Card (Genesys2) First, build an up-to-date a disk image for your desired binary. For `helloworld`: @@ -95,39 +166,101 @@ sudo sgdisk -e /dev/ The second command only ensures correctness of the partition layout; it moves the secondary GPT header at the end of the minimally sized image to the end of your actual SD card. -Insert your SD card and reset into boot mode 1. You should see a `Hello World!` UART output. +Insert your SD card and reset into __boot mode 1__. You should see a `Hello World!` UART output. ## Booting Linux To boot Linux, we must load the *OpenSBI* firmware, which takes over M mode and launches the U-boot bootloader. U-boot then loads Linux. For more details, see [Boot Flow](../um/sw.md#boot-flow). -Clone the `cheshire` branch of CVA6 SDK and build the firmware (OpenSBI + U-boot) and Linux images (*this will take about 30 minutes*): +Clone the `cheshire` branch of CVA6 SDK into `sw/deps/cva6-sdk` and build the firmware (OpenSBI + U-boot) and Linux images (*this will take about 30 minutes*): -``` +```bash git submodule update --init --recursive sw/deps/cva6-sdk make -C sw/deps/cva6-sdk images ``` -In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI, and instructing U-boot to load the kernel directly from memory. Here, we focus on autonomous boot from SD card. +In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI, and instructing U-boot to load the kernel directly from memory. Here, we focus on autonomous boot from SD card or SPI flash. In this case, OpenSBI is loaded by a regular baremetal program called the [Zero-Stage Loader](../um/sw.md#zero-stage-loader) (ZSL). The [boot ROM](../um/sw.md#boot-rom) loads the ZSL from SD card, which then loads the device tree and firmware from other SD card partitions into memory and launches OpenSBI. To create a full Linux disk image from the ZSL, device tree, firmware, and Linux, run: +```bash +# Note that the device tree's flavor depends on the board (see sw/boot/*.dts) +make chs-linux-img BOARD=[genesys2, vcu128] ``` -make sw/boot/linux.gpt.bin + +### Digilent Genesys 2 +> +> Flash this image to an SD card as for the hello world (see [Load from SD Card](#bringup_flash_sd)), then insert the SD card and reset into boot mode 1. You should first see the ZSL print on the UART: +> +> ``` +> /\___/\ Boot mode: 1 +> ( o o ) Real-time clock: ... Hz +> ( =^= ) System clock: ... Hz +> ( ) Read global ptr: 0x... +> ( P ) Read pointer: 0x... +> ( U # L ) Read argument: 0x... +> ( P ) +> ( )))))))))) +> ``` +> You should then boot through OpenSBI, U-Boot, and Linux until you are dropped into a shell. +> +### Xilinx VCU128 +> +> This board does not offer a SD card reader. We need to load the image in the integrated flash: +> +> ``` +> make chs-xil-flash MODE=batch BOARD=vcu128 +> ``` +> +> Use the parameters defined in [Using command line](#bringup_vivado_cli) (defaults are in `target/xilinx/xilinx.mk`) to select your board: +> +> This script will erase your bitstream, once the flash has been written (c.a. 10min) you will need to re-program the bitstream on the board. + +## Add your own board + +If you wish to add a flow for a new FPGA board, please do the following steps: +_Please consider opening a pull request containing the necessary changes to integrate your new board (:_ + +### Makefile + +Add your board on top of `target/xilinx/xilinx.mk`, in particular `XILINX_PART` and `XILINX_BOARD` are identifying the FPGA chip and board (can be found in VIvado GUI). The parameters identifying your personal device `XILINX_PORT`, `FPGA_PATH`, `XILINX_HOST` can be left empty for now. +You then need to define `ip-names` with the Xilinx IPs that you will be using: DDR3/4 depending on your board, Clock Wizard, VIOs. See next sections for more explanations. + +### Vivado IPs + +#### Re-arametrize existing IPs + +Cheshire's emulation requires a few Vivado IPs to work properly. They are defined and pre-compiled in `target/xilinx/xilinx/*`. +If you add a new board, you will need to reconfigure your IPs for this board. For instance, to use the _Vivado MIG DDR4 controller_, modify `target/xilinx/xilinx/xlnx_mig_ddr4/run.tcl`. There, add the relvant `$::env(BOARD)` entry with your configuration. +To know which configuration to use your board, you can open a blank project in Vivado GUI, create a blank block design, and instanciate the MIG DDR4 IP there. The Vivado TCL console should write the default parameters for your FPGA. You can later re-configure the IP in the block design and Vivado will print to the tcl console the modified parameters. Then yuo can copy these tcl lines to the `run.tcl` file. Make sure that you added your ip to `target/xilinx/xilinx.mk` under "ip-names". + +#### Add a new IP + +If your board require a new IP that has not been integrated already do the following : + +- Add a new folder `target/xilinx/xilinx/[your_ip]` taking the example of the `xlnx_mig_ddr4`. +- Modify `target/xilinx/xilinx/[your_ip]/tcl/run.tcl` and `target/xilinx/xilinx/[your_ip]/Makefile` accordingly. +- Add your IP to `target/xilinx/xilinx.mk` under "ip-names". + +#### Instantiate your IP + +Connect it's top module in the top-level: `target/xilinx/src/cheshire_top_xilinx.sv` (you can already ). If your IP is a DDR controller, please add it to `target/xilinx/src/dram_wrapper_xilinx.sv`. Note that this file contains a pipeline to resize AXI transactions from Cheshire to your controller. + +Add the relevant macro parameters to `target/xilinx/src/phy_definitions.sv` in order to disable your IP for non-relevant boards. + +#### Debug + +It is possible to use ILA (Integrated Logic Analyzers) in order to debug some signals on the running FPGA. Add the following before declaring your signals: + +```verilog + // Indicate that you need to debug a signal + (* dont_touch = "yes" *) (* mark_debug = "true" *) logic signal_d0; + // You can also use the following macro from phy_definitions.svh + `ila(ila_signal_d0, signal_d0) ``` -Flash this image to an SD card as you did in the previous section, then insert the SD card and reset into boot mode 1. You should first see the ZSL print on the UART: +Then, re-build your bitstream. -``` - /\___/\ Boot mode: 1 -( o o ) Real-time clock: ... Hz -( =^= ) System clock: ... Hz -( ) Read global ptr: 0x... -( P ) Read pointer: 0x... -( U # L ) Read argument: 0x... -( P ) -( )))))))))) -``` -You should then boot through OpenSBI, U-Boot, and Linux until you are dropped into a shell. +It is also possible to simulate your IPs with `target/xilinx/sim` (undocumented yet). diff --git a/sw/boot/cheshire.dts b/sw/boot/cheshire.dtsi similarity index 94% rename from sw/boot/cheshire.dts rename to sw/boot/cheshire.dtsi index dbef5e50..76decc85 100644 --- a/sw/boot/cheshire.dts +++ b/sw/boot/cheshire.dtsi @@ -7,11 +7,13 @@ // Axel Vanoni /dts-v1/; + / { #address-cells = <2>; #size-cells = <2>; compatible = "eth,cheshire-dev"; model = "eth,cheshire"; + chosen { stdout-path = "/soc/serial@3002000:115200"; }; @@ -74,22 +76,16 @@ interrupts = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>; reg = <0x0 0x3003000 0x0 0x1000>; }; - spi@3004000 { + spi: spi@3004000 { compatible = "opentitan,spi-host", "lowrisc,spi"; interrupt-parent = <&PLIC0>; interrupts = <17 18>; reg = <0x0 0x3004000 0x0 0x1000>; + num-cs = <2>; clock-frequency = <50000000>; max-frequency = <25000000>; #address-cells = <1>; #size-cells = <0>; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <25000000>; - voltage-ranges = <3300 3300>; - disable-wp; - }; }; vga@3007000 { compatible = "eth,axi-vga"; diff --git a/sw/boot/cheshire_genesys2_vanilla.dts b/sw/boot/cheshire_genesys2_vanilla.dts new file mode 100644 index 00000000..e26aa6f9 --- /dev/null +++ b/sw/boot/cheshire_genesys2_vanilla.dts @@ -0,0 +1,18 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; // CS + spi-max-frequency = <25000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; diff --git a/sw/boot/cheshire_vcu128_bd.dts b/sw/boot/cheshire_vcu128_bd.dts new file mode 100644 index 00000000..c2a3528d --- /dev/null +++ b/sw/boot/cheshire_vcu128_bd.dts @@ -0,0 +1,27 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <1>; + nor@1 { + #address-cells = <0x1>; + #size-cells = <0x1>; + // Note : u-boot does not find mt25qu02g + compatible = "mt25qu02g", "jedec,spi-nor"; + reg = <0x1>; // CS + spi-max-frequency = <25000000>; + spi-rx-bus-width = <0x1>; + spi-tx-bus-width = <0x1>; + disable-wp; + partition@0 { + label = "all"; + reg = <0x0 0x6000000>; // 96 MB + read-only; + }; + }; +}; diff --git a/sw/boot/cheshire_vcu128_vanilla.dts b/sw/boot/cheshire_vcu128_vanilla.dts new file mode 100644 index 00000000..c2a3528d --- /dev/null +++ b/sw/boot/cheshire_vcu128_vanilla.dts @@ -0,0 +1,27 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <1>; + nor@1 { + #address-cells = <0x1>; + #size-cells = <0x1>; + // Note : u-boot does not find mt25qu02g + compatible = "mt25qu02g", "jedec,spi-nor"; + reg = <0x1>; // CS + spi-max-frequency = <25000000>; + spi-rx-bus-width = <0x1>; + spi-tx-bus-width = <0x1>; + disable-wp; + partition@0 { + label = "all"; + reg = <0x0 0x6000000>; // 96 MB + read-only; + }; + }; +}; diff --git a/sw/boot/zsl.c b/sw/boot/zsl.c index ea85852a..06d79dc2 100644 --- a/sw/boot/zsl.c +++ b/sw/boot/zsl.c @@ -60,7 +60,7 @@ int main(void) { void *priv = (void *)(uintptr_t)*reg32(&__base_regs, CHESHIRE_SCRATCH_1_REG_OFFSET); // Initialize UART - uart_init(&__base_uart, core_freq, 115200); + uart_init(&__base_uart, core_freq, __BAUDRATE); // Print boot-critical cat, and also parameters printf(" /\\___/\\ Boot mode: %d\r\n" diff --git a/sw/deps/cva6-sdk b/sw/deps/cva6-sdk index 3b08b0ea..1d4ef36b 160000 --- a/sw/deps/cva6-sdk +++ b/sw/deps/cva6-sdk @@ -1 +1 @@ -Subproject commit 3b08b0ea40a259c13443c50e506e6998e73ae1f5 +Subproject commit 1d4ef36baba9ecc63528fa2c0f6fa49db8fb0fbb diff --git a/sw/include/params.h b/sw/include/params.h index b1e6990f..1fc39dcb 100644 --- a/sw/include/params.h +++ b/sw/include/params.h @@ -30,6 +30,9 @@ extern void *__base_axirtgrd; extern void *__base_spm; extern void *__base_dram; +// ZSL baudrate (may be overriden on slower SoCs) +static const uint32_t __BAUDRATE = 115200; + // Maximum number of LBAs to copy to SPM for boot (48 KiB) static const uint64_t __BOOT_SPM_MAX_LBAS = 2 * 48; diff --git a/sw/lib/hal/uart_debug.c b/sw/lib/hal/uart_debug.c index 25877734..a03acaeb 100644 --- a/sw/lib/hal/uart_debug.c +++ b/sw/lib/hal/uart_debug.c @@ -24,7 +24,7 @@ int uart_debug_init(void *uart_base, uint64_t core_freq) { CHECK_ASSERT(0x11, uart_base != 0); CHECK_ASSERT(0x12, core_freq != 0); // The UART debug mode uses the sane default 115.2kBaud - uart_init(uart_base, core_freq, 115200); + uart_init(uart_base, core_freq, __BAUDRATE); fence(); // Nothing went wrong return 0; diff --git a/sw/sw.mk b/sw/sw.mk index c4e0709d..3696bb42 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -116,7 +116,7 @@ $(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*. $(CHS_SW_OBJCOPY) -O binary $< $@ %.dtb: %.dts - $(CHS_SW_DTC) -I dts -O dtb -o $@ $< + $(CHS_SW_DTC) -I dts -O dtb -i $(CHS_SW_DIR)/boot -o $@ $< %.memh: %.elf $(CHS_SW_OBJCOPY) -O verilog $< $@ @@ -139,8 +139,13 @@ $(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*. # Images from CVA6 SDK (built externally) CHS_CVA6_SDK_IMGS ?= $(addprefix $(CHS_SW_DIR)/deps/cva6-sdk/install64/,fw_payload.bin uImage) -# Create full Linux disk image -$(CHS_SW_DIR)/boot/linux.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CHS_SW_DIR)/boot/cheshire.dtb $(CHS_CVA6_SDK_IMGS) +# linux-%.gpt.bin do not provide meaningfull error +$(CHS_CVA6_SDK_IMGS): + @echo "error: Missing CVA6 SDK images. Did you build your kernel?" + @exit 1 + +# Create full Linux disk image for a given board config +$(CHS_SW_DIR)/boot/linux-%.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CHS_SW_DIR)/boot/cheshire_%.dtb $(CHS_CVA6_SDK_IMGS) truncate -s $(CHS_SW_DISK_SIZE) $@ sgdisk --clear -g --set-alignment=1 \ --new=1:64:96 --typecode=1:$(CHS_SW_ZSL_TGUID) \ diff --git a/sw/tests/helloworld.c b/sw/tests/helloworld.c index df250626..12f39c3b 100644 --- a/sw/tests/helloworld.c +++ b/sw/tests/helloworld.c @@ -17,7 +17,7 @@ int main(void) { char str[] = "Hello World!\r\n"; uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET); uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500); - uart_init(&__base_uart, reset_freq, 115200); + uart_init(&__base_uart, reset_freq, __BAUDRATE); uart_write_str(&__base_uart, str, sizeof(str)); uart_write_flush(&__base_uart); return 0; diff --git a/target/xilinx/Makefile b/target/xilinx/Makefile deleted file mode 100644 index 2bc7d135..00000000 --- a/target/xilinx/Makefile +++ /dev/null @@ -1,71 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Nicole Narr -# Christopher Reinwardt - -PROJECT ?= cheshire -BOARD ?= genesys2 -XILINX_PART ?= xc7k325tffg900-2 -XILINX_BOARD ?= digilentinc.com:genesys2:part0:1.1 -XILINX_PORT ?= 3332 -XILINX_HOST ?= bordcomputer -FPGA_PATH ?= xilinx_tcf/Digilent/200300A8C60DB - -out := out -bit := $(out)/cheshire_top_xilinx.bit -mcs := $(out)/cheshire_top_xilinx.mcs -BIT ?= $(bit) - - -VIVADOENV ?= PROJECT=$(PROJECT) \ - BOARD=$(BOARD) \ - XILINX_PART=$(XILINX_PART) \ - XILINX_BOARD=$(XILINX_BOARD) \ - PORT=$(XILINX_PORT) \ - HOST=$(XILINX_HOST) \ - FPGA_PATH=$(FPGA_PATH) \ - BIT=$(BIT) - -# select IIS-internal tool commands if we run on IIS machines -ifneq (,$(wildcard /etc/iis.version)) - VIVADO ?= vitis-2022.1 vivado -else - VIVADO ?= vivado -endif - -VIVADOFLAGS ?= -nojournal -mode batch - -ip-dir := xilinx -ips := xlnx_mig_7_ddr3.xci - -all: $(mcs) - -# Generate mcs from bitstream -$(mcs): $(bit) - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^ - -$(bit): $(ips) - @mkdir -p $(out) - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/prologue.tcl -source scripts/run.tcl - cp $(PROJECT).runs/impl_1/$(PROJECT)* ./$(out) - -$(ips): - @echo "Generating IP $(basename $@)" - cd $(ip-dir)/$(basename $@) && $(MAKE) clean && $(VIVADOENV) VIVADO="$(VIVADO)" $(MAKE) - cp $(ip-dir)/$(basename $@)/$(basename $@).srcs/sources_1/ip/$(basename $@)/$@ $@ - -gui: - @echo "Starting $(vivado) GUI" - @$(VIVADOENV) $(VIVADO) -nojournal -mode gui $(PROJECT).xpr & - -program: - @echo "Programming board $(BOARD) ($(XILINX_PART))" - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl - -clean: - rm -rf *.log *.jou *.str *.mif *.xci *.xpr .Xil/ $(out) $(PROJECT).cache $(PROJECT).hw $(PROJECT).ioplanning $(PROJECT).ip_user_files $(PROJECT).runs $(PROJECT).sim - -.PHONY: - clean diff --git a/target/xilinx/constraints/cheshire.xdc b/target/xilinx/constraints/cheshire.xdc deleted file mode 100644 index 398a8166..00000000 --- a/target/xilinx/constraints/cheshire.xdc +++ /dev/null @@ -1,153 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Nicole Narr -# Christopher Reinwardt - -################### -# Global Settings # -################### - -# Testmode is set to 0 during normal use -set_case_analysis 0 [get_ports test_mode_i] - -# Preserve the output mux of the clock divider -set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux] - -# The pin of which we get the 200 MHz single ended clock from the MIG -set MIG_CLK_SRC {i_dram/ui_clk} - -##################### -# Timing Parameters # -##################### - -# 200 MHz FPGA diff clock -set FPGA_TCK 5.0 - -# 50 MHz SoC clock -set SOC_TCK 20.0 - -# 10 MHz JTAG clock -set JTAG_TCK 100.0 - -# I2C High-speed mode is 3.2 Mb/s -set I2C_IO_SPEED 312.5 - -# UART speed is at most 5 Mb/s -set UART_IO_SPEED 200.0 - -########## -# Clocks # -########## - -# System Clock -create_generated_clock -name clk_soc -source [get_pins $MIG_CLK_SRC] -divide_by 4 [get_pins i_sys_clk_div/i_clk_bypass_mux/i_BUFGMUX/O] - -# JTAG Clock -create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] -set_input_jitter clk_jtag 1.000 - -################ -# Clock Groups # -################ - -# JTAG Clock is asynchronous to all other clocks -set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag] - -####################### -# Placement Overrides # -####################### - -# Accept suboptimal BUFG-BUFG cascades -set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i] - -######## -# JTAG # -######## - -set_input_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] -set_input_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] - -set_output_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports jtag_tdo_o] -set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_tdo_o] - -set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK -set_false_path -hold -from [get_ports jtag_trst_ni] - -####### -# MIG # -####### - -set_max_delay -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] $FPGA_TCK -set_false_path -hold -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] - -######## -# SPIM # -######## - -set_input_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_input_delay -max -clock clk_soc [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_output_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] -set_output_delay -max -clock clk_soc [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] - -####### -# I2C # -####### - -set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] - -set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] - -######## -# UART # -######## - -set_max_delay [expr $UART_IO_SPEED * 0.35] -from [get_ports uart_rx_i] -set_false_path -hold -from [get_ports uart_rx_i] - -set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o] -set_false_path -hold -to [get_ports uart_tx_o] - -####### -# VGA # -####### - -set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports vga*] -set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports vga*] - -############ -# Switches # -############ - -set_input_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* test_mode_i}] -set_input_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* test_mode_i}] - -set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports fan_pwm] -set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports fan_pwm] - -set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* test_mode_i}] -set_false_path -hold -from [get_ports {boot_mode* fan_sw* test_mode_i}] - -set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm] -set_false_path -hold -to [get_ports fan_pwm] - -######## -# CDCs # -######## - -# cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew -set_property KEEP_HIERARCHY SOFT [get_cells i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync] -set_false_path -hold -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]] -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK - -################### -# Reset Generator # -################### - -set_max_delay -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] $SOC_TCK -set_false_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] diff --git a/target/xilinx/flavor_bd/constraints/ooc_cheshire_ip.xdc b/target/xilinx/flavor_bd/constraints/ooc_cheshire_ip.xdc new file mode 100644 index 00000000..3a2446e3 --- /dev/null +++ b/target/xilinx/flavor_bd/constraints/ooc_cheshire_ip.xdc @@ -0,0 +1,5 @@ +create_clock -name carfield_ooc_synth_clk_100 -period 100 [get_ports clk_100] +create_clock -name carfield_ooc_synth_clk_50 -period 50 [get_ports clk_50] +create_clock -name carfield_ooc_synth_clk_20 -period 20 [get_ports clk_20] +create_clock -name carfield_ooc_synth_clk_10 -period 10 [get_ports clk_10] +set_case_analysis 0 [get_ports testmode_i] diff --git a/target/xilinx/flavor_bd/constraints/vcu128.xdc b/target/xilinx/flavor_bd/constraints/vcu128.xdc new file mode 100644 index 00000000..737a40d2 --- /dev/null +++ b/target/xilinx/flavor_bd/constraints/vcu128.xdc @@ -0,0 +1,30 @@ +# VIOs are asynchronous +set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}] + +# Create system clocks +create_clock -period 10 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] +create_clock -period 10 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] +create_clock -period 10 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] + +# Pin related + +set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]] +set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]] + +set_property PACKAGE_PIN BP26 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property PACKAGE_PIN BN26 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 + +set_property PACKAGE_PIN BM29 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] + +set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_clk_n[0]] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_n[0]] +set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_clk_p[0]] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_p[0]] +set_property PACKAGE_PIN BH51 [get_ports sys_clk_clk_p[0]] +set_property PACKAGE_PIN BJ51 [get_ports sys_clk_clk_n[0]] diff --git a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc new file mode 100644 index 00000000..38bb4b50 --- /dev/null +++ b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc @@ -0,0 +1,17 @@ +set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND +set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; + +set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD +set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; + +set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] + +set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; + +set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; + +set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] diff --git a/target/xilinx/flavor_bd/flavor_bd.mk b/target/xilinx/flavor_bd/flavor_bd.mk new file mode 100644 index 00000000..7cd607ae --- /dev/null +++ b/target/xilinx/flavor_bd/flavor_bd.mk @@ -0,0 +1,50 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +# Output bitstream +xilinx_bit_bd = $(CHS_XIL_DIR)/flavor_bd/out/design_1_wrapper.bit + +# Vivado variables +vivado_env_bd := \ + XILINX_PROJECT=$(XILINX_PROJECT) \ + XILINX_BOARD=$(XILINX_BOARD) \ + XILINX_PART=$(xilinx_part) \ + XILINX_BOARD_LONG=$(xilinx_board_long) \ + XILINX_PORT=$(XILINX_PORT) \ + XILINX_HOST=$(XILINX_HOST) \ + XILINX_FPGA_PATH=$(XILINX_FPGA_PATH) \ + XILINX_BIT=$(xilinx_bit) \ + GEN_NO_HYPERBUS=$(GEN_NO_HYPERBUS) \ + GEN_EXT_JTAG=$(GEN_EXT_JTAG) \ + XILINX_ROUTED_DCP=$(XILINX_ROUTED_DCP) \ + XILINX_CHECK_TIMING=$(XILINX_CHECK_TIMING) \ + XILINX_ELABORATION_ONLY=$(XILINX_ELABORATION_ONLY) + +# Flavor specific bender args +xilinx_targs_bd := -t xilinx_bd + +# Add source files for ip +$(CHS_XIL_DIR)/flavor_bd/scripts/add_sources_cheshire_ip.tcl: Bender.yml + $(BENDER) script vivado $(xilinx_targs) $(xilinx_targs_bd) > $@ + +# Build Cheshire IP +$(CHS_XIL_DIR)/flavor_bd/cheshire_ip/cheshire_ip.xpr: $(CHS_XIL_DIR)/flavor_bd/scripts/add_sources_cheshire_ip.tcl + cd $(CHS_XIL_DIR)/flavor_bd && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run_cheshire_ip.tcl + +# Add includes files for block design +$(CHS_XIL_DIR)/flavor_bd/scripts/add_includes.tcl: + $(BENDER) script vivado --only-defines --only-includes $(xilinx_targs) $(xilinx_targs_bd) > $@ + +# Build block design bitstream +$(CHS_XIL_DIR)/flavor_bd/out/%.bit: $(CHS_XIL_DIR)/flavor_bd/scripts/add_includes.tcl $(CHS_XIL_DIR)/flavor_bd/cheshire_ip/cheshire_ip.xpr + mkdir -p $(CHS_XIL_DIR)/flavor_bd/out + cd $(CHS_XIL_DIR)/flavor_bd && $(vivado_env_bd) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl + find $(CHS_XIL_DIR)/flavor_bd -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CHS_XIL_DIR)/flavor_bd/out + +chs-xil-clean-bd: + cd $(CHS_XIL_DIR)/flavor_bd && rm -rf scripts/add_sources* scripts/add_includes* *.log *.jou *.str *.mif cheshire* .Xil/ + +.PHONY: chs-xil-clean-bd diff --git a/target/xilinx/flavor_bd/scripts/cheshire_bd_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/cheshire_bd_ext_jtag.tcl new file mode 100644 index 00000000..f2499c60 --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/cheshire_bd_ext_jtag.tcl @@ -0,0 +1,18 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set jtag_gnd_o [ create_bd_port -dir O jtag_gnd_o ] +set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ] +set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ] +set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ] +set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ] +set jtag_vdd_o [ create_bd_port -dir O jtag_vdd_o ] +connect_bd_net -net cheshire_xilinx_ip_0_jtag_gnd_o [get_bd_ports jtag_gnd_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_gnd_o] +connect_bd_net -net cheshire_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_tdo_o] +connect_bd_net -net cheshire_xilinx_ip_0_jtag_vdd_o [get_bd_ports jtag_vdd_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_vdd_o] +connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tck_i] +connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tdi_i] +connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tms_i] diff --git a/target/xilinx/flavor_bd/scripts/cheshire_bd_vcu128.tcl b/target/xilinx/flavor_bd/scripts/cheshire_bd_vcu128.tcl new file mode 100644 index 00000000..362c2f3f --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/cheshire_bd_vcu128.tcl @@ -0,0 +1,526 @@ + +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2020.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xcvu37p-fsvh2892-2L-e + set_property BOARD_PART xilinx.com:vcu128:part0:1.0 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_dma:7.1\ +xilinx.com:ip:axi_ethernet:7.2\ +ethz.ch:user:cheshire_xilinx_ip:1.0\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:xlconstant:1.1\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:util_ds_buf:2.1\ +xilinx.com:ip:util_vector_logic:2.0\ +xilinx.com:ip:vio:3.0\ +xilinx.com:ip:xdma:4.1\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram ] + + set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ] + + set pci_express_x4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x4 ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $pcie_refclk + + set sgmii_lvds [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii_lvds ] + + set sgmii_phyclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sgmii_phyclk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {625000000} \ + ] $sgmii_phyclk + + set sys_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $sys_clk + + + # Create ports + set dummy_port_in [ create_bd_port -dir I -type rst dummy_port_in ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $dummy_port_in + set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $pcie_perstn + set reset [ create_bd_port -dir I -type rst reset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $reset + set uart_rx_i [ create_bd_port -dir I uart_rx_i ] + set uart_tx_o [ create_bd_port -dir O uart_tx_o ] + + # Create instance: axi_dma_0, and set properties + set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] + set_property -dict [ list \ + CONFIG.c_addr_width {64} \ + CONFIG.c_include_mm2s_dre {1} \ + CONFIG.c_include_s2mm_dre {1} \ + CONFIG.c_sg_length_width {16} \ + CONFIG.c_sg_use_stsapp_length {1} \ + ] $axi_dma_0 + + # Create instance: axi_ethernet_0, and set properties + set axi_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.2 axi_ethernet_0 ] + set_property -dict [ list \ + CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk} \ + CONFIG.ENABLE_LVDS {true} \ + CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds} \ + CONFIG.InstantiateBitslice0 {true} \ + CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} \ + CONFIG.PHYADDR {0} \ + CONFIG.PHYRST_BOARD_INTERFACE {Custom} \ + CONFIG.PHYRST_BOARD_INTERFACE_DUMMY_PORT {dummy_port_in} \ + CONFIG.PHY_TYPE {SGMII} \ + CONFIG.RXCSUM {Full} \ + CONFIG.TXCSUM {Full} \ + CONFIG.lvdsclkrate {625} \ + CONFIG.rxlane0_placement {DIFF_PAIR_2} \ + CONFIG.rxnibblebitslice0used {false} \ + CONFIG.txlane0_placement {DIFF_PAIR_1} \ + ] $axi_ethernet_0 + + # Create instance: cheshire_xilinx_ip_0, and set properties + set cheshire_xilinx_ip_0 [ create_bd_cell -type ip -vlnv ethz.ch:user:cheshire_xilinx_ip:1.0 cheshire_xilinx_ip_0 ] + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.CLKOUT1_JITTER {188.586} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKOUT1_USED {true} \ + CONFIG.CLKOUT2_JITTER {162.167} \ + CONFIG.CLKOUT2_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_JITTER {132.683} \ + CONFIG.CLKOUT3_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_JITTER {115.831} \ + CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.CLK_OUT1_PORT {clk_10} \ + CONFIG.CLK_OUT2_PORT {clk_20} \ + CONFIG.CLK_OUT3_PORT {clk_50} \ + CONFIG.CLK_OUT4_PORT {clk_100} \ + CONFIG.ENABLE_CLOCK_MONITOR {false} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {120.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {12} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.PRIMITIVE {MMCM} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.USE_BOARD_FLOW {true} \ + CONFIG.USE_LOCKED {true} \ + CONFIG.USE_RESET {false} \ + ] $clk_wiz_0 + + # Create instance: concat_irq, and set properties + set concat_irq [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_irq ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {12} \ + ] $concat_irq + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {None} \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {Custom} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ + CONFIG.System_Clock {No_Buffer} \ + ] $ddr4_0 + + # Create instance: low, and set properties + set low [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 low ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $low + + # Create instance: psr_10, and set properties + set psr_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_10 ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {1} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $psr_10 + + # Create instance: psr_333, and set properties + set psr_333 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_333 ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {1} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + ] $psr_333 + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {2} \ + ] $smartconnect_0 + + # Create instance: util_ds_buf_0, and set properties + set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDS} \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf_0 + + # Create instance: util_ds_buf_1, and set properties + set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1 ] + set_property -dict [ list \ + CONFIG.C_BUF_TYPE {IBUFDSGTE} \ + CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $util_ds_buf_1 + + # Create instance: util_vector_logic_0, and set properties + set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ] + set_property -dict [ list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + CONFIG.LOGO_FILE {data/sym_orgate.png} \ + ] $util_vector_logic_0 + + # Create instance: vio_0, and set properties + set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ] + set_property -dict [ list \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT0_WIDTH {2} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + ] $vio_0 + + # Create instance: xbar_dram, and set properties + set xbar_dram [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_dram ] + set_property -dict [ list \ + CONFIG.HAS_ARESETN {1} \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $xbar_dram + + # Create instance: xbar_periph_in, and set properties + set xbar_periph_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_periph_in ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {1} \ + CONFIG.NUM_SI {4} \ + ] $xbar_periph_in + + # Create instance: xbar_periph_out, and set properties + set xbar_periph_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_periph_out ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {3} \ + CONFIG.NUM_MI {3} \ + CONFIG.NUM_SI {1} \ + ] $xbar_periph_out + + # Create instance: xdma_0, and set properties + set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] + set_property -dict [ list \ + CONFIG.PCIE_BOARD_INTERFACE {pci_express_x4} \ + CONFIG.PF0_DEVICE_ID_mqdma {9014} \ + CONFIG.PF2_DEVICE_ID_mqdma {9014} \ + CONFIG.PF3_DEVICE_ID_mqdma {9014} \ + CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ + CONFIG.axi_addr_width {64} \ + CONFIG.axi_bypass_64bit_en {true} \ + CONFIG.axi_bypass_prefetchable {true} \ + CONFIG.axist_bypass_en {true} \ + CONFIG.axist_bypass_scale {Gigabytes} \ + CONFIG.axist_bypass_size {4} \ + CONFIG.axisten_freq {125} \ + CONFIG.functional_mode {DMA} \ + CONFIG.pf0_device_id {9014} \ + CONFIG.pl_link_cap_max_link_width {X4} \ + CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ + CONFIG.xdma_axilite_slave {false} \ + ] $xdma_0 + + # Create interface connections + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_CNTRL [get_bd_intf_pins axi_dma_0/M_AXIS_CNTRL] [get_bd_intf_pins axi_ethernet_0/s_axis_txc] + connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axi_ethernet_0/s_axis_txd] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins xbar_periph_in/S01_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins xbar_periph_in/S02_AXI] + connect_bd_intf_net -intf_net axi_dma_0_M_AXI_SG [get_bd_intf_pins axi_dma_0/M_AXI_SG] [get_bd_intf_pins xbar_periph_in/S00_AXI] + connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxd [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins axi_ethernet_0/m_axis_rxd] + connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxs [get_bd_intf_pins axi_dma_0/S_AXIS_STS] [get_bd_intf_pins axi_ethernet_0/m_axis_rxs] + connect_bd_intf_net -intf_net axi_ethernet_0_mdio [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernet_0/mdio] + connect_bd_intf_net -intf_net axi_ethernet_0_sgmii [get_bd_intf_ports sgmii_lvds] [get_bd_intf_pins axi_ethernet_0/sgmii] + connect_bd_intf_net -intf_net cheshire_xilinx_ip_0_dram_axi [get_bd_intf_pins cheshire_xilinx_ip_0/dram_axi] [get_bd_intf_pins xbar_dram/S00_AXI] + connect_bd_intf_net -intf_net cheshire_xilinx_ip_0_periph_axi_m [get_bd_intf_pins cheshire_xilinx_ip_0/periph_axi_m] [get_bd_intf_pins xbar_periph_out/S00_AXI] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net diff_clock_rtl_1 [get_bd_intf_ports sys_clk] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D] + connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf_1/CLK_IN_D] + connect_bd_intf_net -intf_net sgmii_phyclk_1 [get_bd_intf_ports sgmii_phyclk] [get_bd_intf_pins axi_ethernet_0/lvds_clk] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins xbar_dram/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI1 [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins xbar_periph_in/S03_AXI] + connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins axi_ethernet_0/s_axi] [get_bd_intf_pins xbar_periph_out/M00_AXI] + connect_bd_intf_net -intf_net xbar_periph_in_M00_AXI [get_bd_intf_pins cheshire_xilinx_ip_0/periph_axi_s] [get_bd_intf_pins xbar_periph_in/M00_AXI] + connect_bd_intf_net -intf_net xbar_periph_out_M01_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins xbar_periph_out/M01_AXI] + connect_bd_intf_net -intf_net xbar_periph_out_M02_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] [get_bd_intf_pins xbar_periph_out/M02_AXI] + connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins xdma_0/M_AXI] + connect_bd_intf_net -intf_net xdma_0_M_AXI_BYPASS [get_bd_intf_pins smartconnect_0/S01_AXI] [get_bd_intf_pins xdma_0/M_AXI_BYPASS] + connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x4] [get_bd_intf_pins xdma_0/pcie_mgt] + + # Create port connections + connect_bd_net -net axi_dma_0_mm2s_cntrl_reset_out_n [get_bd_pins axi_dma_0/mm2s_cntrl_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txc_arstn] + connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins concat_irq/In2] + connect_bd_net -net axi_dma_0_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_0/mm2s_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txd_arstn] + connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins concat_irq/In3] + connect_bd_net -net axi_dma_0_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_0/s2mm_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_rxd_arstn] + connect_bd_net -net axi_dma_0_s2mm_sts_reset_out_n [get_bd_pins axi_dma_0/s2mm_sts_reset_out_n] [get_bd_pins axi_ethernet_0/axi_rxs_arstn] + connect_bd_net -net axi_ethernet_0_interrupt [get_bd_pins axi_ethernet_0/interrupt] [get_bd_pins concat_irq/In0] + connect_bd_net -net axi_ethernet_0_mac_irq [get_bd_pins axi_ethernet_0/mac_irq] [get_bd_pins concat_irq/In5] + connect_bd_net -net cheshire_xilinx_ip_0_dram_axi_m_aclk [get_bd_pins cheshire_xilinx_ip_0/dram_axi_m_aclk] [get_bd_pins xbar_dram/aclk] + connect_bd_net -net cheshire_xilinx_ip_0_periph_axi_m_aclk [get_bd_pins cheshire_xilinx_ip_0/periph_axi_m_aclk] [get_bd_pins xbar_periph_out/aclk] + connect_bd_net -net cheshire_xilinx_ip_0_uart_tx_o [get_bd_ports uart_tx_o] [get_bd_pins cheshire_xilinx_ip_0/uart_tx_o] + connect_bd_net -net clk_wiz_0_clk_10 [get_bd_pins cheshire_xilinx_ip_0/clk_10] [get_bd_pins clk_wiz_0/clk_10] [get_bd_pins psr_10/slowest_sync_clk] + connect_bd_net -net clk_wiz_0_clk_20 [get_bd_pins cheshire_xilinx_ip_0/clk_20] [get_bd_pins clk_wiz_0/clk_20] + connect_bd_net -net clk_wiz_0_clk_50 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_ethernet_0/axis_clk] [get_bd_pins axi_ethernet_0/s_axi_lite_clk] [get_bd_pins cheshire_xilinx_ip_0/clk_50] [get_bd_pins clk_wiz_0/clk_50] [get_bd_pins smartconnect_0/aclk1] [get_bd_pins vio_0/clk] [get_bd_pins xbar_periph_in/aclk] [get_bd_pins xbar_periph_out/aclk1] + connect_bd_net -net clk_wiz_0_clk_100 [get_bd_pins cheshire_xilinx_ip_0/clk_100] [get_bd_pins clk_wiz_0/clk_100] + connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins psr_10/dcm_locked] + connect_bd_net -net concat_irq_dout [get_bd_pins cheshire_xilinx_ip_0/gpio_i] [get_bd_pins concat_irq/dout] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins psr_333/slowest_sync_clk] [get_bd_pins xbar_dram/aclk1] [get_bd_pins xbar_periph_out/aclk2] + connect_bd_net -net dummy_port_in_1 [get_bd_ports dummy_port_in] [get_bd_pins axi_ethernet_0/dummy_port_in] + connect_bd_net -net low_dout [get_bd_pins cheshire_xilinx_ip_0/testmode_i] [get_bd_pins low/dout] + connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] + connect_bd_net -net psr_10_interconnect_aresetn [get_bd_pins psr_10/interconnect_aresetn] [get_bd_pins xbar_dram/aresetn] [get_bd_pins xbar_periph_in/aresetn] [get_bd_pins xbar_periph_out/aresetn] + connect_bd_net -net psr_10_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_ethernet_0/s_axi_lite_resetn] [get_bd_pins psr_10/peripheral_aresetn] + connect_bd_net -net psr_333_peripheral_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins psr_333/peripheral_aresetn] + connect_bd_net -net psr_333_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins psr_333/peripheral_reset] + connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins psr_10/ext_reset_in] [get_bd_pins psr_333/ext_reset_in] [get_bd_pins util_vector_logic_0/Op1] + connect_bd_net -net uart_rx_i_1 [get_bd_ports uart_rx_i] [get_bd_pins cheshire_xilinx_ip_0/uart_rx_i] + connect_bd_net -net util_ds_buf_0_IBUF_OUT [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_sys_clk_i] [get_bd_pins util_ds_buf_0/IBUF_OUT] + connect_bd_net -net util_ds_buf_1_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf_1/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] + connect_bd_net -net util_ds_buf_1_IBUF_OUT [get_bd_pins util_ds_buf_1/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] + connect_bd_net -net util_vector_logic_0_Res [get_bd_pins cheshire_xilinx_ip_0/cpu_reset] [get_bd_pins util_vector_logic_0/Res] + connect_bd_net -net vio_0_probe_out0 [get_bd_pins cheshire_xilinx_ip_0/boot_mode_i] [get_bd_pins vio_0/probe_out0] + connect_bd_net -net vio_0_probe_out2 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out2] + connect_bd_net -net xdma_0_axi_aclk [get_bd_pins smartconnect_0/aclk] [get_bd_pins xdma_0/axi_aclk] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force + assign_bd_address -offset 0x41E00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cheshire_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x40C00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces cheshire_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_ethernet_0/s_axi/Reg0] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces cheshire_xilinx_ip_0/dram_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_BYPASS] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force + + # Exclude Address Segments + exclude_bd_addr_seg -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces cheshire_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/target/xilinx/flavor_bd/scripts/run.tcl b/target/xilinx/flavor_bd/scripts/run.tcl new file mode 100644 index 00000000..16037468 --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/run.tcl @@ -0,0 +1,131 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +# Create project +set project $::env(XILINX_PROJECT) + +create_project $project ./$project -force -part $::env(XILINX_PART) +set_property board_part $::env(XILINX_BOARD_LONG) [current_project] +set_property XPM_LIBRARIES XPM_MEMORY [current_project] + +# set number of threads to 8 (maximum, unfortunately) +set_param general.maxThreads 8 + +# Define sources +set_property ip_repo_paths ./cheshire_ip [current_project] +update_ip_catalog + +import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc + +source scripts/cheshire_bd_$::env(XILINX_BOARD).tcl + +source scripts/add_includes.tcl + +# Add the ext_jtag pins to block design +if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} { + source scripts/cheshire_bd_ext_jtag.tcl + import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_ext_jtag.xdc +} + +make_wrapper -files [get_files $project/$project.srcs/sources_1/bd/design_1/design_1.bd] -top +add_files -norecurse $project/$project.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v + +# Create OOC runs +generate_target all [get_files *design_1.bd] +export_ip_user_files -of_objects [get_files *design_1.bd] -no_script +create_ip_run [get_files *design_1.bd] + +# Start OOC synthesis of changed IPs +set synth_runs [get_runs *synth*] +# Exclude the whole design (synth_1) and the cheshire IP (bug) +set all_ooc_synth [lsearch -regexp -all -inline -not $synth_runs {^synth_1$|cheshire}] +set runs_queued {} +foreach run $all_ooc_synth { + if {[get_property PROGRESS [get_run $run]] != "100%"} { + puts "Launching run $run" + lappend runs_queued $run + # Default synthesis strategy + set_property strategy Flow_RuntimeOptimized [get_runs $run] + } else { + puts "Skipping 100% complete run: $run" + } +} +if {[llength $runs_queued] != 0} { + reset_run $runs_queued + launch_runs $runs_queued -jobs 16 + puts "Waiting on $runs_queued" + foreach run $runs_queued { + wait_on_run $run + } + # reset main synthesis + reset_run synth_1 +} + +set_property strategy Flow_RuntimeOptimized [get_runs synth_1] +set_property strategy Flow_RuntimeOptimized [get_runs impl_1] + +set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] +# Enable sfcu due to package conflicts +set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-sfcu} -objects [get_runs synth_1] + +launch_runs synth_1 +wait_on_run synth_1 +open_run synth_1 -name synth_1 + +# Instantiate ILA +set DEBUG [llength [get_nets -hier -filter {MARK_DEBUG == 1}]] +if ($DEBUG) { + # Create core + puts "Creating debug core..." + create_debug_core u_ila_0 ila + set_property -dict "ALL_PROBE_SAME_MU true ALL_PROBE_SAME_MU_CNT 4 C_ADV_TRIGGER true C_DATA_DEPTH 16384 \ + C_EN_STRG_QUAL true C_INPUT_PIPE_STAGES 0 C_TRIGIN_EN false C_TRIGOUT_EN false" [get_debug_cores u_ila_0] + ## Clock + set_property port_width 1 [get_debug_ports u_ila_0/clk] + connect_debug_port u_ila_0/clk [get_nets design_1_i/clk_wiz_0_clk_50] + # Get nets to debug + set debugNets [lsort -dictionary [get_nets -hier -filter {MARK_DEBUG == 1}]] + set netNameLast "" + set probe_i 0 + # Loop through all nets (add extra list element to ensure last net is processed) + foreach net [concat $debugNets {""}] { + # Remove trailing array index + regsub {\[[0-9]*\]$} $net {} netName + # Create probe after all signals with the same name have been collected + if {$netNameLast != $netName} { + if {$netNameLast != ""} { + puts "Creating probe $probe_i with width [llength $sigList] for signal '$netNameLast'" + # probe0 already exists, and does not need to be created + if {$probe_i != 0} { + create_debug_port u_ila_0 probe + } + set_property port_width [llength $sigList] [get_debug_ports u_ila_0/probe$probe_i] + set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe$probe_i] + connect_debug_port u_ila_0/probe$probe_i [get_nets $sigList] + incr probe_i + } + set sigList "" + } + lappend sigList $net + set netNameLast $netName + } + # Need to save save constraints before implementing the core + set_property target_constrs_file [get_files $::env(XILINX_BOARD).xdc] [current_fileset -constrset] + save_constraints -force + implement_debug_core + write_debug_probes -force probes.ltx +} + +# Incremental implementation +if {[info exists ::env(ROUTED_DCP)] && [file exists $::env(ROUTED_DCP)]} { + set_property incremental_checkpoint $::env(ROUTED_DCP) [get_runs impl_1] +} + +# Implementation +launch_runs impl_1 +wait_on_run impl_1 +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 diff --git a/target/xilinx/flavor_bd/scripts/run_cheshire_ip.tcl b/target/xilinx/flavor_bd/scripts/run_cheshire_ip.tcl new file mode 100644 index 00000000..b71329f1 --- /dev/null +++ b/target/xilinx/flavor_bd/scripts/run_cheshire_ip.tcl @@ -0,0 +1,32 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +# Create project +set project cheshire_ip + +create_project $project ./$project -force -part $::env(XILINX_PART) +set_property XPM_LIBRARIES XPM_MEMORY [current_project] + +# set number of threads to 8 (maximum, unfortunately) +set_param general.maxThreads 8 + +# Define sources +source scripts/add_sources_cheshire_ip.tcl + +# Add constraints +add_files -fileset constrs_1 constraints/ooc_cheshire_ip.xdc +set_property USED_IN {synthesis out_of_context} [get_files constraints/ooc_cheshire_ip.xdc] +add_files -fileset constrs_1 ../flavor_vanilla/constraints/cheshire.xdc + +# Package IP +set_property top cheshire_xilinx_ip [current_fileset] + +update_compile_order -fileset sources_1 +synth_design -rtl -name rtl_1 + +ipx::package_project -root_dir ./${project} -vendor ethz.ch -library user -taxonomy /UserIP -set_current true + +exit diff --git a/target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v b/target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v new file mode 100644 index 00000000..79bc1bca --- /dev/null +++ b/target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v @@ -0,0 +1,441 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig +// Just a verilog wrapper to accomodate Vivado + +module cheshire_xilinx_ip +( +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH" *) + input wire cpu_reset , +(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_10" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 10000000" *) + input wire clk_10 , +(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_20" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 20000000" *) + input wire clk_20 , +(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_50" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000, ASSOCIATED_BUSIF periph_axi_s" *) + input wire clk_50 , +(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_100" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000" *) + input wire clk_100 , + + input wire testmode_i , + input wire [1:0] boot_mode_i , + + input wire [31:0] gpio_i, + + input wire jtag_tck_i , + input wire jtag_tms_i , + input wire jtag_tdi_i , + output wire jtag_tdo_o , + input wire jtag_trst_ni , + output wire jtag_vdd_o , + output wire jtag_gnd_o , + + output wire uart_tx_o , + input wire uart_rx_i , + + // MASTER AXI DRAM + +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) + output wire [47:0] dram_axi_m_axi_araddr, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARBURST" *) + output wire [1:0] dram_axi_m_axi_arburst, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARCACHE" *) + output wire [3:0] dram_axi_m_axi_arcache, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARID" *) + output wire [6:0]dram_axi_m_axi_arid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARLEN" *) + output wire [7:0] dram_axi_m_axi_arlen, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARLOCK" *) + output wire dram_axi_m_axi_arlock, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARPROT" *) + output wire [2:0] dram_axi_m_axi_arprot, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARQOS" *) + output wire [3:0] dram_axi_m_axi_arqos, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARREADY" *) + input wire dram_axi_m_axi_arready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARSIZE" *) + output wire [2:0] dram_axi_m_axi_arsize, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARVALID" *) + output wire dram_axi_m_axi_arvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWADDR" *) + output wire [47:0] dram_axi_m_axi_awaddr, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWBURST" *) + output wire [1:0] dram_axi_m_axi_awburst, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWCACHE" *) + output wire [3:0] dram_axi_m_axi_awcache, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWID" *) + output wire [6:0] dram_axi_m_axi_awid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWLEN" *) + output wire [7:0] dram_axi_m_axi_awlen, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWLOCK" *) + output wire dram_axi_m_axi_awlock, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWPROT" *) + output wire [2:0] dram_axi_m_axi_awprot, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWQOS" *) + output wire [3:0] dram_axi_m_axi_awqos, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWREADY" *) + input wire dram_axi_m_axi_awready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWSIZE" *) + output wire [2:0] dram_axi_m_axi_awsize, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWVALID" *) + output wire dram_axi_m_axi_awvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi BID" *) + input wire [6:0] dram_axi_m_axi_bid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi BREADY" *) + output wire dram_axi_m_axi_bready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi BRESP" *) + input wire [1:0] dram_axi_m_axi_bresp, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi BVALID" *) + input wire dram_axi_m_axi_bvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RDATA" *) + input wire [63:0] dram_axi_m_axi_rdata, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RID" *) + input wire [6:0] dram_axi_m_axi_rid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RLAST" *) + input wire dram_axi_m_axi_rlast, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RREADY" *) + output wire dram_axi_m_axi_rready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RRESP" *) + input wire [1:0] dram_axi_m_axi_rresp, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RVALID" *) + input wire dram_axi_m_axi_rvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WDATA" *) + output wire [63:0] dram_axi_m_axi_wdata, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WLAST" *) + output wire dram_axi_m_axi_wlast, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WREADY" *) + input wire dram_axi_m_axi_wready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WSTRB" *) + output wire [7:0] dram_axi_m_axi_wstrb, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WVALID" *) + output wire dram_axi_m_axi_wvalid, +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 dram_axi CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME dram_axi, ASSOCIATED_BUSIF dram_axi, FREQ_HZ 50000000" *) + output wire dram_axi_m_aclk, +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) + output wire dram_axi_m_aresetn, + +// MASTER AXI PERIPHERAL + +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) + output wire [47:0] periph_axi_m_axi_araddr, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARBURST" *) + output wire [1:0] periph_axi_m_axi_arburst, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARCACHE" *) + output wire [3:0] periph_axi_m_axi_arcache, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARID" *) + output wire [1:0]periph_axi_m_axi_arid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARLEN" *) + output wire [7:0] periph_axi_m_axi_arlen, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARLOCK" *) + output wire periph_axi_m_axi_arlock, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARPROT" *) + output wire [2:0] periph_axi_m_axi_arprot, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARQOS" *) + output wire [3:0] periph_axi_m_axi_arqos, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARREADY" *) + input wire periph_axi_m_axi_arready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARSIZE" *) + output wire [2:0] periph_axi_m_axi_arsize, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARVALID" *) + output wire periph_axi_m_axi_arvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWADDR" *) + output wire [47:0] periph_axi_m_axi_awaddr, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWBURST" *) + output wire [1:0] periph_axi_m_axi_awburst, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWCACHE" *) + output wire [3:0] periph_axi_m_axi_awcache, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWID" *) + output wire [1:0] periph_axi_m_axi_awid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWLEN" *) + output wire [7:0] periph_axi_m_axi_awlen, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWLOCK" *) + output wire periph_axi_m_axi_awlock, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWPROT" *) + output wire [2:0] periph_axi_m_axi_awprot, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWQOS" *) + output wire [3:0] periph_axi_m_axi_awqos, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWREADY" *) + input wire periph_axi_m_axi_awready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWSIZE" *) + output wire [2:0] periph_axi_m_axi_awsize, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWVALID" *) + output wire periph_axi_m_axi_awvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m BID" *) + input wire [1:0] periph_axi_m_axi_bid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m BREADY" *) + output wire periph_axi_m_axi_bready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m BRESP" *) + input wire [1:0] periph_axi_m_axi_bresp, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m BVALID" *) + input wire periph_axi_m_axi_bvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RDATA" *) + input wire [63:0] periph_axi_m_axi_rdata, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RID" *) + input wire [1:0] periph_axi_m_axi_rid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RLAST" *) + input wire periph_axi_m_axi_rlast, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RREADY" *) + output wire periph_axi_m_axi_rready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RRESP" *) + input wire [1:0] periph_axi_m_axi_rresp, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RVALID" *) + input wire periph_axi_m_axi_rvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WDATA" *) + output wire [63:0] periph_axi_m_axi_wdata, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WLAST" *) + output wire periph_axi_m_axi_wlast, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WREADY" *) + input wire periph_axi_m_axi_wready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WSTRB" *) + output wire [7:0] periph_axi_m_axi_wstrb, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WVALID" *) + output wire periph_axi_m_axi_wvalid, +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 periph_axi_m CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME periph_axi_m, ASSOCIATED_BUSIF periph_axi_m, FREQ_HZ 500000000" *) + output wire periph_axi_m_aclk, +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 periph_axi_m RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME periph_axi_m, POLARITY ACTIVE_LOW" *) + output wire periph_axi_m_aresetn, + +// SLAVE AXI PERIPHERAL + +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) + input wire [47:0] periph_axi_s_axi_araddr, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARBURST" *) + input wire [1:0] periph_axi_s_axi_arburst, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARCACHE" *) + input wire [3:0] periph_axi_s_axi_arcache, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARID" *) + input wire [1:0]periph_axi_s_axi_arid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARLEN" *) + input wire [7:0] periph_axi_s_axi_arlen, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARLOCK" *) + input wire periph_axi_s_axi_arlock, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARPROT" *) + input wire [2:0] periph_axi_s_axi_arprot, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARQOS" *) + input wire [3:0] periph_axi_s_axi_arqos, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARREADY" *) + output wire periph_axi_s_axi_arready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARSIZE" *) + input wire [2:0] periph_axi_s_axi_arsize, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARVALID" *) + input wire periph_axi_s_axi_arvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWADDR" *) + input wire [47:0] periph_axi_s_axi_awaddr, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWBURST" *) + input wire [1:0] periph_axi_s_axi_awburst, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWCACHE" *) + input wire [3:0] periph_axi_s_axi_awcache, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWID" *) + input wire [1:0] periph_axi_s_axi_awid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWLEN" *) + input wire [7:0] periph_axi_s_axi_awlen, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWLOCK" *) + input wire periph_axi_s_axi_awlock, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWPROT" *) + input wire [2:0] periph_axi_s_axi_awprot, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWQOS" *) + input wire [3:0] periph_axi_s_axi_awqos, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWREADY" *) + output wire periph_axi_s_axi_awready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWSIZE" *) + input wire [2:0] periph_axi_s_axi_awsize, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWVALID" *) + input wire periph_axi_s_axi_awvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s BID" *) + output wire [1:0] periph_axi_s_axi_bid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s BREADY" *) + input wire periph_axi_s_axi_bready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s BRESP" *) + output wire [1:0] periph_axi_s_axi_bresp, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s BVALID" *) + output wire periph_axi_s_axi_bvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RDATA" *) + output wire [63:0] periph_axi_s_axi_rdata, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RID" *) + output wire [1:0] periph_axi_s_axi_rid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RLAST" *) + output wire periph_axi_s_axi_rlast, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RREADY" *) + input wire periph_axi_s_axi_rready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RRESP" *) + output wire [1:0] periph_axi_s_axi_rresp, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RVALID" *) + output wire periph_axi_s_axi_rvalid, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WDATA" *) + input wire [63:0] periph_axi_s_axi_wdata, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WLAST" *) + input wire periph_axi_s_axi_wlast, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WREADY" *) + output wire periph_axi_s_axi_wready, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WSTRB" *) + input wire [7:0] periph_axi_s_axi_wstrb, +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WVALID" *) + input wire periph_axi_s_axi_wvalid + +); + + cheshire_top_xilinx #( + ) i_cheshire_top_xilinx ( + .cpu_reset(cpu_reset), + .clk_10(clk_10), + .clk_20(clk_20), + .clk_50(clk_50), + .clk_100(clk_100), + + .testmode_i (testmode_i ) , + .boot_mode_i (boot_mode_i ) , + + .gpio_i (gpio_i), + + .jtag_tck_i (jtag_tck_i ), + .jtag_tms_i (jtag_tms_i ), + .jtag_tdi_i (jtag_tdi_i ), + .jtag_tdo_o (jtag_tdo_o ), + .jtag_trst_ni(jtag_trst_ni ), + .jtag_vdd_o (jtag_vdd_o ), + .jtag_gnd_o (jtag_gnd_o ), + + .uart_tx_o(uart_tx_o), + .uart_rx_i(uart_rx_i), + + .dram_axi_m_aclk (dram_axi_m_aclk ), + .dram_axi_m_aresetn(dram_axi_m_aresetn), + + // Dram axi + + .dram_axi_m_axi_awid (dram_axi_m_axi_awid ), + .dram_axi_m_axi_awaddr (dram_axi_m_axi_awaddr ), + .dram_axi_m_axi_awlen (dram_axi_m_axi_awlen ), + .dram_axi_m_axi_awsize (dram_axi_m_axi_awsize ), + .dram_axi_m_axi_awburst(dram_axi_m_axi_awburst), + .dram_axi_m_axi_awlock (dram_axi_m_axi_awlock ), + .dram_axi_m_axi_awcache(dram_axi_m_axi_awcache), + .dram_axi_m_axi_awprot (dram_axi_m_axi_awprot ), + .dram_axi_m_axi_awqos (dram_axi_m_axi_awqos ), + .dram_axi_m_axi_awvalid(dram_axi_m_axi_awvalid), + .dram_axi_m_axi_awready(dram_axi_m_axi_awready), + + .dram_axi_m_axi_wdata (dram_axi_m_axi_wdata ), + .dram_axi_m_axi_wstrb (dram_axi_m_axi_wstrb ), + .dram_axi_m_axi_wlast (dram_axi_m_axi_wlast ), + .dram_axi_m_axi_wvalid(dram_axi_m_axi_wvalid), + .dram_axi_m_axi_wready(dram_axi_m_axi_wready), + + .dram_axi_m_axi_bready(dram_axi_m_axi_bready), + .dram_axi_m_axi_bid (dram_axi_m_axi_bid ), + .dram_axi_m_axi_bresp (dram_axi_m_axi_bresp ), + .dram_axi_m_axi_bvalid(dram_axi_m_axi_bvalid), + + .dram_axi_m_axi_arid (dram_axi_m_axi_arid ), + .dram_axi_m_axi_araddr (dram_axi_m_axi_araddr ), + .dram_axi_m_axi_arlen (dram_axi_m_axi_arlen ), + .dram_axi_m_axi_arsize (dram_axi_m_axi_arsize ), + .dram_axi_m_axi_arburst(dram_axi_m_axi_arburst), + .dram_axi_m_axi_arlock (dram_axi_m_axi_arlock ), + .dram_axi_m_axi_arcache(dram_axi_m_axi_arcache), + .dram_axi_m_axi_arprot (dram_axi_m_axi_arprot ), + .dram_axi_m_axi_arqos (dram_axi_m_axi_arqos ), + .dram_axi_m_axi_arvalid(dram_axi_m_axi_arvalid), + .dram_axi_m_axi_arready(dram_axi_m_axi_arready), + + .dram_axi_m_axi_rready(dram_axi_m_axi_rready), + .dram_axi_m_axi_rid (dram_axi_m_axi_rid ), + .dram_axi_m_axi_rdata (dram_axi_m_axi_rdata ), + .dram_axi_m_axi_rresp (dram_axi_m_axi_rresp ), + .dram_axi_m_axi_rlast (dram_axi_m_axi_rlast ), + .dram_axi_m_axi_rvalid(dram_axi_m_axi_rvalid), + + // Peripheral axi + + .periph_axi_m_aclk (periph_axi_m_aclk ), + .periph_axi_m_aresetn(periph_axi_m_aresetn), + + .periph_axi_m_axi_awid (periph_axi_m_axi_awid ), + .periph_axi_m_axi_awaddr (periph_axi_m_axi_awaddr ), + .periph_axi_m_axi_awlen (periph_axi_m_axi_awlen ), + .periph_axi_m_axi_awsize (periph_axi_m_axi_awsize ), + .periph_axi_m_axi_awburst(periph_axi_m_axi_awburst), + .periph_axi_m_axi_awlock (periph_axi_m_axi_awlock ), + .periph_axi_m_axi_awcache(periph_axi_m_axi_awcache), + .periph_axi_m_axi_awprot (periph_axi_m_axi_awprot ), + .periph_axi_m_axi_awqos (periph_axi_m_axi_awqos ), + .periph_axi_m_axi_awvalid(periph_axi_m_axi_awvalid), + .periph_axi_m_axi_awready(periph_axi_m_axi_awready), + + .periph_axi_m_axi_wdata (periph_axi_m_axi_wdata ), + .periph_axi_m_axi_wstrb (periph_axi_m_axi_wstrb ), + .periph_axi_m_axi_wlast (periph_axi_m_axi_wlast ), + .periph_axi_m_axi_wvalid(periph_axi_m_axi_wvalid), + .periph_axi_m_axi_wready(periph_axi_m_axi_wready), + + .periph_axi_m_axi_bready(periph_axi_m_axi_bready), + .periph_axi_m_axi_bid (periph_axi_m_axi_bid ), + .periph_axi_m_axi_bresp (periph_axi_m_axi_bresp ), + .periph_axi_m_axi_bvalid(periph_axi_m_axi_bvalid), + + .periph_axi_m_axi_arid (periph_axi_m_axi_arid ), + .periph_axi_m_axi_araddr (periph_axi_m_axi_araddr ), + .periph_axi_m_axi_arlen (periph_axi_m_axi_arlen ), + .periph_axi_m_axi_arsize (periph_axi_m_axi_arsize ), + .periph_axi_m_axi_arburst(periph_axi_m_axi_arburst), + .periph_axi_m_axi_arlock (periph_axi_m_axi_arlock ), + .periph_axi_m_axi_arcache(periph_axi_m_axi_arcache), + .periph_axi_m_axi_arprot (periph_axi_m_axi_arprot ), + .periph_axi_m_axi_arqos (periph_axi_m_axi_arqos ), + .periph_axi_m_axi_arvalid(periph_axi_m_axi_arvalid), + .periph_axi_m_axi_arready(periph_axi_m_axi_arready), + + .periph_axi_m_axi_rready(periph_axi_m_axi_rready), + .periph_axi_m_axi_rid (periph_axi_m_axi_rid ), + .periph_axi_m_axi_rdata (periph_axi_m_axi_rdata ), + .periph_axi_m_axi_rresp (periph_axi_m_axi_rresp ), + .periph_axi_m_axi_rlast (periph_axi_m_axi_rlast ), + .periph_axi_m_axi_rvalid(periph_axi_m_axi_rvalid), + + // Peripheral axi + + .periph_axi_s_axi_awid (periph_axi_s_axi_awid ), + .periph_axi_s_axi_awaddr (periph_axi_s_axi_awaddr ), + .periph_axi_s_axi_awlen (periph_axi_s_axi_awlen ), + .periph_axi_s_axi_awsize (periph_axi_s_axi_awsize ), + .periph_axi_s_axi_awburst(periph_axi_s_axi_awburst), + .periph_axi_s_axi_awlock (periph_axi_s_axi_awlock ), + .periph_axi_s_axi_awcache(periph_axi_s_axi_awcache), + .periph_axi_s_axi_awprot (periph_axi_s_axi_awprot ), + .periph_axi_s_axi_awqos (periph_axi_s_axi_awqos ), + .periph_axi_s_axi_awvalid(periph_axi_s_axi_awvalid), + .periph_axi_s_axi_awready(periph_axi_s_axi_awready), + + .periph_axi_s_axi_wdata (periph_axi_s_axi_wdata ), + .periph_axi_s_axi_wstrb (periph_axi_s_axi_wstrb ), + .periph_axi_s_axi_wlast (periph_axi_s_axi_wlast ), + .periph_axi_s_axi_wvalid(periph_axi_s_axi_wvalid), + .periph_axi_s_axi_wready(periph_axi_s_axi_wready), + + .periph_axi_s_axi_bready(periph_axi_s_axi_bready), + .periph_axi_s_axi_bid (periph_axi_s_axi_bid ), + .periph_axi_s_axi_bresp (periph_axi_s_axi_bresp ), + .periph_axi_s_axi_bvalid(periph_axi_s_axi_bvalid), + + .periph_axi_s_axi_arid (periph_axi_s_axi_arid ), + .periph_axi_s_axi_araddr (periph_axi_s_axi_araddr ), + .periph_axi_s_axi_arlen (periph_axi_s_axi_arlen ), + .periph_axi_s_axi_arsize (periph_axi_s_axi_arsize ), + .periph_axi_s_axi_arburst(periph_axi_s_axi_arburst), + .periph_axi_s_axi_arlock (periph_axi_s_axi_arlock ), + .periph_axi_s_axi_arcache(periph_axi_s_axi_arcache), + .periph_axi_s_axi_arprot (periph_axi_s_axi_arprot ), + .periph_axi_s_axi_arqos (periph_axi_s_axi_arqos ), + .periph_axi_s_axi_arvalid(periph_axi_s_axi_arvalid), + .periph_axi_s_axi_arready(periph_axi_s_axi_arready), + + .periph_axi_s_axi_rready(periph_axi_s_axi_rready), + .periph_axi_s_axi_rid (periph_axi_s_axi_rid ), + .periph_axi_s_axi_rdata (periph_axi_s_axi_rdata ), + .periph_axi_s_axi_rresp (periph_axi_s_axi_rresp ), + .periph_axi_s_axi_rlast (periph_axi_s_axi_rlast ), + .periph_axi_s_axi_rvalid(periph_axi_s_axi_rvalid) + ); + +endmodule diff --git a/target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv b/target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv new file mode 100644 index 00000000..157bea4e --- /dev/null +++ b/target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv @@ -0,0 +1,676 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Nicole Narr +// Christopher Reinwardt +// Cyril Koenig + +`include "axi/typedef.svh" +`include "cheshire/typedef.svh" + +module cheshire_top_xilinx + import cheshire_pkg::*; +#( +) ( + input logic cpu_reset, + + input logic clk_10, + input logic clk_20, + input logic clk_50, + input logic clk_100, + + input logic testmode_i, + input logic [1:0] boot_mode_i, + + input logic jtag_tck_i, + input logic jtag_tms_i, + input logic jtag_tdi_i, + output logic jtag_tdo_o, + input logic jtag_trst_ni, + output logic jtag_vdd_o, + output logic jtag_gnd_o, + + output logic uart_tx_o, + input logic uart_rx_i, + + // GPIOs will be used as interrupts, + input logic [31:0] gpio_i, + + // Dram axi + + output wire dram_axi_m_aclk, + output wire dram_axi_m_aresetn, + + output wire [6:0] dram_axi_m_axi_awid, + output wire [47:0] dram_axi_m_axi_awaddr, + output wire [7:0] dram_axi_m_axi_awlen, + output wire [2:0] dram_axi_m_axi_awsize, + output wire [1:0] dram_axi_m_axi_awburst, + output wire dram_axi_m_axi_awlock, + output wire [3:0] dram_axi_m_axi_awcache, + output wire [2:0] dram_axi_m_axi_awprot, + output wire [3:0] dram_axi_m_axi_awqos, + output wire dram_axi_m_axi_awvalid, + input wire dram_axi_m_axi_awready, + + output wire [63:0] dram_axi_m_axi_wdata, + output wire [7:0] dram_axi_m_axi_wstrb, + output wire dram_axi_m_axi_wlast, + output wire dram_axi_m_axi_wvalid, + input wire dram_axi_m_axi_wready, + + output wire dram_axi_m_axi_bready, + input wire [6:0] dram_axi_m_axi_bid, + input wire [1:0] dram_axi_m_axi_bresp, + input wire dram_axi_m_axi_bvalid, + + output wire [6:0]dram_axi_m_axi_arid, + output wire [47:0] dram_axi_m_axi_araddr, + output wire [7:0] dram_axi_m_axi_arlen, + output wire [2:0] dram_axi_m_axi_arsize, + output wire [1:0] dram_axi_m_axi_arburst, + output wire dram_axi_m_axi_arlock, + output wire [3:0] dram_axi_m_axi_arcache, + output wire [2:0] dram_axi_m_axi_arprot, + output wire [3:0] dram_axi_m_axi_arqos, + output wire dram_axi_m_axi_arvalid, + input wire dram_axi_m_axi_arready, + + output wire dram_axi_m_axi_rready, + input wire [6:0] dram_axi_m_axi_rid, + input wire [63:0] dram_axi_m_axi_rdata, + input wire [1:0] dram_axi_m_axi_rresp, + input wire dram_axi_m_axi_rlast, + input wire dram_axi_m_axi_rvalid, + + // Periph axi out + + output wire periph_axi_m_aclk, + output wire periph_axi_m_aresetn, + + output wire [1:0] periph_axi_m_axi_awid, + output wire [47:0] periph_axi_m_axi_awaddr, + output wire [7:0] periph_axi_m_axi_awlen, + output wire [2:0] periph_axi_m_axi_awsize, + output wire [1:0] periph_axi_m_axi_awburst, + output wire periph_axi_m_axi_awlock, + output wire [3:0] periph_axi_m_axi_awcache, + output wire [2:0] periph_axi_m_axi_awprot, + output wire [3:0] periph_axi_m_axi_awqos, + output wire periph_axi_m_axi_awvalid, + input wire periph_axi_m_axi_awready, + + output wire [63:0] periph_axi_m_axi_wdata, + output wire [7:0] periph_axi_m_axi_wstrb, + output wire periph_axi_m_axi_wlast, + output wire periph_axi_m_axi_wvalid, + input wire periph_axi_m_axi_wready, + + output wire periph_axi_m_axi_bready, + input wire [1:0] periph_axi_m_axi_bid, + input wire [1:0] periph_axi_m_axi_bresp, + input wire periph_axi_m_axi_bvalid, + + output wire [1:0]periph_axi_m_axi_arid, + output wire [47:0] periph_axi_m_axi_araddr, + output wire [7:0] periph_axi_m_axi_arlen, + output wire [2:0] periph_axi_m_axi_arsize, + output wire [1:0] periph_axi_m_axi_arburst, + output wire periph_axi_m_axi_arlock, + output wire [3:0] periph_axi_m_axi_arcache, + output wire [2:0] periph_axi_m_axi_arprot, + output wire [3:0] periph_axi_m_axi_arqos, + output wire periph_axi_m_axi_arvalid, + input wire periph_axi_m_axi_arready, + + output wire periph_axi_m_axi_rready, + input wire [1:0] periph_axi_m_axi_rid, + input wire [63:0] periph_axi_m_axi_rdata, + input wire [1:0] periph_axi_m_axi_rresp, + input wire periph_axi_m_axi_rlast, + input wire periph_axi_m_axi_rvalid, + + // Periph axi in + + input wire [1:0] periph_axi_s_axi_awid, + input wire [47:0] periph_axi_s_axi_awaddr, + input wire [7:0] periph_axi_s_axi_awlen, + input wire [2:0] periph_axi_s_axi_awsize, + input wire [1:0] periph_axi_s_axi_awburst, + input wire periph_axi_s_axi_awlock, + input wire [3:0] periph_axi_s_axi_awcache, + input wire [2:0] periph_axi_s_axi_awprot, + input wire [3:0] periph_axi_s_axi_awqos, + input wire periph_axi_s_axi_awvalid, + output wire periph_axi_s_axi_awready, + + input wire [63:0] periph_axi_s_axi_wdata, + input wire [7:0] periph_axi_s_axi_wstrb, + input wire periph_axi_s_axi_wlast, + input wire periph_axi_s_axi_wvalid, + output wire periph_axi_s_axi_wready, + + input wire periph_axi_s_axi_bready, + output wire [1:0] periph_axi_s_axi_bid, + output wire [1:0] periph_axi_s_axi_bresp, + output wire periph_axi_s_axi_bvalid, + + input wire [1:0]periph_axi_s_axi_arid, + input wire [47:0] periph_axi_s_axi_araddr, + input wire [7:0] periph_axi_s_axi_arlen, + input wire [2:0] periph_axi_s_axi_arsize, + input wire [1:0] periph_axi_s_axi_arburst, + input wire periph_axi_s_axi_arlock, + input wire [3:0] periph_axi_s_axi_arcache, + input wire [2:0] periph_axi_s_axi_arprot, + input wire [3:0] periph_axi_s_axi_arqos, + input wire periph_axi_s_axi_arvalid, + output wire periph_axi_s_axi_arready, + + input wire periph_axi_s_axi_rready, + output wire [1:0] periph_axi_s_axi_rid, + output wire [63:0] periph_axi_s_axi_rdata, + output wire [1:0] periph_axi_s_axi_rresp, + output wire periph_axi_s_axi_rlast, + output wire periph_axi_s_axi_rvalid + +); + + + // Configure cheshire for FPGA mapping + localparam cheshire_cfg_t FPGACfg = '{ + // CVA6 parameters + Cva6RASDepth : ariane_pkg::ArianeDefaultConfig.RASDepth, + Cva6BTBEntries : ariane_pkg::ArianeDefaultConfig.BTBEntries, + Cva6BHTEntries : ariane_pkg::ArianeDefaultConfig.BHTEntries, + Cva6NrPMPEntries : 0, + Cva6ExtCieLength : 'h2000_0000, + // Harts + NumCores : 1, + CoreMaxTxns : 8, + CoreMaxTxnsPerId : 4, + // Interrupts + NumExtIntrSyncs : 2, + // Interconnect + AddrWidth : 48, + AxiDataWidth : 64, + AxiUserWidth : 2, // Convention: bit 0 for core(s), bit 1 for serial link + AxiMstIdWidth : 2, + AxiMaxMstTrans : 8, + AxiMaxSlvTrans : 8, + AxiUserAmoMsb : 1, + AxiUserAmoLsb : 0, + RegMaxReadTxns : 8, + RegMaxWriteTxns : 8, + RegAmoNumCuts : 1, + RegAmoPostCut : 1, + // RTC + RtcFreq : 1000000, + // Features + Bootrom : 1, + Uart : 1, + I2c : 1, + SpiHost : 1, + Gpio : 1, + Dma : 1, + SerialLink : 0, + Vga : 1, + // Debug + DbgIdCode : CheshireIdCode, + DbgMaxReqs : 4, + DbgMaxReadTxns : 4, + DbgMaxWriteTxns : 4, + DbgAmoNumCuts : 1, + DbgAmoPostCut : 1, + // LLC: 128 KiB, up to 2 GiB DRAM + LlcNotBypass : 1, + LlcSetAssoc : 8, + LlcNumLines : 256, + LlcNumBlocks : 8, + LlcMaxReadTxns : 8, + LlcMaxWriteTxns : 8, + LlcAmoNumCuts : 1, + LlcAmoPostCut : 1, + LlcOutConnect : 1, + LlcOutRegionStart : 'h8000_0000, + LlcOutRegionEnd : 'h1_0000_0000, + // VGA: RGB332 + VgaRedWidth : 5, + VgaGreenWidth : 6, + VgaBlueWidth : 5, + VgaHCountWidth : 24, // TODO: Default is 32; is this needed? + VgaVCountWidth : 24, // TODO: See above + // Serial Link: map other chip's lower 32bit to 'h1_000_0000 + SlinkMaxTxnsPerId : 4, + SlinkMaxUniqIds : 4, + SlinkMaxClkDiv : 1024, + SlinkRegionStart : 'h1_0000_0000, + SlinkRegionEnd : 'h2_0000_0000, + SlinkTxAddrMask : 'hFFFF_FFFF, + SlinkTxAddrDomain : 'h0000_0000, + SlinkUserAmoBit : 1, // Upper atomics bit for serial link + // DMA config + DmaConfMaxReadTxns : 4, + DmaConfMaxWriteTxns : 4, + DmaConfAmoNumCuts : 1, + DmaConfAmoPostCut : 1, + DmaConfEnableTwoD : 1, + DmaNumAxInFlight : 16, + DmaMemSysDepth : 8, + DmaJobFifoDepth : 2, + DmaRAWCouplingAvail : 1, + // GPIOs + GpioInputSyncs : 1, + // All non-set values should be zero + default: '0 + }; + + localparam cheshire_cfg_t CheshireFPGACfg = FPGACfg; + `CHESHIRE_TYPEDEF_ALL(, CheshireFPGACfg) + + /////////////////////////// + // Clk reset definitions // + /////////////////////////// + + logic cpu_resetn; + assign cpu_resetn = ~cpu_reset; + logic sys_rst; + + wire soc_clk; + wire rst_n; + + /////////////////// + // GPIOs // + /////////////////// + + // Give VDD and GND to JTAG + assign jtag_vdd_o = '1; + assign jtag_gnd_o = '0; + + ////////////////// + // Clock Wizard // + ////////////////// + + localparam rtc_clk_divider = 4; + assign soc_clk = clk_50; + + ///////////////////// + // Reset Generator // + ///////////////////// + + rstgen i_rstgen_main ( + .clk_i ( soc_clk ), + .rst_ni ( ~sys_rst ), + .test_mode_i ( testmode_i ), + .rst_no ( rst_n ), + .init_no ( ) // keep open + ); + + /////////////////// + // VIOs // + /////////////////// + + logic [1:0] boot_mode; + + assign sys_rst = cpu_reset; + assign boot_mode = boot_mode_i; + + ///////////////////////// + // "RTC" Clock Divider // + ///////////////////////// + + (* dont_touch = "yes" *) logic rtc_clk_d, rtc_clk_q; + logic [4:0] counter_d, counter_q; + + // Divide clk_10 => 1 MHz RTC Clock + always_comb begin + counter_d = counter_q + 1; + rtc_clk_d = rtc_clk_q; + + if(counter_q == rtc_clk_divider) begin + counter_d = 5'b0; + rtc_clk_d = ~rtc_clk_q; + end + end + + always_ff @(posedge clk_10, negedge rst_n) begin + if(~rst_n) begin + counter_q <= 5'b0; + rtc_clk_q <= 0; + end else begin + counter_q <= counter_d; + rtc_clk_q <= rtc_clk_d; + end + end + + /////////////////// + // LLC interface // + /////////////////// + + // Axi interface + axi_llc_req_t llc_req; + axi_llc_rsp_t llc_rsp; + + assign dram_axi_m_aclk = soc_clk; + assign dram_axi_m_aresetn = rst_n; + + assign dram_axi_m_axi_awid = llc_req.aw.id; + assign dram_axi_m_axi_awaddr = llc_req.aw.addr; + assign dram_axi_m_axi_awlen = llc_req.aw.len; + assign dram_axi_m_axi_awsize = llc_req.aw.size; + assign dram_axi_m_axi_awburst = llc_req.aw.burst; + assign dram_axi_m_axi_awlock = llc_req.aw.lock; + assign dram_axi_m_axi_awcache = llc_req.aw.cache; + assign dram_axi_m_axi_awprot = llc_req.aw.prot; + assign dram_axi_m_axi_awqos = llc_req.aw.qos; + assign dram_axi_m_axi_awvalid = llc_req.aw_valid; + assign llc_rsp.aw_ready = dram_axi_m_axi_awready; + + assign dram_axi_m_axi_wdata = llc_req.w.data; + assign dram_axi_m_axi_wstrb = llc_req.w.strb; + assign dram_axi_m_axi_wlast = llc_req.w.last; + assign dram_axi_m_axi_wvalid = llc_req.w_valid; + assign llc_rsp.w_ready = dram_axi_m_axi_wready; + + assign dram_axi_m_axi_bready = llc_req.b_ready; + assign llc_rsp.b.id = dram_axi_m_axi_bid; + assign llc_rsp.b.resp = dram_axi_m_axi_bresp; + assign llc_rsp.b_valid = dram_axi_m_axi_bvalid; + + assign dram_axi_m_axi_arid = llc_req.ar.id; + assign dram_axi_m_axi_araddr = llc_req.ar.addr; + assign dram_axi_m_axi_arlen = llc_req.ar.len; + assign dram_axi_m_axi_arsize = llc_req.ar.size; + assign dram_axi_m_axi_arburst = llc_req.ar.burst; + assign dram_axi_m_axi_arlock = llc_req.ar.lock; + assign dram_axi_m_axi_arcache = llc_req.ar.cache; + assign dram_axi_m_axi_arprot = llc_req.ar.prot; + assign dram_axi_m_axi_arqos = llc_req.ar.qos; + assign dram_axi_m_axi_arvalid = llc_req.ar_valid; + assign llc_rsp.ar_ready = dram_axi_m_axi_arready; + + assign dram_axi_m_axi_rready = llc_req.r_ready; + assign llc_rsp.r.id = dram_axi_m_axi_rid; + assign llc_rsp.r.data = dram_axi_m_axi_rdata; + assign llc_rsp.r.resp = dram_axi_m_axi_rresp; + assign llc_rsp.r.last = dram_axi_m_axi_rlast; + assign llc_rsp.r_valid = dram_axi_m_axi_rvalid; + + ///////////////////////////////// + // Serial Link to block design // + ///////////////////////////////// + + // Serial link interface + logic [SlinkNumChan-1:0] slink_clk_soc_periph; + logic [SlinkNumChan-1:0] slink_clk_periph_soc; + logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_soc_periph; + logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_periph_soc; + + axi_mst_req_t periph_soc_bd_req, periph_bd_soc_req; + axi_mst_rsp_t periph_soc_bd_rsp, periph_bd_soc_rsp; + + serial_link #( + .axi_req_t ( axi_mst_req_t ), + .axi_rsp_t ( axi_mst_rsp_t ), + .cfg_req_t ( reg_req_t ), + .cfg_rsp_t ( reg_rsp_t ), + .aw_chan_t ( axi_mst_aw_chan_t ), + .ar_chan_t ( axi_mst_ar_chan_t ), + .r_chan_t ( axi_mst_r_chan_t ), + .w_chan_t ( axi_mst_w_chan_t ), + .b_chan_t ( axi_mst_b_chan_t ), + .hw2reg_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t ), + .reg2hw_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t ), + .NumChannels ( SlinkNumChan ), + .NumLanes ( SlinkNumLanes ), + .MaxClkDiv ( SlinkMaxClkDiv ) + ) i_serial_link ( + .clk_i ( host_clk ), + .rst_ni ( rst_n ), + .clk_sl_i ( host_clk ), + .rst_sl_ni ( rst_n ), + .clk_reg_i ( host_clk ), + .rst_reg_ni ( rst_n ), + .testmode_i ( testmode_i ), + .axi_in_req_i ( periph_bd_soc_req ), + .axi_in_rsp_o ( periph_bd_soc_rsp ), + .axi_out_req_o ( periph_soc_bd_req ), + .axi_out_rsp_i ( periph_soc_bd_rsp ), + .cfg_req_i ( '0 ), + .cfg_rsp_o ( ), + .ddr_rcv_clk_i ( slink_clk_soc_periph ), + .ddr_rcv_clk_o ( slink_clk_periph_soc ), + .ddr_i ( slink_soc_periph ), + .ddr_o ( slink_periph_soc ), + .isolated_i ( '0 ), + .isolate_o ( ), + .clk_ena_o ( ), + .reset_no ( ) + ); + + // AXI periph soc to block design + + assign periph_axi_m_aclk = soc_clk; + assign periph_axi_m_aresetn = rst_n; + + assign periph_axi_m_axi_awid = periph_soc_bd_req.aw.id; + assign periph_axi_m_axi_awaddr = periph_soc_bd_req.aw.addr; + assign periph_axi_m_axi_awlen = periph_soc_bd_req.aw.len; + assign periph_axi_m_axi_awsize = periph_soc_bd_req.aw.size; + assign periph_axi_m_axi_awburst = periph_soc_bd_req.aw.burst; + assign periph_axi_m_axi_awlock = periph_soc_bd_req.aw.lock; + assign periph_axi_m_axi_awcache = periph_soc_bd_req.aw.cache; + assign periph_axi_m_axi_awprot = periph_soc_bd_req.aw.prot; + assign periph_axi_m_axi_awqos = periph_soc_bd_req.aw.qos; + assign periph_axi_m_axi_awvalid = periph_soc_bd_req.aw_valid; + assign periph_soc_bd_rsp.aw_ready = periph_axi_m_axi_awready; + + assign periph_axi_m_axi_wdata = periph_soc_bd_req.w.data; + assign periph_axi_m_axi_wstrb = periph_soc_bd_req.w.strb; + assign periph_axi_m_axi_wlast = periph_soc_bd_req.w.last; + assign periph_axi_m_axi_wvalid = periph_soc_bd_req.w_valid; + assign periph_soc_bd_rsp.w_ready = periph_axi_m_axi_wready; + + assign periph_axi_m_axi_bready = periph_soc_bd_req.b_ready; + assign periph_soc_bd_rsp.b.id = periph_axi_m_axi_bid; + assign periph_soc_bd_rsp.b.resp = periph_axi_m_axi_bresp; + assign periph_soc_bd_rsp.b_valid = periph_axi_m_axi_bvalid; + + assign periph_axi_m_axi_arid = periph_soc_bd_req.ar.id; + assign periph_axi_m_axi_araddr = periph_soc_bd_req.ar.addr; + assign periph_axi_m_axi_arlen = periph_soc_bd_req.ar.len; + assign periph_axi_m_axi_arsize = periph_soc_bd_req.ar.size; + assign periph_axi_m_axi_arburst = periph_soc_bd_req.ar.burst; + assign periph_axi_m_axi_arlock = periph_soc_bd_req.ar.lock; + assign periph_axi_m_axi_arcache = periph_soc_bd_req.ar.cache; + assign periph_axi_m_axi_arprot = periph_soc_bd_req.ar.prot; + assign periph_axi_m_axi_arqos = periph_soc_bd_req.ar.qos; + assign periph_axi_m_axi_arvalid = periph_soc_bd_req.ar_valid; + assign periph_soc_bd_rsp.ar_ready = periph_axi_m_axi_arready; + + assign periph_axi_m_axi_rready = periph_soc_bd_req.r_ready; + assign periph_soc_bd_rsp.r.id = periph_axi_m_axi_rid; + assign periph_soc_bd_rsp.r.data = periph_axi_m_axi_rdata; + assign periph_soc_bd_rsp.r.resp = periph_axi_m_axi_rresp; + assign periph_soc_bd_rsp.r.last = periph_axi_m_axi_rlast; + assign periph_soc_bd_rsp.r_valid = periph_axi_m_axi_rvalid; + + // AXI periph block design to soc + + // periph_axi_s_aclk unused (assumed already synch with soc_clk) + // periph_axi_s_aresetn ubused (assumed already synch with reset) + + assign periph_bd_soc_req.aw.id = periph_axi_s_axi_awid ; + assign periph_bd_soc_req.aw.addr = periph_axi_s_axi_awaddr ; + assign periph_bd_soc_req.aw.len = periph_axi_s_axi_awlen ; + assign periph_bd_soc_req.aw.size = periph_axi_s_axi_awsize ; + + assign periph_bd_soc_req.aw.burst = periph_axi_s_axi_awburst ; + assign periph_bd_soc_req.aw.lock = periph_axi_s_axi_awlock ; + assign periph_bd_soc_req.aw.cache = periph_axi_s_axi_awcache ; + assign periph_bd_soc_req.aw.prot = periph_axi_s_axi_awprot ; + assign periph_bd_soc_req.aw.qos = periph_axi_s_axi_awqos ; + assign periph_bd_soc_req.aw_valid = periph_axi_s_axi_awvalid ; + assign periph_axi_s_axi_awready = periph_bd_soc_rsp.aw_ready; + + assign periph_bd_soc_req.w.data = periph_axi_s_axi_wdata ; + assign periph_bd_soc_req.w.strb = periph_axi_s_axi_wstrb ; + assign periph_bd_soc_req.w.last = periph_axi_s_axi_wlast ; + assign periph_bd_soc_req.w_valid = periph_axi_s_axi_wvalid ; + assign periph_axi_s_axi_wready = periph_bd_soc_rsp.w_ready ; + + assign periph_bd_soc_req.b_ready = periph_axi_s_axi_bready ; + assign periph_axi_s_axi_bid = periph_bd_soc_rsp.b.id ; + assign periph_axi_s_axi_bresp = periph_bd_soc_rsp.b.resp ; + assign periph_axi_s_axi_bvalid = periph_bd_soc_rsp.b_valid ; + + assign periph_bd_soc_req.ar.id = periph_axi_s_axi_arid ; + assign periph_bd_soc_req.ar.addr = periph_axi_s_axi_araddr ; + assign periph_bd_soc_req.ar.len = periph_axi_s_axi_arlen ; + assign periph_bd_soc_req.ar.size = periph_axi_s_axi_arsize ; + assign periph_bd_soc_req.ar.burst = periph_axi_s_axi_arburst ; + assign periph_bd_soc_req.ar.lock = periph_axi_s_axi_arlock ; + assign periph_bd_soc_req.ar.cache = periph_axi_s_axi_arcache ; + assign periph_bd_soc_req.ar.prot = periph_axi_s_axi_arprot ; + assign periph_bd_soc_req.ar.qos = periph_axi_s_axi_arqos ; + assign periph_bd_soc_req.ar_valid = periph_axi_s_axi_arvalid ; + assign periph_axi_s_axi_arready = periph_bd_soc_rsp.ar_ready ; + + assign periph_bd_soc_req.r_ready = periph_axi_s_axi_rready ; + assign periph_axi_s_axi_rid = periph_bd_soc_rsp.r.id ; + assign periph_axi_s_axi_rdata = periph_bd_soc_rsp.r.data ; + assign periph_axi_s_axi_rresp = periph_bd_soc_rsp.r.resp ; + assign periph_axi_s_axi_rlast = periph_bd_soc_rsp.r.last ; + assign periph_axi_s_axi_rvalid = periph_bd_soc_rsp.r_valid ; + + ////////////////// + // SPI Adaption // + ////////////////// + + logic spi_sck_soc; + logic [1:0] spi_cs_soc; + logic [3:0] spi_sd_soc_out; + logic [3:0] spi_sd_soc_in; + + logic spi_sck_en; + logic [1:0] spi_cs_en; + logic [3:0] spi_sd_en; + + ////////////////// + // QSPI // + ////////////////// + + logic qspi_clk; + logic qspi_clk_ts; + logic [3:0] qspi_dqi; + logic [3:0] qspi_dqo_ts; + logic [3:0] qspi_dqo; + logic [SpihNumCs-1:0] qspi_cs_b; + logic [SpihNumCs-1:0] qspi_cs_b_ts; + + assign qspi_clk = spi_sck_soc; + assign qspi_cs_b = spi_cs_soc; + assign qspi_dqo = spi_sd_soc_out; + assign spi_sd_soc_in = qspi_dqi; + // Tristate - Enable + assign qspi_clk_ts = ~spi_sck_en; + assign qspi_cs_b_ts = ~spi_cs_en; + assign qspi_dqo_ts = ~spi_sd_en; + + // On VCU128/ZCU102, SPI ports are not directly available + STARTUPE3 #( + .PROG_USR("FALSE"), + .SIM_CCLK_FREQ(0.0) + ) + STARTUPE3_inst ( + .CFGCLK (), + .CFGMCLK (), + .DI (qspi_dqi), + .EOS (), + .PREQ (), + .DO (qspi_dqo), + .DTS (qspi_dqo_ts), + .FCSBO (qspi_cs_b[1]), + .FCSBTS (qspi_cs_b_ts[1]), + .GSR (1'b0), + .GTS (1'b0), + .KEYCLEARB (1'b1), + .PACK (1'b0), + .USRCCLKO (qspi_clk), + .USRCCLKTS (qspi_clk_ts), + .USRDONEO (1'b1), + .USRDONETS (1'b1) + ); + + ////////////////// + // Cheshire SoC // + ////////////////// + + cheshire_soc #( + .Cfg ( FPGACfg ), + .ExtHartinfo ( '0 ), + .axi_ext_llc_req_t ( axi_llc_req_t ), + .axi_ext_llc_rsp_t ( axi_llc_rsp_t ), + .axi_ext_mst_req_t ( axi_mst_req_t ), + .axi_ext_mst_rsp_t ( axi_mst_rsp_t ), + .axi_ext_slv_req_t ( axi_slv_req_t ), + .axi_ext_slv_rsp_t ( axi_slv_rsp_t ), + .reg_ext_req_t ( reg_req_t ), + .reg_ext_rsp_t ( reg_req_t ) + ) i_cheshire_soc ( + .clk_i ( soc_clk ), + .rst_ni ( rst_n ), + .test_mode_i ( testmode_i ), + .boot_mode_i ( boot_mode ), + .rtc_i ( rtc_clk_q ), + .axi_llc_mst_req_o ( llc_req ), + .axi_llc_mst_rsp_i ( llc_rsp ), + .axi_ext_mst_req_i ( '0 ), + .axi_ext_mst_rsp_o ( ), + .axi_ext_slv_req_o ( ), + .axi_ext_slv_rsp_i ( '0 ), + .reg_ext_slv_req_o ( ), + .reg_ext_slv_rsp_i ( '0 ), + .intr_ext_i ( '0 ), + .intr_ext_o ( ), + .xeip_ext_o ( ), + .mtip_ext_o ( ), + .msip_ext_o ( ), + .dbg_active_o ( ), + .dbg_ext_req_o ( ), + .dbg_ext_unavail_i ( '0 ), + .slink_i ( slink_periph_soc ), + .slink_o ( slink_soc_periph ), + .slink_rcv_clk_i ( slink_clk_periph_soc ), + .slink_rcv_clk_o ( slink_clk_soc_periph ), + .jtag_tck_i, + .jtag_trst_ni, + .jtag_tms_i, + .jtag_tdi_i, + .jtag_tdo_o, + // TODO: connect to the tdo pad + .jtag_tdo_oe_o ( ), + .i2c_sda_o ( ), + .i2c_sda_i ( '0 ), + .i2c_sda_en_o ( ), + .i2c_scl_o ( ), + .i2c_scl_i ( '0 ), + .i2c_scl_en_o ( ), + .spih_sck_o ( spi_sck_soc ), + .spih_sck_en_o ( spi_sck_en ), + .spih_csb_o ( spi_cs_soc ), + .spih_csb_en_o ( spi_cs_en ), + .spih_sd_o ( spi_sd_soc_out ), + .spih_sd_en_o ( spi_sd_en ), + .spih_sd_i ( spi_sd_soc_in ), + .vga_hsync_o ( ), + .vga_vsync_o ( ), + .vga_red_o ( ), + .vga_green_o ( ), + .vga_blue_o ( ), + .uart_tx_o, + .uart_rx_i + ); + +endmodule diff --git a/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/cheshire.xdc b/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/cheshire.xdc new file mode 100644 index 00000000..ae035065 --- /dev/null +++ b/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/cheshire.xdc @@ -0,0 +1,93 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig + +##################### +# Timing Parameters # +##################### + +# 10 MHz (max) JTAG clock +set JTAG_TCK 100.0 + +# UART speed is at most 5 Mb/s +set UART_IO_SPEED 200.0 + +########## +# Clocks # +########## + +# Clk_wiz clocks are named clk_(100,50,20,10)_xlnx_clk_wiz +# They are on pins : i_xlnx_clk_wiz/inst/mmcme4_adv_inst/CLKOUT(0,1,2,3) + +# System Clock +# [see in board.xdc] + +# JTAG Clock +create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] +set_input_jitter clk_jtag 1.000 + +########## +# BUFG # +########## + +# JTAG are on non clock capable GPIOs (if not using BSCANE) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset*]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset*]] + +# Remove avoid tc_clk_mux2 to use global clock routing +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + +################ +# Clock Groups # +################ + +# JTAG Clock is asynchronous to all other clocks +set_clock_groups -name jtag_async -asynchronous -group {clk_jtag} + +######## +# JTAG # +######## + +set_input_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] +set_input_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] + +set_output_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports jtag_tdo_o] +set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_tdo_o] + +set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK +set_false_path -hold -from [get_ports jtag_trst_ni] + +######## +# UART # +######## + +set_max_delay [expr $UART_IO_SPEED * 0.35] -from [get_ports uart_rx_i] +set_false_path -hold -from [get_ports uart_rx_i] + +set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o] +set_false_path -hold -to [get_ports uart_tx_o] + +######## +# CDCs # +######## + +# Disable hold checks +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -filter {NAME=~*serial_i}] + +# src false path +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}] +# dst false path +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}] + +# Limit datapath delay +# [see in board.xdc] diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/genesys2.xdc similarity index 92% rename from target/xilinx/constraints/genesys2.xdc rename to target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/genesys2.xdc index 7142b159..ef635363 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/genesys2.xdc @@ -1,11 +1,115 @@ -#### This file is a general .xdc for the Genesys 2 Rev. H -#### To use it in a project: -#### - uncomment the lines corresponding to used pins -#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +##################### +# Timing Parameters # +##################### + +# 50 MHz SoC clock +create_generated_clock -name soc_clk -divide_by 1 -source [get_pins i_xlnx_clk_wiz/inst/mmcm_adv_inst/CLKOUT1] [get_nets soc_clk] +set soc_clk soc_clk +set SOC_TCK 20.0 + +# I2C High-speed mode is 3.2 Mb/s +set I2C_IO_SPEED 312.5 + +########## +# Basics # +########## + +# Testmode is set to 0 during normal use +set_case_analysis 0 [get_ports testmode_i] + +############# +# Sys clock # +############# + +# 200 MHz ref clock +set SYS_TCK 5 +create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] + +############# +# Mig clock # +############# + +# Dram axi clock : 200 MHz +set MIG_TCK 5 +create_generated_clock -source [get_pins i_dram_wrapper/i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT] \ + -divide_by 1 -add -master_clock clk_pll_i -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/ui_clk] +# Aynch reset in +set MIG_RST_I [get_pin i_dram_wrapper/i_dram/aresetn] +set_false_path -hold -setup -through $MIG_RST_I +# Synch reset out +set MIG_RST_O [get_pins i_dram_wrapper/i_dram/ui_clk] +set_false_path -hold -through $MIG_RST_O +set_max_delay -through $MIG_RST_O $MIG_TCK + +######## +# CDCs # +######## + +set_max_delay -datapath \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK + +set_max_delay -datapath \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK + + +####### +# VGA # +####### + +set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports vga*] +set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports vga*] + +############ +# Switches # +############ + +set_input_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* testmode_i}] +set_input_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* testmode_i}] + +set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports fan_pwm] +set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports fan_pwm] + +set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* testmode_i}] +set_false_path -hold -from [get_ports {boot_mode* fan_sw* testmode_i}] + +set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm] +set_false_path -hold -to [get_ports fan_pwm] + +######## +# SPIM # +######## + +set_input_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_input_delay -max -clock $soc_clk [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_output_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] +set_output_delay -max -clock $soc_clk [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] + +####### +# I2C # +####### + +set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] +set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] + +set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] +set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] + +################################################################################# + +############### +# ASSIGN PINS # +############### ## Clock Signal -set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n -set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p +set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n +set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p ## Buttons #set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc @@ -33,7 +137,7 @@ set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] #set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { test_mode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { testmode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] ## USB HIDs For Both Mouse and Keyboard #set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0] diff --git a/target/xilinx/flavor_vanilla/constraints/cheshire.xdc b/target/xilinx/flavor_vanilla/constraints/cheshire.xdc new file mode 100644 index 00000000..ae035065 --- /dev/null +++ b/target/xilinx/flavor_vanilla/constraints/cheshire.xdc @@ -0,0 +1,93 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig + +##################### +# Timing Parameters # +##################### + +# 10 MHz (max) JTAG clock +set JTAG_TCK 100.0 + +# UART speed is at most 5 Mb/s +set UART_IO_SPEED 200.0 + +########## +# Clocks # +########## + +# Clk_wiz clocks are named clk_(100,50,20,10)_xlnx_clk_wiz +# They are on pins : i_xlnx_clk_wiz/inst/mmcme4_adv_inst/CLKOUT(0,1,2,3) + +# System Clock +# [see in board.xdc] + +# JTAG Clock +create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] +set_input_jitter clk_jtag 1.000 + +########## +# BUFG # +########## + +# JTAG are on non clock capable GPIOs (if not using BSCANE) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset*]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset*]] + +# Remove avoid tc_clk_mux2 to use global clock routing +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + +################ +# Clock Groups # +################ + +# JTAG Clock is asynchronous to all other clocks +set_clock_groups -name jtag_async -asynchronous -group {clk_jtag} + +######## +# JTAG # +######## + +set_input_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] +set_input_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] + +set_output_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports jtag_tdo_o] +set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_tdo_o] + +set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK +set_false_path -hold -from [get_ports jtag_trst_ni] + +######## +# UART # +######## + +set_max_delay [expr $UART_IO_SPEED * 0.35] -from [get_ports uart_rx_i] +set_false_path -hold -from [get_ports uart_rx_i] + +set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o] +set_false_path -hold -to [get_ports uart_tx_o] + +######## +# CDCs # +######## + +# Disable hold checks +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -filter {NAME=~*serial_i}] + +# src false path +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}] +# dst false path +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}] + +# Limit datapath delay +# [see in board.xdc] diff --git a/target/xilinx/flavor_vanilla/constraints/genesys2.xdc b/target/xilinx/flavor_vanilla/constraints/genesys2.xdc new file mode 100644 index 00000000..ef635363 --- /dev/null +++ b/target/xilinx/flavor_vanilla/constraints/genesys2.xdc @@ -0,0 +1,540 @@ +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +##################### +# Timing Parameters # +##################### + +# 50 MHz SoC clock +create_generated_clock -name soc_clk -divide_by 1 -source [get_pins i_xlnx_clk_wiz/inst/mmcm_adv_inst/CLKOUT1] [get_nets soc_clk] +set soc_clk soc_clk +set SOC_TCK 20.0 + +# I2C High-speed mode is 3.2 Mb/s +set I2C_IO_SPEED 312.5 + +########## +# Basics # +########## + +# Testmode is set to 0 during normal use +set_case_analysis 0 [get_ports testmode_i] + +############# +# Sys clock # +############# + +# 200 MHz ref clock +set SYS_TCK 5 +create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] + +############# +# Mig clock # +############# + +# Dram axi clock : 200 MHz +set MIG_TCK 5 +create_generated_clock -source [get_pins i_dram_wrapper/i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT] \ + -divide_by 1 -add -master_clock clk_pll_i -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/ui_clk] +# Aynch reset in +set MIG_RST_I [get_pin i_dram_wrapper/i_dram/aresetn] +set_false_path -hold -setup -through $MIG_RST_I +# Synch reset out +set MIG_RST_O [get_pins i_dram_wrapper/i_dram/ui_clk] +set_false_path -hold -through $MIG_RST_O +set_max_delay -through $MIG_RST_O $MIG_TCK + +######## +# CDCs # +######## + +set_max_delay -datapath \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK + +set_max_delay -datapath \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK + + +####### +# VGA # +####### + +set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports vga*] +set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports vga*] + +############ +# Switches # +############ + +set_input_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* testmode_i}] +set_input_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* testmode_i}] + +set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports fan_pwm] +set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports fan_pwm] + +set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* testmode_i}] +set_false_path -hold -from [get_ports {boot_mode* fan_sw* testmode_i}] + +set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm] +set_false_path -hold -to [get_ports fan_pwm] + +######## +# SPIM # +######## + +set_input_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_input_delay -max -clock $soc_clk [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_output_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] +set_output_delay -max -clock $soc_clk [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] + +####### +# I2C # +####### + +set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] +set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] + +set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] +set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] + +################################################################################# + +############### +# ASSIGN PINS # +############### + +## Clock Signal +set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n +set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p + +## Buttons +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_0_15 Sch=btnd +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L6P_T0_15 Sch=btnl +#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L24P_T3_17 Sch=btnr +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_L24N_T3_17 Sch=btnu +set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_0_14 Sch=cpu_resetn + +## LEDs +#set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0] +#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1] +#set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2] +#set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3] +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4] +#set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5] +#set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6] +#set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7] + +## Switches +set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[0] }]; #IO_0_17 Sch=sw[0] +set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[1] }]; #IO_25_16 Sch=sw[1] +set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[0] }]; #IO_L19P_T3_16 Sch=sw[2] +set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[1] }]; #IO_L6P_T0_17 Sch=sw[3] +set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] +set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] +#set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { testmode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] + +## USB HIDs For Both Mouse and Keyboard +#set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0] +#set_property -dict { PACKAGE_PIN AE20 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_data_0 }]; #IO_25_12 Sch=ps2_data[0] + +## UART +set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L1P_T0_12 Sch=uart_rx_out +set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_0_12 Sch=uart_tx_in + +## SD Card +set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd_i }]; #IO_L8N_T1_D12_14 Sch=sd_cd +set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd_o }]; #IO_L7N_T1_D10_14 Sch=sd_cmd +set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0] +set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1] +set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2] +set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3] +set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset +set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk_o }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk + +## Audio Codec +#set_property -dict { PACKAGE_PIN AH19 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L8N_T1_32 Sch=aud_adc_sdata +#set_property -dict { PACKAGE_PIN AD19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L10P_T1_32 Sch=aud_adr[0] +#set_property -dict { PACKAGE_PIN AG19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L8P_T1_32 Sch=aud_adr[1] +#set_property -dict { PACKAGE_PIN AG18 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L11N_T1_SRCC_32 Sch=aud_bclk +#set_property -dict { PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L7P_T1_32 Sch=aud_dac_sdata +#set_property -dict { PACKAGE_PIN AJ18 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L9P_T1_DQS_32 Sch=aud_lrclk +#set_property -dict { PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L7N_T1_32 Sch=aud_mclk +#set_property -dict { PACKAGE_PIN AE19 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L10N_T1_32 Sch=aud_scl +#set_property -dict { PACKAGE_PIN AF18 IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_L11P_T1_SRCC_32 Sch=aud_sda + +## Ethernet +#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb +#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n +#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb +#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk +#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl +#set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0] +#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1] +#set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2] +#set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3] +#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk +#set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0] +#set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1] +#set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2] +#set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3] +#set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en + +## VGA Connector +set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] +set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] +set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5] +set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6] +set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7] + +set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2] +set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3] +set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4] +set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5] +set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6] +set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7] + +set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3] +set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4] +set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5] +set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6] +set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7] + +set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs +set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs + +## HDMI in +#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L2P_T0_12 Sch=hdmi_rx_cec +#set_property -dict { PACKAGE_PIN AF28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_clk_n +#set_property -dict { PACKAGE_PIN AE28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L14P_T2_SRCC_13 Sch=hdmi_rx_clk_p +#set_property -dict { PACKAGE_PIN AH29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_hpa +#set_property -dict { PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17P_T2_13 Sch=hdmi_rx_scl +#set_property -dict { PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_13 Sch=hdmi_rx_sda +#set_property -dict { PACKAGE_PIN AK26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0] +#set_property -dict { PACKAGE_PIN AJ26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0] +#set_property -dict { PACKAGE_PIN AG28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L21N_T3_DQS_13 Sch=hdmi_rx_n[1] +#set_property -dict { PACKAGE_PIN AG27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L21P_T3_DQS_13 Sch=hdmi_rx_p[1] +#set_property -dict { PACKAGE_PIN AH27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[2] +#set_property -dict { PACKAGE_PIN AH26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[2] + +## HDMI out +#set_property -dict { PACKAGE_PIN Y24 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L1N_T0_12 Sch=hdmi_tx_cec +#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L6N_T0_VREF_12 Sch=hdmi_tx_clk_n +#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L6P_T0_12 Sch=hdmi_tx_clk_p +#set_property -dict { PACKAGE_PIN AG29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_tx_hpd +#set_property -dict { PACKAGE_PIN AF27 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L23N_T3_13 Sch=hdmi_tx_scl +#set_property -dict { PACKAGE_PIN AF26 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L23P_T3_13 Sch=hdmi_tx_sda +#set_property -dict { PACKAGE_PIN AC21 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_12 Sch=hdmi_tx_n[0] +#set_property -dict { PACKAGE_PIN AC20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_12 Sch=hdmi_tx_p[0] +#set_property -dict { PACKAGE_PIN AA23 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L4N_T0_12 Sch=hdmi_tx_n[1] +#set_property -dict { PACKAGE_PIN AA22 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L4P_T0_12 Sch=hdmi_tx_p[1] +#set_property -dict { PACKAGE_PIN AC25 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L7N_T1_12 Sch=hdmi_tx_n[2] +#set_property -dict { PACKAGE_PIN AB24 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L7P_T1_12 Sch=hdmi_tx_p[2] + +## OLED Display +#set_property -dict { PACKAGE_PIN AC17 IOSTANDARD LVCMOS18 } [get_ports { oled_dc }]; #IO_L18N_T2_32 Sch=oled_dc +#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS18 } [get_ports { oled_res }]; #IO_L18P_T2_32 Sch=oled_res +#set_property -dict { PACKAGE_PIN AF17 IOSTANDARD LVCMOS18 } [get_ports { oled_sclk }]; #IO_L12P_T1_MRCC_32 Sch=oled_sclk +#set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { oled_sdin }]; #IO_L24N_T3_32 Sch=oled_sdin +#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_L3P_T0_DQS_12 Sch=oled_vbat +#set_property -dict { PACKAGE_PIN AG17 IOSTANDARD LVCMOS18 } [get_ports { oled_vdd }]; #IO_L12N_T1_MRCC_32 Sch=oled_vdd + +## PMOD Header JA +#set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1] +#set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1] +#set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2] +#set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2] +#set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3] +#set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3] +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4] +#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4] + +## PMOD Header JB +#set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L17P_T2_A14_D30_14 Sch=jb_p[1] +#set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L17N_T2_A13_D29_14 Sch=jb_n[1] +#set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L18P_T2_A12_D28_14 Sch=jb_p[2] +#set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L18N_T2_A11_D27_14 Sch=jb_n[2] +#set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L14P_T2_SRCC_14 Sch=jb_p[3] +#set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L14N_T2_SRCC_14 Sch=jb_n[3] +#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L21P_T3_DQS_14 Sch=jb_p[4] +#set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4] + +## PMOD Header JC +#set_property -dict { PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L19P_T3_13 Sch=jc[1] +#set_property -dict { PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20P_T3_13 Sch=jc[2] +#set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L18N_T2_13 Sch=jc[3] +#set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15P_T2_DQS_13 Sch=jc[4] +#set_property -dict { PACKAGE_PIN AD26 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L19N_T3_VREF_13 Sch=jc[7] +#set_property -dict { PACKAGE_PIN AG30 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L18P_T2_13 Sch=jc[8] +#set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L15N_T2_DQS_13 Sch=jc[9] +#set_property -dict { PACKAGE_PIN AK28 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_13 Sch=jc[10] + +## PMOD Header JD +#set_property -dict { PACKAGE_PIN V27 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1] +#set_property -dict { PACKAGE_PIN Y30 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L8P_T1_13 Sch=jd[2] +#set_property -dict { PACKAGE_PIN V24 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3] +#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4] +#set_property -dict { PACKAGE_PIN U24 IOSTANDARD LVCMOS33 } [get_ports { spi_sck_o }]; #IO_L23P_T3_A03_D19_14 Sch=jd[7] +#set_property -dict { PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 } [get_ports { spi_cs_o }]; #IO_L1P_T0_13 Sch=jd[8] +#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { spi_mosi_o }]; #IO_L22N_T3_A04_D20_14 Sch=jd[9] +#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { spi_miso_i }]; #IO_L24P_T3_A01_D17_14 Sch=jd[10] + +## XADC Header +#set_property -dict { PACKAGE_PIN J24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD0N_15 Sch=xadc0r_n +#set_property -dict { PACKAGE_PIN J23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD0P_15 Sch=xadc0r_p +#set_property -dict { PACKAGE_PIN K24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xadc1r_n +#set_property -dict { PACKAGE_PIN K23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xadc1r_p +#set_property -dict { PACKAGE_PIN L23 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xadc8r_n +#set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xadc8r_p +#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L4N_T0_AD9N_15 Sch=xadc9r_n +#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L4P_T0_AD9P_15 Sch=xadc9r_p + +## FMC +#set_property -dict { PACKAGE_PIN AB30 IOSTANDARD LVCMOS33 } [get_ports { FMC_CLK_DIR }]; #IO_L10N_T1_13 Sch=fmc_clk_dir +#set_property -dict { PACKAGE_PIN E20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_17 Sch=fmc_clk0_m2c_n +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_17 Sch=fmc_clk0_m2c_p +#set_property -dict { PACKAGE_PIN D28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L14N_T2_SRCC_16 Sch=fmc_clk1_m2c_n +#set_property -dict { PACKAGE_PIN E28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L14P_T2_SRCC_16 Sch=fmc_clk1_m2c_p +#set_property -dict { PACKAGE_PIN K25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_N[2] }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=fmc_clk_n[2] +#set_property -dict { PACKAGE_PIN L25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_P[2] }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=fmc_clk_p[2] +#set_property -dict { PACKAGE_PIN K29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[00] }]; #IO_L13N_T2_MRCC_15 Sch=fmc_ha_n[00] +#set_property -dict { PACKAGE_PIN K28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[00] }]; #IO_L13P_T2_MRCC_15 Sch=fmc_ha_p[00] +#set_property -dict { PACKAGE_PIN L28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[01] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_ha_n[01] +#set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[01] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_ha_p[01] +#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[02] }]; #IO_L22N_T3_A16_15 Sch=fmc_ha_n[02] +#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[02] }]; #IO_L22P_T3_A17_15 Sch=fmc_ha_p[02] +#set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[03] }]; #IO_L18N_T2_A23_15 Sch=fmc_ha_n[03] +#set_property -dict { PACKAGE_PIN N25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[03] }]; #IO_L18P_T2_A24_15 Sch=fmc_ha_p[03] +#set_property -dict { PACKAGE_PIN M25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[04] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_ha_n[04] +#set_property -dict { PACKAGE_PIN M24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[04] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_ha_p[04] +#set_property -dict { PACKAGE_PIN H29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[05] }]; #IO_L7N_T1_AD10N_15 Sch=fmc_ha_n[05] +#set_property -dict { PACKAGE_PIN J29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[05] }]; #IO_L7P_T1_AD10P_15 Sch=fmc_ha_p[05] +#set_property -dict { PACKAGE_PIN N30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[06] }]; #IO_L17N_T2_A25_15 Sch=fmc_ha_n[06] +#set_property -dict { PACKAGE_PIN N29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[06] }]; #IO_L17P_T2_A26_15 Sch=fmc_ha_p[06] +#set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[07] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_ha_n[07] +#set_property -dict { PACKAGE_PIN M29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[07] }]; #IO_L15P_T2_DQS_15 Sch=fmc_ha_p[07] +#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[08] }]; #IO_L8N_T1_AD3N_15 Sch=fmc_ha_n[08] +#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[08] }]; #IO_L8P_T1_AD3P_15 Sch=fmc_ha_p[08] +#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[09] }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fmc_ha_n[09] +#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[09] }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fmc_ha_p[09] +#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[10] }]; #IO_L20N_T3_A19_15 Sch=fmc_ha_n[10] +#set_property -dict { PACKAGE_PIN N21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[10] }]; #IO_L20P_T3_A20_15 Sch=fmc_ha_p[10] +#set_property -dict { PACKAGE_PIN N24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[11] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_ha_n[11] +#set_property -dict { PACKAGE_PIN P23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[11] }]; #IO_L21P_T3_DQS_15 Sch=fmc_ha_p[11] +#set_property -dict { PACKAGE_PIN L27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[12] }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=fmc_ha_n[12] +#set_property -dict { PACKAGE_PIN L26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[12] }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=fmc_ha_p[12] +#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[13] }]; #IO_L10N_T1_AD4N_15 Sch=fmc_ha_n[13] +#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[13] }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] +#set_property -dict { PACKAGE_PIN M27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[14] }]; #IO_L16N_T2_A27_15 Sch=fmc_ha_n[14] +#set_property -dict { PACKAGE_PIN N27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[14] }]; #IO_L16P_T2_A28_15 Sch=fmc_ha_p[14] +#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[15] }]; #IO_L5N_T0_AD2N_15 Sch=fmc_ha_n[15] +#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[15] }]; #IO_L5P_T0_AD2P_15 Sch=fmc_ha_p[15] +#set_property -dict { PACKAGE_PIN M23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[16] }]; #IO_L24N_T3_RS0_15 Sch=fmc_ha_n[16] +#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[16] }]; #IO_L24P_T3_RS1_15 Sch=fmc_ha_p[16] +#set_property -dict { PACKAGE_PIN B25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[17] }]; #IO_L12N_T1_MRCC_16 Sch=fmc_ha_n[17] +#set_property -dict { PACKAGE_PIN C25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[17] }]; #IO_L12P_T1_MRCC_16 Sch=fmc_ha_p[17] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[18] }]; #IO_L14N_T2_SRCC_17 Sch=fmc_ha_n[18] +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[18] }]; #IO_L14P_T2_SRCC_17 Sch=fmc_ha_p[18] +#set_property -dict { PACKAGE_PIN F30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[19] }]; #IO_L22N_T3_16 Sch=fmc_ha_n[19] +#set_property -dict { PACKAGE_PIN G29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[19] }]; #IO_L22P_T3_16 Sch=fmc_ha_p[19] +#set_property -dict { PACKAGE_PIN F27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[20] }]; #IO_L21N_T3_DQS_16 Sch=fmc_ha_n[20] +#set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[20] }]; #IO_L21P_T3_DQS_16 Sch=fmc_ha_p[20] +#set_property -dict { PACKAGE_PIN F28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[21] }]; #IO_L20N_T3_16 Sch=fmc_ha_n[21] +#set_property -dict { PACKAGE_PIN G28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[21] }]; #IO_L20P_T3_16 Sch=fmc_ha_p[21] +#set_property -dict { PACKAGE_PIN C21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[22] }]; #IO_L8N_T1_17 Sch=fmc_ha_n[22] +#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[22] }]; #IO_L8P_T1_17 Sch=fmc_ha_p[22] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[23] }]; #IO_L16N_T2_17 Sch=fmc_ha_n[23] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[23] }]; #IO_L16P_T2_17 Sch=fmc_ha_p[23] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[00] }]; #IO_L12N_T1_MRCC_18 Sch=fmc_hb_n[00] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[00] }]; #IO_L12P_T1_MRCC_18 Sch=fmc_hb_p[00] +#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[01] }]; #IO_L7N_T1_18 Sch=fmc_hb_n[01] +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[01] }]; #IO_L7P_T1_18 Sch=fmc_hb_p[01] +#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[02] }]; #IO_L2N_T0_18 Sch=fmc_hb_n[02] +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[02] }]; #IO_L2P_T0_18 Sch=fmc_hb_p[02] +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[03] }]; #IO_L11N_T1_SRCC_18 Sch=fmc_hb_n[03] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[03] }]; #IO_L11P_T1_SRCC_18 Sch=fmc_hb_p[03] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[04] }]; #IO_L9N_T1_DQS_18 Sch=fmc_hb_n[04] +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[04] }]; #IO_L9P_T1_DQS_18 Sch=fmc_hb_p[04] +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[05] }]; #IO_L1N_T0_18 Sch=fmc_hb_n[05] +#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[05] }]; #IO_L1P_T0_18 Sch=fmc_hb_p[05] +#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[06] }]; #IO_L14N_T2_SRCC_18 Sch=fmc_hb_n[06] +#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[06] }]; #IO_L14P_T2_SRCC_18 Sch=fmc_hb_p[06] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[07] }]; #IO_L22N_T3_18 Sch=fmc_hb_n[07] +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[07] }]; #IO_L22P_T3_18 Sch=fmc_hb_p[07] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[08] }]; #IO_L5N_T0_18 Sch=fmc_hb_n[08] +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[08] }]; #IO_L5P_T0_18 Sch=fmc_hb_p[08] +#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[09] }]; #IO_L23N_T3_18 Sch=fmc_hb_n[09] +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[09] }]; #IO_L23P_T3_18 Sch=fmc_hb_p[09] +#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[10] }]; #IO_L8N_T1_18 Sch=fmc_hb_n[10] +#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[10] }]; #IO_L8P_T1_18 Sch=fmc_hb_p[10] +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[11] }]; #IO_L18N_T2_18 Sch=fmc_hb_n[11] +#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[11] }]; #IO_L18P_T2_18 Sch=fmc_hb_p[11] +#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[12] }]; #IO_L17N_T2_18 Sch=fmc_hb_n[12] +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[12] }]; #IO_L17P_T2_18 Sch=fmc_hb_p[12] +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[13] }]; #IO_L15N_T2_DQS_18 Sch=fmc_hb_n[13] +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[13] }]; #IO_L15P_T2_DQS_18 Sch=fmc_hb_p[13] +#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[14] }]; #IO_L10N_T1_18 Sch=fmc_hb_n[14] +#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[14] }]; #IO_L10P_T1_18 Sch=fmc_hb_p[14] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[15] }]; #IO_L3N_T0_DQS_18 Sch=fmc_hb_n[15] +#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[15] }]; #IO_L3P_T0_DQS_18 Sch=fmc_hb_p[15] +#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[16] }]; #IO_L4N_T0_18 Sch=fmc_hb_n[16] +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[16] }]; #IO_L4P_T0_18 Sch=fmc_hb_p[16] +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[17] }]; #IO_L13N_T2_MRCC_18 Sch=fmc_hb_n[17] +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[17] }]; #IO_L13P_T2_MRCC_18 Sch=fmc_hb_p[17] +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[18] }]; #IO_L20N_T3_18 Sch=fmc_hb_n[18] +#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[18] }]; #IO_L20P_T3_18 Sch=fmc_hb_p[18] +#set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[19] }]; #IO_L16N_T2_18 Sch=fmc_hb_n[19] +#set_property -dict { PACKAGE_PIN F11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[19] }]; #IO_L16P_T2_18 Sch=fmc_hb_p[19] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[20] }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[20] }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[21] }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[21] }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21] +#set_property -dict { PACKAGE_PIN C27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[00] }]; #IO_L13N_T2_MRCC_16 Sch=fmc_la_n[00] +#set_property -dict { PACKAGE_PIN D27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[00] }]; #IO_L13P_T2_MRCC_16 Sch=fmc_la_p[00] +#set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[01] }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la_n[01] +#set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[01] }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la_p[01] +#set_property -dict { PACKAGE_PIN G30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L24N_T3_16 Sch=fmc_la_n[02] +#set_property -dict { PACKAGE_PIN H30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L24P_T3_16 Sch=fmc_la_p[02] +#set_property -dict { PACKAGE_PIN E30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L18N_T2_16 Sch=fmc_la_n[03] +#set_property -dict { PACKAGE_PIN E29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L18P_T2_16 Sch=fmc_la_p[03] +#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] +#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] +#set_property -dict { PACKAGE_PIN A30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L17N_T2_16 Sch=fmc_la_n[05] +#set_property -dict { PACKAGE_PIN B30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L17P_T2_16 Sch=fmc_la_p[05] +#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] +#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] +#set_property -dict { PACKAGE_PIN E25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[07] +#set_property -dict { PACKAGE_PIN F25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[07] +#set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[08] +#set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[08] +#set_property -dict { PACKAGE_PIN A28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[09] +#set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[09] +#set_property -dict { PACKAGE_PIN A27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L7N_T1_16 Sch=fmc_la_n[10] +#set_property -dict { PACKAGE_PIN B27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L7P_T1_16 Sch=fmc_la_p[10] +#set_property -dict { PACKAGE_PIN A26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L10N_T1_16 Sch=fmc_la_n[11] +#set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L10P_T1_16 Sch=fmc_la_p[11] +#set_property -dict { PACKAGE_PIN E26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L5N_T0_16 Sch=fmc_la_n[12] +#set_property -dict { PACKAGE_PIN F26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L5P_T0_16 Sch=fmc_la_p[12] +#set_property -dict { PACKAGE_PIN D24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L4N_T0_16 Sch=fmc_la_n[13] +#set_property -dict { PACKAGE_PIN E24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L4P_T0_16 Sch=fmc_la_p[13] +#set_property -dict { PACKAGE_PIN B24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L8N_T1_16 Sch=fmc_la_n[14] +#set_property -dict { PACKAGE_PIN C24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L8P_T1_16 Sch=fmc_la_p[14] +#set_property -dict { PACKAGE_PIN A23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L1N_T0_16 Sch=fmc_la_n[15] +#set_property -dict { PACKAGE_PIN B23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L1P_T0_16 Sch=fmc_la_p[15] +#set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L2N_T0_16 Sch=fmc_la_n[16] +#set_property -dict { PACKAGE_PIN E23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L2P_T0_16 Sch=fmc_la_p[16] +#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[17] }]; #IO_L11N_T1_SRCC_17 Sch=fmc_la_n[17] +#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[17] }]; #IO_L11P_T1_SRCC_17 Sch=fmc_la_p[17] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[18] }]; #IO_L13N_T2_MRCC_17 Sch=fmc_la_n[18] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[18] }]; #IO_L13P_T2_MRCC_17 Sch=fmc_la_p[18] +#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L7N_T1_17 Sch=fmc_la_n[19] +#set_property -dict { PACKAGE_PIN H21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L7P_T1_17 Sch=fmc_la_p[19] +#set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L9N_T1_DQS_17 Sch=fmc_la_n[20] +#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L9P_T1_DQS_17 Sch=fmc_la_p[20] +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L5N_T0_17 Sch=fmc_la_n[21] +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L5P_T0_17 Sch=fmc_la_p[21] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0_DQS_17 Sch=fmc_la_n[22] +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0_DQS_17 Sch=fmc_la_p[22] +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L18N_T2_17 Sch=fmc_la_n[23] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L18P_T2_17 Sch=fmc_la_p[23] +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L2N_T0_17 Sch=fmc_la_n[24] +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L2P_T0_17 Sch=fmc_la_p[24] +#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L10N_T1_17 Sch=fmc_la_n[25] +#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L10P_T1_17 Sch=fmc_la_p[25] +#set_property -dict { PACKAGE_PIN A22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L23N_T3_17 Sch=fmc_la_n[26] +#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L23P_T3_17 Sch=fmc_la_p[26] +#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L21N_T3_DQS_17 Sch=fmc_la_n[27] +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L21P_T3_DQS_17 Sch=fmc_la_p[27] +#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L4N_T0_17 Sch=fmc_la_n[28] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L4P_T0_17 Sch=fmc_la_p[28] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L22N_T3_17 Sch=fmc_la_n[29] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L22P_T3_17 Sch=fmc_la_p[29] +#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L20N_T3_17 Sch=fmc_la_n[30] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L20P_T3_17 Sch=fmc_la_p[30] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L17N_T2_17 Sch=fmc_la_n[31] +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L17P_T2_17 Sch=fmc_la_p[31] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L1N_T0_17 Sch=fmc_la_n[32] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L1P_T0_17 Sch=fmc_la_p[32] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L15N_T2_DQS_17 Sch=fmc_la_n[33] +#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L15P_T2_DQS_17 Sch=fmc_la_p[33] +#set_property -dict { PACKAGE_PIN AC24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SCL }]; #IO_L9P_T1_DQS_12 Sch=fmc_scl +#set_property -dict { PACKAGE_PIN AD24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SDA }]; #IO_L9N_T1_DQS_12 Sch=fmc_sda + +## Fan Control +set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { fan_pwm }]; #IO_25_14 Sch=fan_pwm +#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tach + +## DPTI +## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins. +#set_property -dict { PACKAGE_PIN AB27 IOSTANDARD LVCMOS33 } [get_ports { PROG_CLKO }]; #IO_L12P_T1_MRCC_13 Sch=prog_clko +set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { jtag_tck_i }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck +set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdi_i }]; #IO_L2P_T0_13 Sch=prog_d1/mosi +set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdo_o }]; #IO_L2N_T0_13 Sch=prog_d2/miso +set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { jtag_tms_i }]; #IO_L4P_T0_13 Sch=prog_d3/ss +set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { jtag_trst_ni }]; #IO_L4N_T0_13 Sch=prog_d[4] +#set_property -dict { PACKAGE_PIN Y28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[5] }]; #IO_L3P_T0_DQS_13 Sch=prog_d[5] +#set_property -dict { PACKAGE_PIN AA28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[6] }]; #IO_L3N_T0_DQS_13 Sch=prog_d[6] +#set_property -dict { PACKAGE_PIN AA26 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[7] }]; #IO_L1N_T0_13 Sch=prog_d[7] +#set_property -dict { PACKAGE_PIN AC30 IOSTANDARD LVCMOS33 } [get_ports { PROG_OEN }]; #IO_L7N_T1_13 Sch=prog_oen +#set_property -dict { PACKAGE_PIN AB25 IOSTANDARD LVCMOS33 } [get_ports { PROG_RDN }]; #IO_L6N_T0_VREF_13 Sch=prog_rdn +#set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 } [get_ports { PROG_RXFN }]; #IO_L10P_T1_13 Sch=prog_rxfn +#set_property -dict { PACKAGE_PIN AB28 IOSTANDARD LVCMOS33 } [get_ports { PROG_SIWUN }]; #IO_L5N_T0_13 Sch=prog_siwun +#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien +#set_property -dict { PACKAGE_PIN AA25 IOSTANDARD LVCMOS33 } [get_ports { PROG_TXEN }]; #IO_L6P_T0_13 Sch=prog_txen +#set_property -dict { PACKAGE_PIN AC27 IOSTANDARD LVCMOS33 } [get_ports { PROG_WRN }]; #IO_L12N_T1_MRCC_13 Sch=prog_wrn + +## DSPI +## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins. +#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien +#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { PROG_SCK }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck +#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { PROG_MOSI }]; #IO_L2P_T0_13 Sch=prog_d1/mosi +#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { PROG_MISO }]; #IO_L2N_T0_13 Sch=prog_d2/miso +#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SS }]; #IO_L4P_T0_13 Sch=prog_d3/ss + +## QSPI +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn +#set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0] +#set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1] +#set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2] +#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3] + +## IIC Bus +set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { i2c_scl_io }]; #IO_L16P_T2_13 Sch=sys_scl +set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { i2c_sda_io }]; #IO_L16N_T2_13 Sch=sys_sda + +## Display Port IN +#set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_N }]; #IO_L17N_T2_32 Sch=rx_aux_ch_n +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_N }]; #IO_L15N_T2_DQS_32 Sch=rx_aux_ch_n +#set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_P }]; #IO_L17P_T2_32 Sch=rx_aux_ch_p +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_P }]; #IO_L15P_T2_DQS_32 Sch=rx_aux_ch_p +#set_property -dict { PACKAGE_PIN AE21 IOSTANDARD LVCMOS33 } [get_ports { RX_HPD }]; #IO_L10N_T1_12 Sch=rx_hpd + +## Display Port OUT +#set_property -dict { PACKAGE_PIN AD16 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_N }]; #IO_L14N_T2_SRCC_32 Sch=tx_aux_ch_n +#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_N }]; #IO_L16N_T2_32 Sch=tx_aux_ch_n +#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_P }]; #IO_L16P_T2_32 Sch=tx_aux_ch_p +#set_property -dict { PACKAGE_PIN AD17 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_P }]; #IO_L14P_T2_SRCC_32 Sch=tx_aux_ch_p +#set_property -dict { PACKAGE_PIN AD21 IOSTANDARD LVCMOS33 } [get_ports { TX_HPD }]; #IO_L10P_T1_12 Sch=tx_hpd + +## USB +#set_property -dict { PACKAGE_PIN AD18 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_CLK }]; #IO_L13P_T2_MRCC_32 Sch=usb_otg_clk +#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[0] }]; #IO_L19N_T3_VREF_32 Sch=usb_otg_d[0] +#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[1] }]; #IO_L19P_T3_32 Sch=usb_otg_d[1] +#set_property -dict { PACKAGE_PIN AC15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[2] }]; #IO_L21N_T3_DQS_32 Sch=usb_otg_d[2] +#set_property -dict { PACKAGE_PIN AC16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[3] }]; #IO_L21P_T3_DQS_32 Sch=usb_otg_d[3] +#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[4] }]; #IO_L20N_T3_32 Sch=usb_otg_d[4] +#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[5] }]; #IO_L20P_T3_32 Sch=usb_otg_d[5] +#set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[6] }]; #IO_L22N_T3_32 Sch=usb_otg_d[6] +#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[7] }]; #IO_L22P_T3_32 Sch=usb_otg_d[7] +#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_DIR }]; #IO_L24P_T3_32 Sch=usb_otg_dir +#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_NXT }]; #IO_L23N_T3_32 Sch=usb_otg_nxt +#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_RESETB }]; #IO_25_VRP_32 Sch=usb_otg_resetb +#set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_STP }]; #IO_L23P_T3_32 Sch=usb_otg_stp +#set_property -dict { PACKAGE_PIN AF16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_VBUSOC }]; #IO_L6N_T0_VREF_32 Sch=usb_otg_vbusoc diff --git a/target/xilinx/flavor_vanilla/constraints/vcu128.xdc b/target/xilinx/flavor_vanilla/constraints/vcu128.xdc new file mode 100644 index 00000000..a55db78d --- /dev/null +++ b/target/xilinx/flavor_vanilla/constraints/vcu128.xdc @@ -0,0 +1,1810 @@ +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +############# +# Sys clock # +############# + +# 100 MHz ref clock +set SYS_TCK 10 +create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] + +############# +# Mig clock # +############# + +# Dram axi clock : 750ps * 4 +set MIG_TCK 3 +create_generated_clock -source [get_pins i_dram_wrapper/i_dram/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0] \ + -divide_by 1 -add -master_clock mmcm_clkout0 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +# Aynch reset in +set MIG_RST_I [get_pin i_dram_wrapper/i_dram/inst/c0_ddr4_aresetn] +set_false_path -hold -setup -through $MIG_RST_I +# Synch reset out +set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +set_false_path -hold -through $MIG_RST_O +set_max_delay -through $MIG_RST_O $MIG_TCK + +######## +# CDCs # +######## + +set_max_delay -datapath \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK + +set_max_delay -datapath \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK + +################################################################################# + +############### +# ASSIGN PINS # +############### + +# VCU128 Rev1.0 XDC +# Date: 01/24/2018 + +#### This file is a general .xdc for the VCU128 1 Rev. +#### To use it in a project: +#### - uncomment the lines corresponding to used pins +#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + + +#set_property PACKAGE_PIN BF21 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L24N_T3U_N11_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L24N_T3U_N11_67 +#set_property PACKAGE_PIN BF22 [get_ports "ENET_PDWN_B_I_INT_B_O"] ;# Bank 67 VCCO - VCC1V8 - IO_L24P_T3U_N10_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_PDWN_B_I_INT_B_O"] ;# Bank 67 VCCO - VCC1V8 - IO_L24P_T3U_N10_67 +#set_property PACKAGE_PIN BH22 [get_ports "ENET_SGMII_IN_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L23N_T3U_N9_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_IN_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L23N_T3U_N9_67 +#set_property PACKAGE_PIN BG22 [get_ports "ENET_SGMII_IN_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L23P_T3U_N8_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_IN_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L23P_T3U_N8_67 +#set_property PACKAGE_PIN BJ21 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_67 +#set_property PACKAGE_PIN BH21 [get_ports "QSFP4_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_67 +#set_property PACKAGE_PIN BK21 [get_ports "ENET_SGMII_OUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_OUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67 +#set_property PACKAGE_PIN BJ22 [get_ports "ENET_SGMII_OUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_OUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67 +#set_property PACKAGE_PIN BK23 [get_ports "QSFP4_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_67 +#set_property PACKAGE_PIN BK24 [get_ports "QSFP4_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_67 +#set_property PACKAGE_PIN BL22 [get_ports "QSFP4_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_67 +#set_property PACKAGE_PIN BL23 [get_ports "DUMMY_NC"] ;# Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "DUMMY_NC"] ;# Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 +#set_property PACKAGE_PIN BG23 [get_ports "ENET_MDIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T3U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_MDIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T3U_N12_67 +#set_property PACKAGE_PIN BF23 [get_ports "QSFP4_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_T2U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_T2U_N12_67 +#set_property PACKAGE_PIN BH24 [get_ports "GPIO_LED_0_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_0_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_67 +#set_property PACKAGE_PIN BG24 [get_ports "GPIO_LED_1_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_1_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_67 +#set_property PACKAGE_PIN BG25 [get_ports "GPIO_LED_2_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_2_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_67 +#set_property PACKAGE_PIN BF25 [get_ports "GPIO_LED_3_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_3_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_67 +#set_property PACKAGE_PIN BF26 [get_ports "GPIO_LED_4_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_4_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_67 +#set_property PACKAGE_PIN BF27 [get_ports "GPIO_LED_5_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_5_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_67 +#set_property PACKAGE_PIN BG27 [get_ports "GPIO_LED_6_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_6_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_67 +#set_property PACKAGE_PIN BG28 [get_ports "GPIO_LED_7_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_7_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_67 +#set_property PACKAGE_PIN BJ23 [get_ports "ENET_CLKOUT"] ;# Bank 67 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_CLKOUT"] ;# Bank 67 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_67 +#set_property PACKAGE_PIN BJ24 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_67 +#set_property PACKAGE_PIN BH25 [get_ports "QSFP1_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_67 +#set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_67 +#set_property PACKAGE_PIN BH26 [get_ports "QSFP1_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +#set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +#set_property PACKAGE_PIN BJ27 [get_ports "ENET_SGMII_CLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_CLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67 +#set_property PACKAGE_PIN BH27 [get_ports "ENET_SGMII_CLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_67 +#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_CLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_67 +#set_property PACKAGE_PIN BK25 [get_ports "QSFP2_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_67 +#set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_67 +#set_property PACKAGE_PIN BJ26 [get_ports "QSFP2_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_67 +#set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_67 +#set_property PACKAGE_PIN BL25 [get_ports "SMA_CLK_OUTPUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_67 +#set_property IOSTANDARD LVDS [get_ports "SMA_CLK_OUTPUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_67 +#set_property PACKAGE_PIN BK26 [get_ports "SMA_CLK_OUTPUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_67 +#set_property IOSTANDARD LVDS [get_ports "SMA_CLK_OUTPUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_67 +#set_property PACKAGE_PIN BK28 [get_ports "UART1_RXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_RXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_67 +#set_property PACKAGE_PIN BJ28 [get_ports "UART1_TXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_TXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_67 +#set_property PACKAGE_PIN BL26 [get_ports "UART1_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_67 +#set_property PACKAGE_PIN BL27 [get_ports "UART1_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_67 +#set_property PACKAGE_PIN BM27 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_67 +#set_property PACKAGE_PIN BL28 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_67 +#set_property PACKAGE_PIN BN27 [get_ports "ENET_MDC"] ;# Bank 67 VCCO - VCC1V8 - IO_T1U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_MDC"] ;# Bank 67 VCCO - VCC1V8 - IO_T1U_N12_67 +#set_property PACKAGE_PIN BP27 [get_ports "ENET_COL_GPIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T0U_N12_VRP_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_COL_GPIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T0U_N12_VRP_67 +#set_property PACKAGE_PIN BN22 [get_ports "SYSCTLR_UCA1_TX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_UCA1_TX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_67 +#set_property PACKAGE_PIN BM22 [get_ports "SYSCTLR_UCA1_RX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_UCA1_RX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_67 +#set_property PACKAGE_PIN BM23 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_67 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_67 +#set_property PACKAGE_PIN BM24 [get_ports "QSFP1_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_67 +#set_property PACKAGE_PIN BN25 [get_ports "QSFP1_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_67 +#set_property PACKAGE_PIN BM25 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_67 +#set_property PACKAGE_PIN BP24 [get_ports "QSFP1_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_67 +#set_property PACKAGE_PIN BN24 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_67 +set_property PACKAGE_PIN BP26 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property PACKAGE_PIN BN26 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +#set_property PACKAGE_PIN BP22 [get_ports "UART0_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART0_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_67 +#set_property PACKAGE_PIN BP23 [get_ports "UART0_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "UART0_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_67 +#set_property PACKAGE_PIN BE51 [get_ports "PL_DDR4_A5"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A5"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_66 +#set_property PACKAGE_PIN BD51 [get_ports "PL_DDR4_A1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_66 +#set_property PACKAGE_PIN BE50 [get_ports "PL_DDR4_A3"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A3"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_66 +#set_property PACKAGE_PIN BE49 [get_ports "PL_DDR4_A4"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A4"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_66 +#set_property PACKAGE_PIN BF48 [get_ports "PL_DDR4_A12"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A12"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_66 +#set_property PACKAGE_PIN BF47 [get_ports "PL_DDR4_A10"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A10"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_66 +#set_property PACKAGE_PIN BF52 [get_ports "PL_DDR4_A13"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A13"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_66 +#set_property PACKAGE_PIN BF51 [get_ports "PL_DDR4_A8"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A8"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_66 +#set_property PACKAGE_PIN BG50 [get_ports "PL_DDR4_A7"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A7"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_66 +#set_property PACKAGE_PIN BF50 [get_ports "PL_DDR4_A0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_66 +#set_property PACKAGE_PIN BG49 [get_ports "PL_DDR4_A11"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A11"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_66 +#set_property PACKAGE_PIN BG48 [get_ports "PL_DDR4_A2"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A2"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_66 +#set_property PACKAGE_PIN BG47 [get_ports "PL_DDR4_A9"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A9"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_66 +#set_property PACKAGE_PIN BF53 [get_ports "PL_DDR4_A6"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A6"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_66 +#set_property PACKAGE_PIN BE54 [get_ports "PL_DDR4_BA0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BA0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_66 +#set_property PACKAGE_PIN BE53 [get_ports "PL_DDR4_BA1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BA1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_66 +#set_property PACKAGE_PIN BG54 [get_ports "PL_DDR4_BG0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BG0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_66 +#set_property PACKAGE_PIN BG53 [get_ports "PL_DDR4_WE_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_WE_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_66 +#set_property PACKAGE_PIN BJ54 [get_ports "PL_DDR4_RAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_RAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_66 +#set_property PACKAGE_PIN BH54 [get_ports "PL_DDR4_CAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_CAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_66 +#set_property PACKAGE_PIN BK54 [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_66 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_66 +#set_property PACKAGE_PIN BK53 [get_ports "c0_sys_clk_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_66 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_sys_clk_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_66 +#set_property PACKAGE_PIN BH52 [get_ports "PL_DDR4_CKE"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_CKE"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_66 +#set_property PACKAGE_PIN BG52 [get_ports "c0_ddr4_act_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_act_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_66 +#set_property PACKAGE_PIN BJ53 [get_ports "PL_DDR4_TEN"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_TEN"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_66 +#set_property PACKAGE_PIN BJ52 [get_ports "PL_DDR4_ALERT_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_ALERT_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_66 +#set_property PACKAGE_PIN BH50 [get_ports "PL_DDR4_RE#set_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_66 +#set_property IOSTANDARD LVCMOS12 [get_ports "PL_DDR4_RE#set_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_66 +#set_property PACKAGE_PIN BH49 [get_ports "PL_DDR4_ODT"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_ODT"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_66 +#set_property PACKAGE_PIN BJ51 [get_ports "DDR4_CLK_100MHZ_N"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_66 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CLK_100MHZ_N"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_66 +#set_property PACKAGE_PIN BH51 [get_ports "DDR4_CLK_100MHZ_P"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_66 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CLK_100MHZ_P"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_66 +#set_property PACKAGE_PIN BJ47 [get_ports "SYSCTLR_GPIO_0_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_66 +#set_property IOSTANDARD LVCMOS12 [get_ports "SYSCTLR_GPIO_0_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_66 +#set_property PACKAGE_PIN BH47 [get_ports "SYSCTLR_GPIO_1_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_66 +#set_property IOSTANDARD LVCMOS12 [get_ports "SYSCTLR_GPIO_1_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_66 +#set_property PACKAGE_PIN BJ49 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_66 +#set_property PACKAGE_PIN BJ48 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_66 +#set_property PACKAGE_PIN BK51 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_66 +#set_property PACKAGE_PIN BK50 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_66 +#set_property PACKAGE_PIN BK49 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_66 +#set_property PACKAGE_PIN BK48 [get_ports "PL_DDR4_BOT_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BOT_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_66 +#set_property PACKAGE_PIN BL48 [get_ports "PL_DDR4_PARITY"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_66 +#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_PARITY"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_66 +#set_property PACKAGE_PIN BL50 [get_ports "VRP_66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_66 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_66 +#set_property PACKAGE_PIN BL53 [get_ports "PL_DDR4_DQ69"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ69"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_66 +#set_property PACKAGE_PIN BL52 [get_ports "PL_DDR4_DQ67"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ67"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_66 +#set_property PACKAGE_PIN BM52 [get_ports "PL_DDR4_DQ65"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ65"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_66 +#set_property PACKAGE_PIN BL51 [get_ports "PL_DDR4_DQ71"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ71"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_66 +#set_property PACKAGE_PIN BM50 [get_ports "PL_DDR4_DQS8_C"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_66 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS8_C"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_66 +#set_property PACKAGE_PIN BM49 [get_ports "PL_DDR4_DQS8_T"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_66 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS8_T"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_66 +#set_property PACKAGE_PIN BN49 [get_ports "PL_DDR4_DQ70"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ70"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_66 +#set_property PACKAGE_PIN BM48 [get_ports "PL_DDR4_DQ68"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ68"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_66 +#set_property PACKAGE_PIN BN51 [get_ports "PL_DDR4_DQ64"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ64"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_66 +#set_property PACKAGE_PIN BN50 [get_ports "PL_DDR4_DQ66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_66 +#set_property PACKAGE_PIN BP49 [get_ports "PL_DDR4_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_66 +#set_property IOSTANDARD SSTL12 [get_ports "PL_DDR4_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_66 +#set_property PACKAGE_PIN BP48 [get_ports "PL_DDR4_DM8_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_66 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM8_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_66 +#set_property PACKAGE_PIN BE44 [get_ports "PL_DDR4_DQ30"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_DOUT_CSO_B_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ30"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_DOUT_CSO_B_65 +#set_property PACKAGE_PIN BE43 [get_ports "PL_DDR4_DQ24"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_EMCCLK_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ24"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_EMCCLK_65 +#set_property PACKAGE_PIN BD42 [get_ports "PL_DDR4_DQ28"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ28"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +#set_property PACKAGE_PIN BC42 [get_ports "PL_DDR4_DQ26"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ26"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property PACKAGE_PIN BE46 [get_ports "PL_DDR4_DQS3_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS3_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property PACKAGE_PIN BE45 [get_ports "PL_DDR4_DQS3_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS3_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property PACKAGE_PIN BF43 [get_ports "PL_DDR4_DQ27"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_D07_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ27"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_D07_65 +#set_property PACKAGE_PIN BF42 [get_ports "PL_DDR4_DQ25"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_D06_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ25"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_D06_65 +#set_property PACKAGE_PIN BF46 [get_ports "PL_DDR4_DQ31"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_D09_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ31"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_D09_65 +#set_property PACKAGE_PIN BF45 [get_ports "PL_DDR4_DQ29"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_D08_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ29"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_D08_65 +#set_property PACKAGE_PIN BE41 [get_ports "SYSMON_SDA_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +#set_property IOSTANDARD LVCMOS12 [get_ports "SYSMON_SDA_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +#set_property PACKAGE_PIN BD41 [get_ports "PL_DDR4_DM3_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM3_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +#set_property PACKAGE_PIN BF41 [get_ports "PCIE_EP_PERST_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_PERSTN0_65 +#set_property IOSTANDARD LVCMOS12 [get_ports "PCIE_EP_PERST_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_PERSTN0_65 +#set_property PACKAGE_PIN BH41 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_CSI_ADV_B_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_CSI_ADV_B_65 +#set_property PACKAGE_PIN BG45 [get_ports "PL_DDR4_DQ21"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_D13_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ21"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_D13_65 +#set_property PACKAGE_PIN BG44 [get_ports "PL_DDR4_DQ17"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_D12_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ17"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_D12_65 +#set_property PACKAGE_PIN BG43 [get_ports "PL_DDR4_DQ22"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_D15_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ22"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_D15_65 +#set_property PACKAGE_PIN BG42 [get_ports "PL_DDR4_DQ18"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_D14_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ18"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_D14_65 +#set_property PACKAGE_PIN BJ46 [get_ports "PL_DDR4_DQS2_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS2_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +#set_property PACKAGE_PIN BH46 [get_ports "PL_DDR4_DQS2_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS2_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property PACKAGE_PIN BK41 [get_ports "PL_DDR4_DQ16"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ16"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property PACKAGE_PIN BJ41 [get_ports "PL_DDR4_DQ23"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_A02_D18_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ23"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_A02_D18_65 +#set_property PACKAGE_PIN BH45 [get_ports "PL_DDR4_DQ20"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_A05_D21_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ20"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_A05_D21_65 +#set_property PACKAGE_PIN BH44 [get_ports "PL_DDR4_DQ19"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_A04_D20_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ19"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_A04_D20_65 +#set_property PACKAGE_PIN BJ42 [get_ports "PCIE_EP_WAKE_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +#set_property IOSTANDARD LVCMOS12 [get_ports "PCIE_EP_WAKE_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +#set_property PACKAGE_PIN BH42 [get_ports "PL_DDR4_DM2_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM2_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +#set_property PACKAGE_PIN BJ44 [get_ports "PL_DDR4_DQ13"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_A09_D25_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ13"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_A09_D25_65 +#set_property PACKAGE_PIN BJ43 [get_ports "PL_DDR4_DQ15"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_A08_D24_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ15"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_A08_D24_65 +#set_property PACKAGE_PIN BK44 [get_ports "PL_DDR4_DQ9"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_A11_D27_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ9"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_A11_D27_65 +#set_property PACKAGE_PIN BK43 [get_ports "PL_DDR4_DQ11"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_A10_D26_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ11"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_A10_D26_65 +#set_property PACKAGE_PIN BK46 [get_ports "PL_DDR4_DQS1_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS1_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +#set_property PACKAGE_PIN BK45 [get_ports "PL_DDR4_DQS1_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS1_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +#set_property PACKAGE_PIN BL43 [get_ports "PL_DDR4_DQ12"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_A15_D31_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ12"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_A15_D31_65 +#set_property PACKAGE_PIN BL42 [get_ports "PL_DDR4_DQ14"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_A14_D30_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ14"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_A14_D30_65 +#set_property PACKAGE_PIN BL46 [get_ports "PL_DDR4_DQ10"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_A17_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ10"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_A17_65 +#set_property PACKAGE_PIN BL45 [get_ports "PL_DDR4_DQ8"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_A16_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ8"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_A16_65 +#set_property PACKAGE_PIN BM47 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +#set_property PACKAGE_PIN BL47 [get_ports "PL_DDR4_DM1_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM1_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +#set_property PACKAGE_PIN BM42 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_SMBALERT_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_SMBALERT_65 +#set_property PACKAGE_PIN BM43 [get_ports "VRP_65"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_A28_65 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_A28_65 +#set_property PACKAGE_PIN BN45 [get_ports "PL_DDR4_DQ3"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_A21_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ3"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_A21_65 +#set_property PACKAGE_PIN BM45 [get_ports "PL_DDR4_DQ0"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_A20_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ0"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_A20_65 +#set_property PACKAGE_PIN BN44 [get_ports "PL_DDR4_DQ5"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_A23_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ5"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_A23_65 +#set_property PACKAGE_PIN BM44 [get_ports "PL_DDR4_DQ4"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_A22_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ4"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_A22_65 +#set_property PACKAGE_PIN BP46 [get_ports "PL_DDR4_DQS0_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS0_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +#set_property PACKAGE_PIN BN46 [get_ports "PL_DDR4_DQS0_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS0_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +#set_property PACKAGE_PIN BP44 [get_ports "PL_DDR4_DQ1"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_A27_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ1"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_A27_65 +#set_property PACKAGE_PIN BP43 [get_ports "PL_DDR4_DQ7"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_A26_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ7"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_A26_65 +#set_property PACKAGE_PIN BP47 [get_ports "PL_DDR4_DQ2"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_FWE_FCS2_B_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ2"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_FWE_FCS2_B_65 +#set_property PACKAGE_PIN BN47 [get_ports "PL_DDR4_DQ6"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_FOE_B_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ6"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_FOE_B_65 +#set_property PACKAGE_PIN BP42 [get_ports "SYSMON_SCL_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_RS1_65 +#set_property IOSTANDARD LVCMOS12 [get_ports "SYSMON_SCL_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_RS1_65 +#set_property PACKAGE_PIN BN42 [get_ports "PL_DDR4_DM0_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_RS0_65 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM0_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_RS0_65 +#set_property PACKAGE_PIN BJ31 [get_ports "PL_DDR4_DQ58"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ58"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_64 +#set_property PACKAGE_PIN BH31 [get_ports "PL_DDR4_DQ60"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ60"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_64 +#set_property PACKAGE_PIN BF33 [get_ports "PL_DDR4_DQ63"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ63"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_64 +#set_property PACKAGE_PIN BF32 [get_ports "PL_DDR4_DQ61"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ61"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_64 +#set_property PACKAGE_PIN BK30 [get_ports "PL_DDR4_DQS7_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS7_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 +#set_property PACKAGE_PIN BJ29 [get_ports "PL_DDR4_DQS7_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS7_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 +#set_property PACKAGE_PIN BG32 [get_ports "PL_DDR4_DQ59"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ59"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_64 +#set_property PACKAGE_PIN BF31 [get_ports "PL_DDR4_DQ56"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ56"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_64 +#set_property PACKAGE_PIN BH30 [get_ports "PL_DDR4_DQ57"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ57"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_64 +#set_property PACKAGE_PIN BH29 [get_ports "PL_DDR4_DQ62"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ62"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_64 +#set_property PACKAGE_PIN BG30 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 +#set_property PACKAGE_PIN BG29 [get_ports "PL_DDR4_DM7_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM7_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 +#set_property PACKAGE_PIN BK29 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_64 +#set_property PACKAGE_PIN BG33 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_64 +#set_property PACKAGE_PIN BH35 [get_ports "PL_DDR4_DQ51"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ51"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_64 +#set_property PACKAGE_PIN BH34 [get_ports "PL_DDR4_DQ50"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ50"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_64 +#set_property PACKAGE_PIN BF36 [get_ports "PL_DDR4_DQ55"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ55"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_64 +#set_property PACKAGE_PIN BF35 [get_ports "PL_DDR4_DQ53"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ53"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_64 +#set_property PACKAGE_PIN BK35 [get_ports "PL_DDR4_DQS6_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS6_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 +#set_property PACKAGE_PIN BK34 [get_ports "PL_DDR4_DQS6_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS6_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 +#set_property PACKAGE_PIN BG35 [get_ports "PL_DDR4_DQ49"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ49"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_64 +#set_property PACKAGE_PIN BG34 [get_ports "PL_DDR4_DQ54"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ54"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_64 +#set_property PACKAGE_PIN BJ34 [get_ports "PL_DDR4_DQ48"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ48"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_64 +#set_property PACKAGE_PIN BJ33 [get_ports "PL_DDR4_DQ52"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ52"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_64 +#set_property PACKAGE_PIN BJ32 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_64 +#set_property PACKAGE_PIN BH32 [get_ports "PL_DDR4_DM6_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM6_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_64 +#set_property PACKAGE_PIN BL33 [get_ports "PL_DDR4_DQ45"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ45"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_64 +#set_property PACKAGE_PIN BK33 [get_ports "PL_DDR4_DQ43"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ43"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_64 +#set_property PACKAGE_PIN BL31 [get_ports "PL_DDR4_DQ44"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ44"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_64 +#set_property PACKAGE_PIN BK31 [get_ports "PL_DDR4_DQ47"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ47"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_64 +#set_property PACKAGE_PIN BM35 [get_ports "PL_DDR4_DQS5_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS5_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 +#set_property PACKAGE_PIN BL35 [get_ports "PL_DDR4_DQS5_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS5_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 +#set_property PACKAGE_PIN BM33 [get_ports "PL_DDR4_DQ46"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ46"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_64 +#set_property PACKAGE_PIN BL32 [get_ports "PL_DDR4_DQ40"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ40"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_64 +#set_property PACKAGE_PIN BP34 [get_ports "PL_DDR4_DQ41"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ41"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_64 +#set_property PACKAGE_PIN BN34 [get_ports "PL_DDR4_DQ42"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ42"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_64 +#set_property PACKAGE_PIN BN35 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 +#set_property PACKAGE_PIN BM34 [get_ports "PL_DDR4_DM5_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM5_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 +#set_property PACKAGE_PIN BP33 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_64 +#set_property PACKAGE_PIN BM32 [get_ports "VRP_64"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_64 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_64"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_64 +#set_property PACKAGE_PIN BP32 [get_ports "PL_DDR4_DQ32"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ32"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_64 +#set_property PACKAGE_PIN BN32 [get_ports "PL_DDR4_DQ36"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ36"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_64 +#set_property PACKAGE_PIN BM30 [get_ports "PL_DDR4_DQ37"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ37"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_64 +#set_property PACKAGE_PIN BL30 [get_ports "PL_DDR4_DQ39"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ39"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_64 +#set_property PACKAGE_PIN BN30 [get_ports "PL_DDR4_DQS4_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS4_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 +#set_property PACKAGE_PIN BN29 [get_ports "PL_DDR4_DQS4_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS4_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 +#set_property PACKAGE_PIN BP31 [get_ports "PL_DDR4_DQ34"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ34"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_64 +#set_property PACKAGE_PIN BN31 [get_ports "PL_DDR4_DQ38"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ38"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_64 +#set_property PACKAGE_PIN BP29 [get_ports "PL_DDR4_DQ33"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ33"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_64 +#set_property PACKAGE_PIN BP28 [get_ports "PL_DDR4_DQ35"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ35"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_64 +set_property PACKAGE_PIN BM29 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] +#set_property PACKAGE_PIN BM28 [get_ports "PL_DDR4_DM4_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_64 +#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM4_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_64 +#set_property PACKAGE_PIN A16 [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 +#set_property PACKAGE_PIN B16 [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 71 VCCO - VADJ - IO_L24P_T3U_N10_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 71 VCCO - VADJ - IO_L24P_T3U_N10_71 +#set_property PACKAGE_PIN A18 [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 71 VCCO - VADJ - IO_L23N_T3U_N9_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 71 VCCO - VADJ - IO_L23N_T3U_N9_71 +#set_property PACKAGE_PIN A19 [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 71 VCCO - VADJ - IO_L23P_T3U_N8_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 71 VCCO - VADJ - IO_L23P_T3U_N8_71 +#set_property PACKAGE_PIN A20 [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71 +#set_property PACKAGE_PIN A21 [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 +#set_property PACKAGE_PIN B17 [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 71 VCCO - VADJ - IO_L21N_T3L_N5_AD8N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 71 VCCO - VADJ - IO_L21N_T3L_N5_AD8N_71 +#set_property PACKAGE_PIN B18 [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 71 VCCO - VADJ - IO_L21P_T3L_N4_AD8P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 71 VCCO - VADJ - IO_L21P_T3L_N4_AD8P_71 +#set_property PACKAGE_PIN B20 [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 71 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 71 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_71 +#set_property PACKAGE_PIN B21 [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 71 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 71 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_71 +#set_property PACKAGE_PIN C17 [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 71 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 71 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_71 +#set_property PACKAGE_PIN C18 [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 71 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 71 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_71 +#set_property PACKAGE_PIN C19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T3U_N12_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T3U_N12_71 +#set_property PACKAGE_PIN C20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T2U_N12_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T2U_N12_71 +#set_property PACKAGE_PIN D19 [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 71 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 71 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_71 +#set_property PACKAGE_PIN D20 [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 +#set_property PACKAGE_PIN D16 [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 71 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 71 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_71 +#set_property PACKAGE_PIN D17 [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 71 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 71 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_71 +#set_property PACKAGE_PIN D21 [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 71 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 71 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_71 +#set_property PACKAGE_PIN E21 [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 71 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 71 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_71 +#set_property PACKAGE_PIN E16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_71 +#set_property PACKAGE_PIN F16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_71 +#set_property PACKAGE_PIN E18 [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L14N_T2L_N3_GC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L14N_T2L_N3_GC_71 +#set_property PACKAGE_PIN E19 [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L14P_T2L_N2_GC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L14P_T2L_N2_GC_71 +#set_property PACKAGE_PIN E17 [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_71 +#set_property PACKAGE_PIN F18 [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_71 +#set_property PACKAGE_PIN F19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12N_T1U_N11_GC_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12N_T1U_N11_GC_71 +#set_property PACKAGE_PIN F20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12P_T1U_N10_GC_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12P_T1U_N10_GC_71 +#set_property PACKAGE_PIN G17 [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 71 VCCO - VADJ - IO_L11N_T1U_N9_GC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 71 VCCO - VADJ - IO_L11N_T1U_N9_GC_71 +#set_property PACKAGE_PIN G18 [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 71 VCCO - VADJ - IO_L11P_T1U_N8_GC_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 71 VCCO - VADJ - IO_L11P_T1U_N8_GC_71 +#set_property PACKAGE_PIN F21 [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 71 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 71 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_71 +#set_property PACKAGE_PIN G21 [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 71 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 71 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_71 +#set_property PACKAGE_PIN H18 [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 71 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 71 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_71 +#set_property PACKAGE_PIN H19 [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 71 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 71 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_71 +#set_property PACKAGE_PIN G20 [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 71 VCCO - VADJ - IO_L8N_T1L_N3_AD5N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 71 VCCO - VADJ - IO_L8N_T1L_N3_AD5N_71 +#set_property PACKAGE_PIN H20 [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 71 VCCO - VADJ - IO_L8P_T1L_N2_AD5P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 71 VCCO - VADJ - IO_L8P_T1L_N2_AD5P_71 +#set_property PACKAGE_PIN G16 [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 71 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 71 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_71 +#set_property PACKAGE_PIN H17 [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 71 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 71 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_71 +#set_property PACKAGE_PIN J16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T1U_N12_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T1U_N12_71 +#set_property PACKAGE_PIN J17 [get_ports "VRP_71"] ;# Bank 71 VCCO - VADJ - IO_T0U_N12_VRP_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_71"] ;# Bank 71 VCCO - VADJ - IO_T0U_N12_VRP_71 +#set_property PACKAGE_PIN J19 [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 71 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 71 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_71 +#set_property PACKAGE_PIN J20 [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 71 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 71 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_71 +#set_property PACKAGE_PIN J21 [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 71 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 71 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_71 +#set_property PACKAGE_PIN K21 [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 71 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_71 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 71 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_71 +#set_property PACKAGE_PIN K18 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_71 +#set_property PACKAGE_PIN K19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_71 +#set_property PACKAGE_PIN L20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_71 +#set_property PACKAGE_PIN L21 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_71 +#set_property PACKAGE_PIN L18 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2N_T0L_N3_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2N_T0L_N3_71 +#set_property PACKAGE_PIN L19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2P_T0L_N2_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2P_T0L_N2_71 +#set_property PACKAGE_PIN K16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1N_T0L_N1_DBC_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1N_T0L_N1_DBC_71 +#set_property PACKAGE_PIN K17 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1P_T0L_N0_DBC_71 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1P_T0L_N0_DBC_71 +#set_property PACKAGE_PIN A8 [get_ports "QDR4_DQB31"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB31"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_70 +#set_property PACKAGE_PIN A9 [get_ports "QDR4_DQB32"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB32"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_70 +#set_property PACKAGE_PIN A10 [get_ports "QDR4_DQB35"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB35"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_70 +#set_property PACKAGE_PIN A11 [get_ports "QDR4_DQB28"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB28"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_70 +#set_property PACKAGE_PIN A13 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_70 +#set_property PACKAGE_PIN B13 [get_ports "QDR4_DQB29"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB29"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_70 +#set_property PACKAGE_PIN B12 [get_ports "QDR4_DQB30"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB30"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_70 +#set_property PACKAGE_PIN C12 [get_ports "QDR4_DQB27"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB27"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_70 +#set_property PACKAGE_PIN B10 [get_ports "QDR4_DQB34"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB34"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_70 +#set_property PACKAGE_PIN B11 [get_ports "QDR4_DQB33"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB33"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_70 +#set_property PACKAGE_PIN C9 [get_ports "QDR4_DKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_70 +#set_property PACKAGE_PIN C10 [get_ports "QDR4_DKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_70 +#set_property PACKAGE_PIN C13 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_70 +#set_property PACKAGE_PIN C14 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_70 +#set_property PACKAGE_PIN A14 [get_ports "QDR4_DQB19"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB19"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_70 +#set_property PACKAGE_PIN A15 [get_ports "QDR4_DQB25"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB25"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_70 +#set_property PACKAGE_PIN B15 [get_ports "QDR4_DQB21"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB21"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_70 +#set_property PACKAGE_PIN C15 [get_ports "QDR4_DQB23"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB23"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_70 +#set_property PACKAGE_PIN D14 [get_ports "QDR4_QVLDB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_70 +#set_property PACKAGE_PIN D15 [get_ports "QDR4_DQB20"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB20"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_70 +#set_property PACKAGE_PIN E14 [get_ports "QDR4_DQB18"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB18"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_70 +#set_property PACKAGE_PIN F15 [get_ports "QDR4_DQB24"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB24"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_70 +#set_property PACKAGE_PIN F13 [get_ports "QDR4_DQB22"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB22"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_70 +#set_property PACKAGE_PIN F14 [get_ports "QDR4_DQB26"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB26"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_70 +#set_property PACKAGE_PIN D12 [get_ports "QDR4_QKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_70 +#set_property PACKAGE_PIN E13 [get_ports "QDR4_QKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_70 +#set_property PACKAGE_PIN E11 [get_ports "QDR4_DQB12"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB12"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_70 +#set_property PACKAGE_PIN F11 [get_ports "QDR4_DQB16"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB16"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_70 +#set_property PACKAGE_PIN D11 [get_ports "QDR4_DQB17"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB17"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_70 +#set_property PACKAGE_PIN E12 [get_ports "QDR4_DQB10"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB10"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_70 +#set_property PACKAGE_PIN D9 [get_ports "QDR4_QVLDB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_70 +#set_property PACKAGE_PIN D10 [get_ports "QDR4_DQB13"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB13"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_70 +#set_property PACKAGE_PIN E9 [get_ports "QDR4_DQB14"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB14"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_70 +#set_property PACKAGE_PIN F9 [get_ports "QDR4_DQB15"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB15"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_70 +#set_property PACKAGE_PIN F10 [get_ports "QDR4_DQB11"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB11"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_70 +#set_property PACKAGE_PIN G11 [get_ports "QDR4_DQB9"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB9"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_70 +#set_property PACKAGE_PIN G10 [get_ports "QDR4_QKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_70 +#set_property PACKAGE_PIN H10 [get_ports "QDR4_QKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_70 +#set_property PACKAGE_PIN H9 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_70 +#set_property PACKAGE_PIN G12 [get_ports "VRP_70"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_70"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_70 +#set_property PACKAGE_PIN G13 [get_ports "QDR4_DQB5"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB5"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_70 +#set_property PACKAGE_PIN H14 [get_ports "QDR4_DQB4"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB4"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_70 +#set_property PACKAGE_PIN H12 [get_ports "QDR4_DQB7"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB7"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_70 +#set_property PACKAGE_PIN H13 [get_ports "QDR4_DQB8"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB8"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_70 +#set_property PACKAGE_PIN G15 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_70 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_70 +#set_property PACKAGE_PIN H15 [get_ports "QDR4_DQB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_70 +#set_property PACKAGE_PIN J11 [get_ports "QDR4_DQB3"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB3"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_70 +#set_property PACKAGE_PIN J12 [get_ports "QDR4_DQB2"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB2"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_70 +#set_property PACKAGE_PIN J14 [get_ports "QDR4_DQB6"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB6"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_70 +#set_property PACKAGE_PIN J15 [get_ports "QDR4_DQB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_70 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_70 +#set_property PACKAGE_PIN K13 [get_ports "QDR4_DKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_70 +#set_property PACKAGE_PIN K14 [get_ports "QDR4_DKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_70 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_70 +#set_property PACKAGE_PIN BF1 [get_ports "QDR4_A1"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A1"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_69 +#set_property PACKAGE_PIN BE1 [get_ports "QDR4_A2"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A2"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_69 +#set_property PACKAGE_PIN BE3 [get_ports "QDR4_A3"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A3"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_69 +#set_property PACKAGE_PIN BE4 [get_ports "QDR4_A4"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A4"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_69 +#set_property PACKAGE_PIN BE5 [get_ports "QDR4_A5"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A5"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_69 +#set_property PACKAGE_PIN BE6 [get_ports "QDR4_A6"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A6"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_69 +#set_property PACKAGE_PIN BF2 [get_ports "QDR4_A7"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A7"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_69 +#set_property PACKAGE_PIN BF3 [get_ports "QDR4_A8"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A8"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_69 +#set_property PACKAGE_PIN BG2 [get_ports "QDR4_A9"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A9"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_69 +#set_property PACKAGE_PIN BG3 [get_ports "QDR4_A10"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A10"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_69 +#set_property PACKAGE_PIN BG4 [get_ports "QDR4_A11"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A11"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_69 +#set_property PACKAGE_PIN BG5 [get_ports "QDR4_A12"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A12"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_69 +#set_property PACKAGE_PIN BF5 [get_ports "QDR4_A0"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A0"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_69 +#set_property PACKAGE_PIN BF6 [get_ports "No Connect"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_69 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_69 +#set_property PACKAGE_PIN BF7 [get_ports "QDR4_A13"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A13"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_69 +#set_property PACKAGE_PIN BF8 [get_ports "QDR4_A14"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A14"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_69 +#set_property PACKAGE_PIN BG7 [get_ports "QDR4_A15"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A15"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_69 +#set_property PACKAGE_PIN BG8 [get_ports "QDR4_A16"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A16"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_69 +#set_property PACKAGE_PIN BJ7 [get_ports "QDR4_A17"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A17"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_69 +#set_property PACKAGE_PIN BH7 [get_ports "QDR4_A18"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A18"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_69 +#set_property PACKAGE_PIN BK8 [get_ports "QDR4_A19"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A19"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_69 +#set_property PACKAGE_PIN BJ8 [get_ports "QDR4_A20"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A20"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_69 +#set_property PACKAGE_PIN BH4 [get_ports "QDR4_CK_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_69 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_CK_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_69 +#set_property PACKAGE_PIN BH5 [get_ports "QDR4_CK_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_69 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_CK_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_69 +#set_property PACKAGE_PIN BJ6 [get_ports "QDR4_A21"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A21"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_69 +#set_property PACKAGE_PIN BH6 [get_ports "QDR4_A23"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A23"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_69 +#set_property PACKAGE_PIN BK4 [get_ports "QDR4_A24"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A24"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_69 +#set_property PACKAGE_PIN BK5 [get_ports "QDR4_A22"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A22"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_69 +#set_property PACKAGE_PIN BK3 [get_ports "QDR4_CLK_100MHZ_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_69 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "QDR4_CLK_100MHZ_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_69 +#set_property PACKAGE_PIN BJ4 [get_ports "QDR4_CLK_100MHZ_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_69 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "QDR4_CLK_100MHZ_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_69 +#set_property PACKAGE_PIN BJ2 [get_ports "QDR4_PE_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_PE_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_69 +#set_property PACKAGE_PIN BJ3 [get_ports "QDR4_LBK0_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LBK0_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_69 +#set_property PACKAGE_PIN BH1 [get_ports "QDR4_LBK1_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LBK1_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_69 +#set_property PACKAGE_PIN BH2 [get_ports "QDR4_CFG_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_CFG_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_69 +#set_property PACKAGE_PIN BK1 [get_ports "QDR4_RST_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QDR4_RST_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_69 +#set_property PACKAGE_PIN BJ1 [get_ports "QDR4_AINV"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_AINV"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_69 +#set_property PACKAGE_PIN BL2 [get_ports "QDR4_LDB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LDB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_69 +#set_property PACKAGE_PIN BL3 [get_ports "QDR4_RWB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_RWB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_69 +#set_property PACKAGE_PIN BK6 [get_ports "QDR4_AP"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_AP"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_69 +#set_property PACKAGE_PIN BL5 [get_ports "VRP_69"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_69 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_69"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_69 +#set_property PACKAGE_PIN BM3 [get_ports "QDR4_LDA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LDA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_69 +#set_property PACKAGE_PIN BM4 [get_ports "QDR4_RWA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_69 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_RWA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_69 +#set_property PACKAGE_PIN BM5 [get_ports "QSFP3_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_69 +#set_property PACKAGE_PIN BL6 [get_ports "QSFP3_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_69 +#set_property PACKAGE_PIN BM7 [get_ports "QSFP3_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_69 +#set_property PACKAGE_PIN BL7 [get_ports "QSFP3_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_69 +#set_property PACKAGE_PIN BN4 [get_ports "QSFP3_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_69 +#set_property PACKAGE_PIN BN5 [get_ports "QSFP2_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_69 +#set_property PACKAGE_PIN BN6 [get_ports "QSFP2_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_69 +#set_property PACKAGE_PIN BN7 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_69 +#set_property PACKAGE_PIN BP6 [get_ports "QSFP2_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_69 +#set_property PACKAGE_PIN BP7 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_69 +#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_69 +#set_property PACKAGE_PIN BE9 [get_ports "QDR4_DQA27"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA27"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_68 +#set_property PACKAGE_PIN BE10 [get_ports "QDR4_DQA28"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA28"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_68 +#set_property PACKAGE_PIN BF10 [get_ports "QDR4_DQA31"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA31"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_68 +#set_property PACKAGE_PIN BE11 [get_ports "QDR4_DQA30"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA30"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_68 +#set_property PACKAGE_PIN BF11 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_68 +#set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_68 +#set_property PACKAGE_PIN BF12 [get_ports "QDR4_DQA35"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA35"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_68 +#set_property PACKAGE_PIN BG9 [get_ports "QDR4_DQA33"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA33"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_68 +#set_property PACKAGE_PIN BG10 [get_ports "QDR4_DQA34"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA34"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_68 +#set_property PACKAGE_PIN BG12 [get_ports "QDR4_DQA32"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA32"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_68 +#set_property PACKAGE_PIN BG13 [get_ports "QDR4_DQA29"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA29"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_68 +#set_property PACKAGE_PIN BH9 [get_ports "QDR4_DKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_68 +#set_property PACKAGE_PIN BH10 [get_ports "QDR4_DKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_68 +#set_property PACKAGE_PIN BH11 [get_ports "PMBUS_ALERT_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_68 +#set_property IOSTANDARD LVCMOS12 [get_ports "PMBUS_ALERT_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_68 +#set_property PACKAGE_PIN BH12 [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_68 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_68 +#set_property PACKAGE_PIN BH14 [get_ports "QDR4_DQA23"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA23"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_68 +#set_property PACKAGE_PIN BH15 [get_ports "QDR4_DQA24"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA24"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_68 +#set_property PACKAGE_PIN BJ12 [get_ports "QDR4_DQA20"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA20"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_68 +#set_property PACKAGE_PIN BJ13 [get_ports "QDR4_DQA26"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA26"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_68 +#set_property PACKAGE_PIN BK13 [get_ports "QDR4_QVLDA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_68 +#set_property PACKAGE_PIN BJ14 [get_ports "QDR4_DQA25"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA25"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_68 +#set_property PACKAGE_PIN BK14 [get_ports "QDR4_DQA19"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA19"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_68 +#set_property PACKAGE_PIN BK15 [get_ports "QDR4_DQA21"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA21"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_68 +#set_property PACKAGE_PIN BL12 [get_ports "QDR4_DQA18"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA18"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_68 +#set_property PACKAGE_PIN BL13 [get_ports "QDR4_DQA22"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA22"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_68 +#set_property PACKAGE_PIN BK11 [get_ports "QDR4_QKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_68 +#set_property PACKAGE_PIN BJ11 [get_ports "QDR4_QKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_68 +#set_property PACKAGE_PIN BK9 [get_ports "QDR4_DQA10"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA10"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_68 +#set_property PACKAGE_PIN BJ9 [get_ports "QDR4_DQA17"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA17"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_68 +#set_property PACKAGE_PIN BL10 [get_ports "QDR4_DQA11"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA11"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_68 +#set_property PACKAGE_PIN BK10 [get_ports "QDR4_DQA12"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA12"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_68 +#set_property PACKAGE_PIN BM8 [get_ports "QDR4_QVLDA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_68 +#set_property PACKAGE_PIN BL8 [get_ports "QDR4_DQA13"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA13"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_68 +#set_property PACKAGE_PIN BN9 [get_ports "QDR4_DQA16"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA16"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_68 +#set_property PACKAGE_PIN BM9 [get_ports "QDR4_DQA9"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA9"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_68 +#set_property PACKAGE_PIN BN10 [get_ports "QDR4_DQA14"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA14"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_68 +#set_property PACKAGE_PIN BM10 [get_ports "QDR4_DQA15"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA15"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_68 +#set_property PACKAGE_PIN BP8 [get_ports "QDR4_QKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_68 +#set_property PACKAGE_PIN BP9 [get_ports "QDR4_QKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_68 +#set_property PACKAGE_PIN BL11 [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_68 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_68 +#set_property PACKAGE_PIN BN11 [get_ports "VRP_68"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_68 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_68"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_68 +#set_property PACKAGE_PIN BM15 [get_ports "QDR4_DQA4"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA4"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_68 +#set_property PACKAGE_PIN BL15 [get_ports "QDR4_DQA8"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA8"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_68 +#set_property PACKAGE_PIN BM13 [get_ports "QDR4_DQA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_68 +#set_property PACKAGE_PIN BM14 [get_ports "QDR4_DQA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_68 +#set_property PACKAGE_PIN BN14 [get_ports "SI5328_RST_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_68 +#set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_RST_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_68 +#set_property PACKAGE_PIN BN15 [get_ports "QDR4_DQA2"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA2"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_68 +#set_property PACKAGE_PIN BN12 [get_ports "QDR4_DQA3"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA3"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_68 +#set_property PACKAGE_PIN BM12 [get_ports "QDR4_DQA7"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA7"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_68 +#set_property PACKAGE_PIN BP13 [get_ports "QDR4_DQA5"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA5"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_68 +#set_property PACKAGE_PIN BP14 [get_ports "QDR4_DQA6"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_68 +#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA6"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_68 +#set_property PACKAGE_PIN BP11 [get_ports "QDR4_DKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_68 +#set_property PACKAGE_PIN BP12 [get_ports "QDR4_DKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_68 +#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_68 +#set_property PACKAGE_PIN A28 [get_ports "RLD3_72B_DM1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_75 +#set_property PACKAGE_PIN B28 [get_ports "RLD3_72B_DQ35"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ35"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_75 +#set_property PACKAGE_PIN A30 [get_ports "RLD3_72B_DQ31"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ31"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_75 +#set_property PACKAGE_PIN A29 [get_ports "RLD3_72B_DQ34"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ34"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_75 +#set_property PACKAGE_PIN A31 [get_ports "RLD3_72B_DQ27"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ27"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_75 +#set_property PACKAGE_PIN B30 [get_ports "RLD3_72B_DQ30"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ30"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_75 +#set_property PACKAGE_PIN A33 [get_ports "RLD3_72B_DQ29"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ29"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_75 +#set_property PACKAGE_PIN B32 [get_ports "RLD3_72B_DQ28"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ28"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_75 +#set_property PACKAGE_PIN C29 [get_ports "RLD3_72B_DQ33"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ33"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_75 +#set_property PACKAGE_PIN C28 [get_ports "RLD3_72B_DQ32"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ32"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_75 +#set_property PACKAGE_PIN B31 [get_ports "RLD3_72B_QK3_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK3_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_75 +#set_property PACKAGE_PIN C30 [get_ports "RLD3_72B_QK3_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK3_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_75 +#set_property PACKAGE_PIN B33 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_75 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_75 +#set_property PACKAGE_PIN C33 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_75 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_75 +#set_property PACKAGE_PIN D29 [get_ports "RLD3_72B_DQ25"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ25"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_75 +#set_property PACKAGE_PIN E28 [get_ports "RLD3_72B_QVLD1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_75 +#set_property PACKAGE_PIN C32 [get_ports "RLD3_72B_DQ21"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ21"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_75 +#set_property PACKAGE_PIN D32 [get_ports "RLD3_72B_DQ24"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ24"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_75 +#set_property PACKAGE_PIN D31 [get_ports "RLD3_72B_DQ26"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ26"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_75 +#set_property PACKAGE_PIN D30 [get_ports "RLD3_72B_DQ23"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ23"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_75 +#set_property PACKAGE_PIN E33 [get_ports "RLD3_72B_DQ18"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ18"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_75 +#set_property PACKAGE_PIN F33 [get_ports "RLD3_72B_DQ22"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ22"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_75 +#set_property PACKAGE_PIN E29 [get_ports "RLD3_72B_DQ20"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ20"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_75 +#set_property PACKAGE_PIN F29 [get_ports "RLD3_72B_DQ19"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ19"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_75 +#set_property PACKAGE_PIN E32 [get_ports "RLD3_72B_QK2_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QK2_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_75 +#set_property PACKAGE_PIN E31 [get_ports "RLD3_72B_QK2_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QK2_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_75 +#set_property PACKAGE_PIN F30 [get_ports "RLD3_72B_QVLD0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_75 +#set_property PACKAGE_PIN G30 [get_ports "RLD3_72B_DQ9"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ9"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_75 +#set_property PACKAGE_PIN F31 [get_ports "RLD3_72B_DQ11"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ11"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_75 +#set_property PACKAGE_PIN G31 [get_ports "RLD3_72B_DQ14"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ14"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_75 +#set_property PACKAGE_PIN F28 [get_ports "RLD3_72B_DQ17"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ17"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_75 +#set_property PACKAGE_PIN G28 [get_ports "RLD3_72B_DQ12"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ12"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_75 +#set_property PACKAGE_PIN G32 [get_ports "RLD3_72B_DQ15"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ15"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_75 +#set_property PACKAGE_PIN H32 [get_ports "RLD3_72B_DQ16"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ16"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_75 +#set_property PACKAGE_PIN H30 [get_ports "RLD3_72B_DQ10"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ10"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_75 +#set_property PACKAGE_PIN H29 [get_ports "RLD3_72B_DQ13"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ13"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_75 +#set_property PACKAGE_PIN G33 [get_ports "RLD3_72B_QK1_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK1_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_75 +#set_property PACKAGE_PIN H33 [get_ports "RLD3_72B_QK1_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK1_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_75 +#set_property PACKAGE_PIN H28 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_75 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_75 +#set_property PACKAGE_PIN K28 [get_ports "VRP_75"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_75 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_75"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_75 +#set_property PACKAGE_PIN J29 [get_ports "RLD3_72B_DM0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_75 +#set_property PACKAGE_PIN K29 [get_ports "RLD3_72B_DQ0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_75 +#set_property PACKAGE_PIN J31 [get_ports "RLD3_72B_DQ3"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ3"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_75 +#set_property PACKAGE_PIN J30 [get_ports "RLD3_72B_DQ1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_75 +#set_property PACKAGE_PIN J32 [get_ports "RLD3_72B_DQ7"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ7"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_75 +#set_property PACKAGE_PIN K32 [get_ports "RLD3_72B_DQ2"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ2"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_75 +#set_property PACKAGE_PIN K31 [get_ports "RLD3_72B_DQ8"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ8"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_75 +#set_property PACKAGE_PIN L31 [get_ports "RLD3_72B_DQ5"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ5"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_75 +#set_property PACKAGE_PIN L30 [get_ports "RLD3_72B_DQ6"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ6"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_75 +#set_property PACKAGE_PIN L29 [get_ports "RLD3_72B_DQ4"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_75 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ4"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_75 +#set_property PACKAGE_PIN K33 [get_ports "RLD3_72B_QK0_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK0_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_75 +#set_property PACKAGE_PIN L33 [get_ports "RLD3_72B_QK0_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_75 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK0_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_75 +#set_property PACKAGE_PIN A35 [get_ports "RLD3_72B_A12"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A12"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_74 +#set_property PACKAGE_PIN A34 [get_ports "RLD3_72B_CS_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_CS_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_74 +#set_property PACKAGE_PIN A36 [get_ports "RLD3_72B_BA2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_74 +#set_property PACKAGE_PIN B35 [get_ports "RLD3_72B_A8"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A8"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_74 +#set_property PACKAGE_PIN A38 [get_ports "RLD3_72B_A1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_74 +#set_property PACKAGE_PIN B37 [get_ports "RLD3_72B_BA1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_74 +#set_property PACKAGE_PIN B36 [get_ports "RLD3_72B_A17"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A17"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_74 +#set_property PACKAGE_PIN C35 [get_ports "RLD3_72B_A13"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A13"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_74 +#set_property PACKAGE_PIN B38 [get_ports "RLD3_72B_A2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_74 +#set_property PACKAGE_PIN C37 [get_ports "RLD3_72B_A16"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A16"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_74 +#set_property PACKAGE_PIN C34 [get_ports "RLD3_72B_BA0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_74 +#set_property PACKAGE_PIN D34 [get_ports "RLD3_72B_A10"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A10"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_74 +#set_property PACKAGE_PIN C38 [get_ports "RLD3_72B_A6"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A6"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_74 +#set_property PACKAGE_PIN C39 [get_ports "RLD3_72B_A20"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A20"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_74 +#set_property PACKAGE_PIN D37 [get_ports "RLD3_72B_WE_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_WE_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_74 +#set_property PACKAGE_PIN E36 [get_ports "RLD3_72B_A7"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A7"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_74 +#set_property PACKAGE_PIN E34 [get_ports "RLD3_72B_REF_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_REF_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_74 +#set_property PACKAGE_PIN F34 [get_ports "RLD3_72B_A18"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A18"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_74 +#set_property PACKAGE_PIN D39 [get_ports "RLD3_72B_A0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_74 +#set_property PACKAGE_PIN E39 [get_ports "RLD3_72B_A11"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A11"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_74 +#set_property PACKAGE_PIN D36 [get_ports "RLD3_72B_BA3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_74 +#set_property PACKAGE_PIN D35 [get_ports "RLD3_72B_RE#set_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_RE#set_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_74 +#set_property PACKAGE_PIN E38 [get_ports "RLD3_72B_A15"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A15"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_74 +#set_property PACKAGE_PIN E37 [get_ports "RLD3_72B_A14"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A14"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_74 +#set_property PACKAGE_PIN F36 [get_ports "RLD3_CLK_100MHZ_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_74 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_CLK_100MHZ_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_74 +#set_property PACKAGE_PIN F35 [get_ports "RLD3_CLK_100MHZ_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_74 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_CLK_100MHZ_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_74 +#set_property PACKAGE_PIN F38 [get_ports "RLD3_72B_CK_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_CK_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_74 +#set_property PACKAGE_PIN G37 [get_ports "RLD3_72B_CK_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_CK_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_74 +#set_property PACKAGE_PIN G36 [get_ports "RLD3_72B_DK3_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK3_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_74 +#set_property PACKAGE_PIN G35 [get_ports "RLD3_72B_DK3_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK3_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_74 +#set_property PACKAGE_PIN F39 [get_ports "RLD3_72B_DK2_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK2_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_74 +#set_property PACKAGE_PIN G38 [get_ports "RLD3_72B_DK2_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK2_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_74 +#set_property PACKAGE_PIN H35 [get_ports "RLD3_72B_DK1_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK1_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_74 +#set_property PACKAGE_PIN H34 [get_ports "RLD3_72B_DK1_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK1_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_74 +#set_property PACKAGE_PIN H38 [get_ports "RLD3_72B_DK0_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK0_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_74 +#set_property PACKAGE_PIN H37 [get_ports "RLD3_72B_DK0_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_74 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK0_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_74 +#set_property PACKAGE_PIN H39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_74 +#set_property PACKAGE_PIN J39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_74 +#set_property PACKAGE_PIN J34 [get_ports "RLD3_72B_A3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_74 +#set_property PACKAGE_PIN J35 [get_ports "VRP_74"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_74 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "VRP_74"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_74 +#set_property PACKAGE_PIN J37 [get_ports "RLD3_72B_A19"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A19"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_74 +#set_property PACKAGE_PIN K37 [get_ports "RLD3_72B_A5"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A5"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_74 +#set_property PACKAGE_PIN K34 [get_ports "RLD3_72B_A4"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A4"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_74 +#set_property PACKAGE_PIN L34 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_74 +#set_property PACKAGE_PIN K38 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_74 +#set_property PACKAGE_PIN L38 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_74 +#set_property PACKAGE_PIN J36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_74 +#set_property PACKAGE_PIN K36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_74 +#set_property PACKAGE_PIN K39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_74 +#set_property PACKAGE_PIN L39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_74 +#set_property PACKAGE_PIN L36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_74 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_74 +#set_property PACKAGE_PIN L35 [get_ports "RLD3_72B_A9"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_74 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A9"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_74 +#set_property PACKAGE_PIN A40 [get_ports "RLD3_72B_DM3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_73 +#set_property PACKAGE_PIN A39 [get_ports "RLD3_72B_DQ65"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ65"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_73 +#set_property PACKAGE_PIN B42 [get_ports "RLD3_72B_DQ70"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ70"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_73 +#set_property PACKAGE_PIN B41 [get_ports "RLD3_72B_DQ67"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ67"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_73 +#set_property PACKAGE_PIN A41 [get_ports "RLD3_72B_DQ66"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ66"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_73 +#set_property PACKAGE_PIN B40 [get_ports "RLD3_72B_DQ68"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ68"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_73 +#set_property PACKAGE_PIN D41 [get_ports "RLD3_72B_DQ69"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ69"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_73 +#set_property PACKAGE_PIN E41 [get_ports "RLD3_72B_DQ71"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ71"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_73 +#set_property PACKAGE_PIN C40 [get_ports "RLD3_72B_DQ64"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ64"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_73 +#set_property PACKAGE_PIN D40 [get_ports "RLD3_72B_DQ63"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ63"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_73 +#set_property PACKAGE_PIN F41 [get_ports "RLD3_72B_QK7_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK7_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_73 +#set_property PACKAGE_PIN F40 [get_ports "RLD3_72B_QK7_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK7_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_73 +#set_property PACKAGE_PIN C42 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_73 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_73 +#set_property PACKAGE_PIN B43 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_73 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_73 +#set_property PACKAGE_PIN A44 [get_ports "RLD3_72B_QVLD3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_73 +#set_property PACKAGE_PIN A43 [get_ports "RLD3_72B_DQ62"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ62"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_73 +#set_property PACKAGE_PIN B45 [get_ports "RLD3_72B_DQ57"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ57"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_73 +#set_property PACKAGE_PIN C44 [get_ports "RLD3_72B_DQ60"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ60"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_73 +#set_property PACKAGE_PIN A46 [get_ports "RLD3_72B_DQ55"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ55"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_73 +#set_property PACKAGE_PIN A45 [get_ports "RLD3_72B_DQ58"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ58"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_73 +#set_property PACKAGE_PIN B46 [get_ports "RLD3_72B_DQ54"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ54"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_73 +#set_property PACKAGE_PIN C45 [get_ports "RLD3_72B_DQ59"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ59"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_73 +#set_property PACKAGE_PIN C43 [get_ports "RLD3_72B_DQ56"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ56"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_73 +#set_property PACKAGE_PIN D42 [get_ports "RLD3_72B_DQ61"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ61"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_73 +#set_property PACKAGE_PIN E43 [get_ports "RLD3_72B_QK6_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK6_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_73 +#set_property PACKAGE_PIN E42 [get_ports "RLD3_72B_QK6_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK6_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_73 +#set_property PACKAGE_PIN D45 [get_ports "RLD3_72B_QVLD2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_73 +#set_property PACKAGE_PIN D44 [get_ports "RLD3_72B_DQ45"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ45"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_73 +#set_property PACKAGE_PIN E44 [get_ports "RLD3_72B_DQ50"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ50"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_73 +#set_property PACKAGE_PIN F44 [get_ports "RLD3_72B_DQ47"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ47"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_73 +#set_property PACKAGE_PIN D46 [get_ports "RLD3_72B_DQ48"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ48"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_73 +#set_property PACKAGE_PIN E46 [get_ports "RLD3_72B_DQ51"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ51"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_73 +#set_property PACKAGE_PIN G45 [get_ports "RLD3_72B_DQ52"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ52"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_73 +#set_property PACKAGE_PIN H45 [get_ports "RLD3_72B_DQ53"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ53"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_73 +#set_property PACKAGE_PIN F46 [get_ports "RLD3_72B_DQ49"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ49"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_73 +#set_property PACKAGE_PIN F45 [get_ports "RLD3_72B_DQ46"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ46"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_73 +#set_property PACKAGE_PIN H44 [get_ports "RLD3_72B_QK5_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK5_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_73 +#set_property PACKAGE_PIN J44 [get_ports "RLD3_72B_QK5_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK5_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_73 +#set_property PACKAGE_PIN G46 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_73 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_73 +#set_property PACKAGE_PIN F43 [get_ports "VRP_73"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_73 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_73"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_73 +#set_property PACKAGE_PIN G43 [get_ports "RLD3_72B_DM2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_73 +#set_property PACKAGE_PIN H43 [get_ports "RLD3_72B_DQ40"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ40"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_73 +#set_property PACKAGE_PIN G42 [get_ports "RLD3_72B_DQ36"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ36"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_73 +#set_property PACKAGE_PIN G41 [get_ports "RLD3_72B_DQ37"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ37"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_73 +#set_property PACKAGE_PIN G40 [get_ports "RLD3_72B_DQ39"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ39"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_73 +#set_property PACKAGE_PIN H40 [get_ports "RLD3_72B_DQ42"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ42"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_73 +#set_property PACKAGE_PIN J41 [get_ports "RLD3_72B_DQ44"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ44"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_73 +#set_property PACKAGE_PIN J40 [get_ports "RLD3_72B_DQ43"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ43"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_73 +#set_property PACKAGE_PIN H42 [get_ports "RLD3_72B_DQ38"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ38"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_73 +#set_property PACKAGE_PIN J42 [get_ports "RLD3_72B_DQ41"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_73 +#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ41"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_73 +#set_property PACKAGE_PIN K42 [get_ports "RLD3_72B_QK4_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK4_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_73 +#set_property PACKAGE_PIN K41 [get_ports "RLD3_72B_QK4_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_73 +#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK4_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_73 +#set_property PACKAGE_PIN A24 [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 +#set_property PACKAGE_PIN A25 [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 +#set_property PACKAGE_PIN A26 [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 72 VCCO - VADJ - IO_L23N_T3U_N9_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 72 VCCO - VADJ - IO_L23N_T3U_N9_72 +#set_property PACKAGE_PIN B27 [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 72 VCCO - VADJ - IO_L23P_T3U_N8_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 72 VCCO - VADJ - IO_L23P_T3U_N8_72 + +set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND +set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; + +set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD +set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; + +set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] + +set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; + +#set_property PACKAGE_PIN C24 [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 72 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 72 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_72 +#set_property PACKAGE_PIN C25 [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 72 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 72 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_72 +#set_property PACKAGE_PIN B22 [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 72 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 72 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_72 +#set_property PACKAGE_PIN C23 [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 +#set_property PACKAGE_PIN C22 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T3U_N12_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T3U_N12_72 +#set_property PACKAGE_PIN C27 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T2U_N12_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T2U_N12_72 +#set_property PACKAGE_PIN D27 [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 72 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 72 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_72 +#set_property PACKAGE_PIN E27 [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 72 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 72 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_72 +#set_property PACKAGE_PIN D26 [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 +#set_property PACKAGE_PIN E26 [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 +#set_property PACKAGE_PIN D24 [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_72 +#set_property PACKAGE_PIN D25 [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_72 +#set_property PACKAGE_PIN D22 [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 +#set_property PACKAGE_PIN E22 [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 +#set_property PACKAGE_PIN F25 [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 +#set_property PACKAGE_PIN F26 [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 +#set_property PACKAGE_PIN E23 [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_72 +#set_property PACKAGE_PIN E24 [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_72 +#set_property PACKAGE_PIN G25 [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L12N_T1U_N11_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L12N_T1U_N11_GC_72 +#set_property PACKAGE_PIN G26 [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L12P_T1U_N10_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L12P_T1U_N10_GC_72 +#set_property PACKAGE_PIN F23 [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L11N_T1U_N9_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L11N_T1U_N9_GC_72 +#set_property PACKAGE_PIN F24 [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L11P_T1U_N8_GC_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L11P_T1U_N8_GC_72 +#set_property PACKAGE_PIN G22 [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_72 +#set_property PACKAGE_PIN G23 [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_72 +#set_property PACKAGE_PIN G27 [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 +#set_property PACKAGE_PIN H27 [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 + +set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; + +set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] + +#set_property PACKAGE_PIN H23 [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_72 +#set_property PACKAGE_PIN H24 [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_72 +#set_property PACKAGE_PIN H25 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T1U_N12_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T1U_N12_72 +#set_property PACKAGE_PIN J24 [get_ports "VRP_72"] ;# Bank 72 VCCO - VADJ - IO_T0U_N12_VRP_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_72"] ;# Bank 72 VCCO - VADJ - IO_T0U_N12_VRP_72 +#set_property PACKAGE_PIN J25 [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 72 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 72 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_72 +#set_property PACKAGE_PIN J26 [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 72 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 72 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_72 +#set_property PACKAGE_PIN J27 [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 72 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 72 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_72 +#set_property PACKAGE_PIN K27 [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 72 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 72 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_72 +#set_property PACKAGE_PIN K22 [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 72 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 72 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_72 +#set_property PACKAGE_PIN L23 [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 +#set_property PACKAGE_PIN K23 [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 +#set_property PACKAGE_PIN K24 [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 +#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 +#set_property PACKAGE_PIN K26 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2N_T0L_N3_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2N_T0L_N3_72 +#set_property PACKAGE_PIN L26 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2P_T0L_N2_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2P_T0L_N2_72 +#set_property PACKAGE_PIN L24 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1N_T0L_N1_DBC_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1N_T0L_N1_DBC_72 +#set_property PACKAGE_PIN L25 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1P_T0L_N0_DBC_72 +#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1P_T0L_N0_DBC_72 +#set_property PACKAGE_PIN AV43 [get_ports "FMCP_HSPC_GBTCLK0_M2C_N"] ;# Bank 124 - MGTREFCLK0N_124 +#set_property PACKAGE_PIN AV42 [get_ports "FMCP_HSPC_GBTCLK0_M2C_P"] ;# Bank 124 - MGTREFCLK0P_124 +#set_property PACKAGE_PIN AT43 [get_ports "No Connect"] ;# Bank 124 - MGTREFCLK1N_124 +#set_property PACKAGE_PIN AT42 [get_ports "No Connect"] ;# Bank 124 - MGTREFCLK1P_124 +#set_property PACKAGE_PIN BC54 [get_ports "FMCP_HSPC_DP0_M2C_N"] ;# Bank 124 - MGTYRXN0_124 +#set_property PACKAGE_PIN BB52 [get_ports "FMCP_HSPC_DP1_M2C_N"] ;# Bank 124 - MGTYRXN1_124 +#set_property PACKAGE_PIN BA54 [get_ports "FMCP_HSPC_DP2_M2C_N"] ;# Bank 124 - MGTYRXN2_124 +#set_property PACKAGE_PIN BA50 [get_ports "FMCP_HSPC_DP3_M2C_N"] ;# Bank 124 - MGTYRXN3_124 +#set_property PACKAGE_PIN BC53 [get_ports "FMCP_HSPC_DP0_M2C_P"] ;# Bank 124 - MGTYRXP0_124 +#set_property PACKAGE_PIN BB51 [get_ports "FMCP_HSPC_DP1_M2C_P"] ;# Bank 124 - MGTYRXP1_124 +#set_property PACKAGE_PIN BA53 [get_ports "FMCP_HSPC_DP2_M2C_P"] ;# Bank 124 - MGTYRXP2_124 +#set_property PACKAGE_PIN BA49 [get_ports "FMCP_HSPC_DP3_M2C_P"] ;# Bank 124 - MGTYRXP3_124 +#set_property PACKAGE_PIN BC49 [get_ports "FMCP_HSPC_DP0_C2M_N"] ;# Bank 124 - MGTYTXN0_124 +#set_property PACKAGE_PIN BC45 [get_ports "FMCP_HSPC_DP1_C2M_N"] ;# Bank 124 - MGTYTXN1_124 +#set_property PACKAGE_PIN BB47 [get_ports "FMCP_HSPC_DP2_C2M_N"] ;# Bank 124 - MGTYTXN2_124 +#set_property PACKAGE_PIN BA45 [get_ports "FMCP_HSPC_DP3_C2M_N"] ;# Bank 124 - MGTYTXN3_124 +#set_property PACKAGE_PIN BC48 [get_ports "FMCP_HSPC_DP0_C2M_P"] ;# Bank 124 - MGTYTXP0_124 +#set_property PACKAGE_PIN BC44 [get_ports "FMCP_HSPC_DP1_C2M_P"] ;# Bank 124 - MGTYTXP1_124 +#set_property PACKAGE_PIN BB46 [get_ports "FMCP_HSPC_DP2_C2M_P"] ;# Bank 124 - MGTYTXP2_124 +#set_property PACKAGE_PIN BA44 [get_ports "FMCP_HSPC_DP3_C2M_P"] ;# Bank 124 - MGTYTXP3_124 +#set_property PACKAGE_PIN AR41 [get_ports "FMCP_HSPC_GBTCLK1_M2C_N"] ;# Bank 125 - MGTREFCLK0N_125 +#set_property PACKAGE_PIN AR40 [get_ports "FMCP_HSPC_GBTCLK1_M2C_P"] ;# Bank 125 - MGTREFCLK0P_125 +#set_property PACKAGE_PIN AP43 [get_ports "No Connect"] ;# Bank 125 - MGTREFCLK1N_125 +#set_property PACKAGE_PIN AP42 [get_ports "No Connect"] ;# Bank 125 - MGTREFCLK1P_125 +#set_property PACKAGE_PIN AU41 [get_ports "N22117206"] ;# Bank 125 - MGTRREF_LS +#set_property PACKAGE_PIN AY52 [get_ports "FMCP_HSPC_DP4_M2C_N"] ;# Bank 125 - MGTYRXN0_125 +#set_property PACKAGE_PIN AW54 [get_ports "FMCP_HSPC_DP5_M2C_N"] ;# Bank 125 - MGTYRXN1_125 +#set_property PACKAGE_PIN AW50 [get_ports "FMCP_HSPC_DP6_M2C_N"] ;# Bank 125 - MGTYRXN2_125 +#set_property PACKAGE_PIN AV52 [get_ports "FMCP_HSPC_DP7_M2C_N"] ;# Bank 125 - MGTYRXN3_125 +#set_property PACKAGE_PIN AY51 [get_ports "FMCP_HSPC_DP4_M2C_P"] ;# Bank 125 - MGTYRXP0_125 +#set_property PACKAGE_PIN AW53 [get_ports "FMCP_HSPC_DP5_M2C_P"] ;# Bank 125 - MGTYRXP1_125 +#set_property PACKAGE_PIN AW49 [get_ports "FMCP_HSPC_DP6_M2C_P"] ;# Bank 125 - MGTYRXP2_125 +#set_property PACKAGE_PIN AV51 [get_ports "FMCP_HSPC_DP7_M2C_P"] ;# Bank 125 - MGTYRXP3_125 +#set_property PACKAGE_PIN AY47 [get_ports "FMCP_HSPC_DP4_C2M_N"] ;# Bank 125 - MGTYTXN0_125 +#set_property PACKAGE_PIN AW45 [get_ports "FMCP_HSPC_DP5_C2M_N"] ;# Bank 125 - MGTYTXN1_125 +#set_property PACKAGE_PIN AV47 [get_ports "FMCP_HSPC_DP6_C2M_N"] ;# Bank 125 - MGTYTXN2_125 +#set_property PACKAGE_PIN AU45 [get_ports "FMCP_HSPC_DP7_C2M_N"] ;# Bank 125 - MGTYTXN3_125 +#set_property PACKAGE_PIN AY46 [get_ports "FMCP_HSPC_DP4_C2M_P"] ;# Bank 125 - MGTYTXP0_125 +#set_property PACKAGE_PIN AW44 [get_ports "FMCP_HSPC_DP5_C2M_P"] ;# Bank 125 - MGTYTXP1_125 +#set_property PACKAGE_PIN AV46 [get_ports "FMCP_HSPC_DP6_C2M_P"] ;# Bank 125 - MGTYTXP2_125 +#set_property PACKAGE_PIN AU44 [get_ports "FMCP_HSPC_DP7_C2M_P"] ;# Bank 125 - MGTYTXP3_125 +#set_property PACKAGE_PIN AN41 [get_ports "FMCP_HSPC_GBTCLK2_M2C_N"] ;# Bank 126 - MGTREFCLK0N_126 +#set_property PACKAGE_PIN AN40 [get_ports "FMCP_HSPC_GBTCLK2_M2C_P"] ;# Bank 126 - MGTREFCLK0P_126 +#set_property PACKAGE_PIN AM43 [get_ports "No Connect"] ;# Bank 126 - MGTREFCLK1N_126 +#set_property PACKAGE_PIN AM42 [get_ports "No Connect"] ;# Bank 126 - MGTREFCLK1P_126 +#set_property PACKAGE_PIN AU54 [get_ports "FMCP_HSPC_DP8_M2C_N"] ;# Bank 126 - MGTYRXN0_126 +#set_property PACKAGE_PIN AT52 [get_ports "FMCP_HSPC_DP9_M2C_N"] ;# Bank 126 - MGTYRXN1_126 +#set_property PACKAGE_PIN AR54 [get_ports "FMCP_HSPC_DP10_M2C_N"] ;# Bank 126 - MGTYRXN2_126 +#set_property PACKAGE_PIN AP52 [get_ports "FMCP_HSPC_DP11_M2C_N"] ;# Bank 126 - MGTYRXN3_126 +#set_property PACKAGE_PIN AU53 [get_ports "FMCP_HSPC_DP8_M2C_P"] ;# Bank 126 - MGTYRXP0_126 +#set_property PACKAGE_PIN AT51 [get_ports "FMCP_HSPC_DP9_M2C_P"] ;# Bank 126 - MGTYRXP1_126 +#set_property PACKAGE_PIN AR53 [get_ports "FMCP_HSPC_DP10_M2C_P"] ;# Bank 126 - MGTYRXP2_126 +#set_property PACKAGE_PIN AP51 [get_ports "FMCP_HSPC_DP11_M2C_P"] ;# Bank 126 - MGTYRXP3_126 +#set_property PACKAGE_PIN AU49 [get_ports "FMCP_HSPC_DP8_C2M_N"] ;# Bank 126 - MGTYTXN0_126 +#set_property PACKAGE_PIN AT47 [get_ports "FMCP_HSPC_DP9_C2M_N"] ;# Bank 126 - MGTYTXN1_126 +#set_property PACKAGE_PIN AR49 [get_ports "FMCP_HSPC_DP10_C2M_N"] ;# Bank 126 - MGTYTXN2_126 +#set_property PACKAGE_PIN AR45 [get_ports "FMCP_HSPC_DP11_C2M_N"] ;# Bank 126 - MGTYTXN3_126 +#set_property PACKAGE_PIN AU48 [get_ports "FMCP_HSPC_DP8_C2M_P"] ;# Bank 126 - MGTYTXP0_126 +#set_property PACKAGE_PIN AT46 [get_ports "FMCP_HSPC_DP9_C2M_P"] ;# Bank 126 - MGTYTXP1_126 +#set_property PACKAGE_PIN AR48 [get_ports "FMCP_HSPC_DP10_C2M_P"] ;# Bank 126 - MGTYTXP2_126 +#set_property PACKAGE_PIN AR44 [get_ports "FMCP_HSPC_DP11_C2M_P"] ;# Bank 126 - MGTYTXP3_126 +#set_property PACKAGE_PIN AL41 [get_ports "FMCP_HSPC_GBTCLK3_M2C_N"] ;# Bank 127 - MGTREFCLK0N_127 +#set_property PACKAGE_PIN AL40 [get_ports "FMCP_HSPC_GBTCLK3_M2C_P"] ;# Bank 127 - MGTREFCLK0P_127 +#set_property PACKAGE_PIN AK43 [get_ports "No Connect"] ;# Bank 127 - MGTREFCLK1N_127 +#set_property PACKAGE_PIN AK42 [get_ports "No Connect"] ;# Bank 127 - MGTREFCLK1P_127 +#set_property PACKAGE_PIN AN54 [get_ports "FMCP_HSPC_DP12_M2C_N"] ;# Bank 127 - MGTYRXN0_127 +#set_property PACKAGE_PIN AN50 [get_ports "FMCP_HSPC_DP13_M2C_N"] ;# Bank 127 - MGTYRXN1_127 +#set_property PACKAGE_PIN AM52 [get_ports "FMCP_HSPC_DP14_M2C_N"] ;# Bank 127 - MGTYRXN2_127 +#set_property PACKAGE_PIN AL54 [get_ports "FMCP_HSPC_DP15_M2C_N"] ;# Bank 127 - MGTYRXN3_127 +#set_property PACKAGE_PIN AN53 [get_ports "FMCP_HSPC_DP12_M2C_P"] ;# Bank 127 - MGTYRXP0_127 +#set_property PACKAGE_PIN AN49 [get_ports "FMCP_HSPC_DP13_M2C_P"] ;# Bank 127 - MGTYRXP1_127 +#set_property PACKAGE_PIN AM51 [get_ports "FMCP_HSPC_DP14_M2C_P"] ;# Bank 127 - MGTYRXP2_127 +#set_property PACKAGE_PIN AL53 [get_ports "FMCP_HSPC_DP15_M2C_P"] ;# Bank 127 - MGTYRXP3_127 +#set_property PACKAGE_PIN AP47 [get_ports "FMCP_HSPC_DP12_C2M_N"] ;# Bank 127 - MGTYTXN0_127 +#set_property PACKAGE_PIN AN45 [get_ports "FMCP_HSPC_DP13_C2M_N"] ;# Bank 127 - MGTYTXN1_127 +#set_property PACKAGE_PIN AM47 [get_ports "FMCP_HSPC_DP14_C2M_N"] ;# Bank 127 - MGTYTXN2_127 +#set_property PACKAGE_PIN AL45 [get_ports "FMCP_HSPC_DP15_C2M_N"] ;# Bank 127 - MGTYTXN3_127 +#set_property PACKAGE_PIN AP46 [get_ports "FMCP_HSPC_DP12_C2M_P"] ;# Bank 127 - MGTYTXP0_127 +#set_property PACKAGE_PIN AN44 [get_ports "FMCP_HSPC_DP13_C2M_P"] ;# Bank 127 - MGTYTXP1_127 +#set_property PACKAGE_PIN AM46 [get_ports "FMCP_HSPC_DP14_C2M_P"] ;# Bank 127 - MGTYTXP2_127 +#set_property PACKAGE_PIN AL44 [get_ports "FMCP_HSPC_DP15_C2M_P"] ;# Bank 127 - MGTYTXP3_127 +#set_property PACKAGE_PIN AJ41 [get_ports "FMCP_HSPC_GBTCLK4_M2C_N"] ;# Bank 128 - MGTREFCLK0N_128 +#set_property PACKAGE_PIN AJ40 [get_ports "FMCP_HSPC_GBTCLK4_M2C_P"] ;# Bank 128 - MGTREFCLK0P_128 +#set_property PACKAGE_PIN AH43 [get_ports "No Connect"] ;# Bank 128 - MGTREFCLK1N_128 +#set_property PACKAGE_PIN AH42 [get_ports "No Connect"] ;# Bank 128 - MGTREFCLK1P_128 +#set_property PACKAGE_PIN AL50 [get_ports "FMCP_HSPC_DP16_M2C_N"] ;# Bank 128 - MGTYRXN0_128 +#set_property PACKAGE_PIN AK52 [get_ports "FMCP_HSPC_DP17_M2C_N"] ;# Bank 128 - MGTYRXN1_128 +#set_property PACKAGE_PIN AJ54 [get_ports "FMCP_HSPC_DP18_M2C_N"] ;# Bank 128 - MGTYRXN2_128 +#set_property PACKAGE_PIN AH52 [get_ports "FMCP_HSPC_DP19_M2C_N"] ;# Bank 128 - MGTYRXN3_128 +#set_property PACKAGE_PIN AL49 [get_ports "FMCP_HSPC_DP16_M2C_P"] ;# Bank 128 - MGTYRXP0_128 +#set_property PACKAGE_PIN AK51 [get_ports "FMCP_HSPC_DP17_M2C_P"] ;# Bank 128 - MGTYRXP1_128 +#set_property PACKAGE_PIN AJ53 [get_ports "FMCP_HSPC_DP18_M2C_P"] ;# Bank 128 - MGTYRXP2_128 +#set_property PACKAGE_PIN AH51 [get_ports "FMCP_HSPC_DP19_M2C_P"] ;# Bank 128 - MGTYRXP3_128 +#set_property PACKAGE_PIN AK47 [get_ports "FMCP_HSPC_DP16_C2M_N"] ;# Bank 128 - MGTYTXN0_128 +#set_property PACKAGE_PIN AJ49 [get_ports "FMCP_HSPC_DP17_C2M_N"] ;# Bank 128 - MGTYTXN1_128 +#set_property PACKAGE_PIN AJ45 [get_ports "FMCP_HSPC_DP18_C2M_N"] ;# Bank 128 - MGTYTXN2_128 +#set_property PACKAGE_PIN AH47 [get_ports "FMCP_HSPC_DP19_C2M_N"] ;# Bank 128 - MGTYTXN3_128 +#set_property PACKAGE_PIN AK46 [get_ports "FMCP_HSPC_DP16_C2M_P"] ;# Bank 128 - MGTYTXP0_128 +#set_property PACKAGE_PIN AJ48 [get_ports "FMCP_HSPC_DP17_C2M_P"] ;# Bank 128 - MGTYTXP1_128 +#set_property PACKAGE_PIN AJ44 [get_ports "FMCP_HSPC_DP18_C2M_P"] ;# Bank 128 - MGTYTXP2_128 +#set_property PACKAGE_PIN AH46 [get_ports "FMCP_HSPC_DP19_C2M_P"] ;# Bank 128 - MGTYTXP3_128 +#set_property PACKAGE_PIN AG41 [get_ports "FMCP_HSPC_GBTCLK5_M2C_N"] ;# Bank 129 - MGTREFCLK0N_129 +#set_property PACKAGE_PIN AG40 [get_ports "FMCP_HSPC_GBTCLK5_M2C_P"] ;# Bank 129 - MGTREFCLK0P_129 +#set_property PACKAGE_PIN AF43 [get_ports "No Connect"] ;# Bank 129 - MGTREFCLK1N_129 +#set_property PACKAGE_PIN AF42 [get_ports "No Connect"] ;# Bank 129 - MGTREFCLK1P_129 +#set_property PACKAGE_PIN AE41 [get_ports "N21075880"] ;# Bank 129 - MGTRREF_LC +#set_property PACKAGE_PIN AG54 [get_ports "FMCP_HSPC_DP20_M2C_N"] ;# Bank 129 - MGTYRXN0_129 +#set_property PACKAGE_PIN AF52 [get_ports "FMCP_HSPC_DP21_M2C_N"] ;# Bank 129 - MGTYRXN1_129 +#set_property PACKAGE_PIN AE54 [get_ports "FMCP_HSPC_DP22_M2C_N"] ;# Bank 129 - MGTYRXN2_129 +#set_property PACKAGE_PIN AE50 [get_ports "FMCP_HSPC_DP23_M2C_N"] ;# Bank 129 - MGTYRXN3_129 +#set_property PACKAGE_PIN AG53 [get_ports "FMCP_HSPC_DP20_M2C_P"] ;# Bank 129 - MGTYRXP0_129 +#set_property PACKAGE_PIN AF51 [get_ports "FMCP_HSPC_DP21_M2C_P"] ;# Bank 129 - MGTYRXP1_129 +#set_property PACKAGE_PIN AE53 [get_ports "FMCP_HSPC_DP22_M2C_P"] ;# Bank 129 - MGTYRXP2_129 +#set_property PACKAGE_PIN AE49 [get_ports "FMCP_HSPC_DP23_M2C_P"] ;# Bank 129 - MGTYRXP3_129 +#set_property PACKAGE_PIN AG49 [get_ports "FMCP_HSPC_DP20_C2M_N"] ;# Bank 129 - MGTYTXN0_129 +#set_property PACKAGE_PIN AG45 [get_ports "FMCP_HSPC_DP21_C2M_N"] ;# Bank 129 - MGTYTXN1_129 +#set_property PACKAGE_PIN AF47 [get_ports "FMCP_HSPC_DP22_C2M_N"] ;# Bank 129 - MGTYTXN2_129 +#set_property PACKAGE_PIN AE45 [get_ports "FMCP_HSPC_DP23_C2M_N"] ;# Bank 129 - MGTYTXN3_129 +#set_property PACKAGE_PIN AG48 [get_ports "FMCP_HSPC_DP20_C2M_P"] ;# Bank 129 - MGTYTXP0_129 +#set_property PACKAGE_PIN AG44 [get_ports "FMCP_HSPC_DP21_C2M_P"] ;# Bank 129 - MGTYTXP1_129 +#set_property PACKAGE_PIN AF46 [get_ports "FMCP_HSPC_DP22_C2M_P"] ;# Bank 129 - MGTYTXP2_129 +#set_property PACKAGE_PIN AE44 [get_ports "FMCP_HSPC_DP23_C2M_P"] ;# Bank 129 - MGTYTXP3_129 +#set_property PACKAGE_PIN AD43 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK0N_130 +#set_property PACKAGE_PIN AD42 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK0P_130 +#set_property PACKAGE_PIN AC41 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK1N_130 +#set_property PACKAGE_PIN AC40 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK1P_130 +#set_property PACKAGE_PIN AD52 [get_ports "GND"] ;# Bank 130 - MGTYRXN0_130 +#set_property PACKAGE_PIN AC54 [get_ports "GND"] ;# Bank 130 - MGTYRXN1_130 +#set_property PACKAGE_PIN AC50 [get_ports "GND"] ;# Bank 130 - MGTYRXN2_130 +#set_property PACKAGE_PIN AB52 [get_ports "GND"] ;# Bank 130 - MGTYRXN3_130 +#set_property PACKAGE_PIN AD51 [get_ports "GND"] ;# Bank 130 - MGTYRXP0_130 +#set_property PACKAGE_PIN AC53 [get_ports "GND"] ;# Bank 130 - MGTYRXP1_130 +#set_property PACKAGE_PIN AC49 [get_ports "GND"] ;# Bank 130 - MGTYRXP2_130 +#set_property PACKAGE_PIN AB51 [get_ports "GND"] ;# Bank 130 - MGTYRXP3_130 +#set_property PACKAGE_PIN AD47 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN0_130 +#set_property PACKAGE_PIN AC45 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN1_130 +#set_property PACKAGE_PIN AB47 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN2_130 +#set_property PACKAGE_PIN AA49 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN3_130 +#set_property PACKAGE_PIN AD46 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP0_130 +#set_property PACKAGE_PIN AC44 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP1_130 +#set_property PACKAGE_PIN AB46 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP2_130 +#set_property PACKAGE_PIN AA48 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP3_130 +#set_property PACKAGE_PIN AB43 [get_ports "QSFP4_SI570_CLOCK_N"] ;# Bank 131 - MGTREFCLK0N_131 +#set_property PACKAGE_PIN AB42 [get_ports "QSFP4_SI570_CLOCK_P"] ;# Bank 131 - MGTREFCLK0P_131 +#set_property PACKAGE_PIN AA41 [get_ports "SMA_REFCLK_INPUT_N"] ;# Bank 131 - MGTREFCLK1N_131 +#set_property PACKAGE_PIN AA40 [get_ports "SMA_REFCLK_INPUT_P"] ;# Bank 131 - MGTREFCLK1P_131 +#set_property PACKAGE_PIN AA54 [get_ports "QSFP4_RX1_N"] ;# Bank 131 - MGTYRXN0_131 +#set_property PACKAGE_PIN Y52 [get_ports "QSFP4_RX2_N"] ;# Bank 131 - MGTYRXN1_131 +#set_property PACKAGE_PIN W54 [get_ports "QSFP4_RX3_N"] ;# Bank 131 - MGTYRXN2_131 +#set_property PACKAGE_PIN V52 [get_ports "QSFP4_RX4_N"] ;# Bank 131 - MGTYRXN3_131 +#set_property PACKAGE_PIN AA53 [get_ports "QSFP4_RX1_P"] ;# Bank 131 - MGTYRXP0_131 +#set_property PACKAGE_PIN Y51 [get_ports "QSFP4_RX2_P"] ;# Bank 131 - MGTYRXP1_131 +#set_property PACKAGE_PIN W53 [get_ports "QSFP4_RX3_P"] ;# Bank 131 - MGTYRXP2_131 +#set_property PACKAGE_PIN V51 [get_ports "QSFP4_RX4_P"] ;# Bank 131 - MGTYRXP3_131 +#set_property PACKAGE_PIN AA45 [get_ports "QSFP4_TX1_N"] ;# Bank 131 - MGTYTXN0_131 +#set_property PACKAGE_PIN Y47 [get_ports "QSFP4_TX2_N"] ;# Bank 131 - MGTYTXN1_131 +#set_property PACKAGE_PIN W49 [get_ports "QSFP4_TX3_N"] ;# Bank 131 - MGTYTXN2_131 +#set_property PACKAGE_PIN W45 [get_ports "QSFP4_TX4_N"] ;# Bank 131 - MGTYTXN3_131 +#set_property PACKAGE_PIN AA44 [get_ports "QSFP4_TX1_P"] ;# Bank 131 - MGTYTXP0_131 +#set_property PACKAGE_PIN Y46 [get_ports "QSFP4_TX2_P"] ;# Bank 131 - MGTYTXP1_131 +#set_property PACKAGE_PIN W48 [get_ports "QSFP4_TX3_P"] ;# Bank 131 - MGTYTXP2_131 +#set_property PACKAGE_PIN W44 [get_ports "QSFP4_TX4_P"] ;# Bank 131 - MGTYTXP3_131 +#set_property PACKAGE_PIN Y43 [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 132 - MGTREFCLK0N_132 +#set_property PACKAGE_PIN Y42 [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 132 - MGTREFCLK0P_132 +#set_property PACKAGE_PIN W41 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 132 - MGTREFCLK1N_132 +#set_property PACKAGE_PIN W40 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 132 - MGTREFCLK1P_132 +#set_property PACKAGE_PIN U54 [get_ports "QSFP3_RX1_N"] ;# Bank 132 - MGTYRXN0_132 +#set_property PACKAGE_PIN U50 [get_ports "QSFP3_RX2_N"] ;# Bank 132 - MGTYRXN1_132 +#set_property PACKAGE_PIN T52 [get_ports "QSFP3_RX3_N"] ;# Bank 132 - MGTYRXN2_132 +#set_property PACKAGE_PIN R54 [get_ports "QSFP3_RX4_N"] ;# Bank 132 - MGTYRXN3_132 +#set_property PACKAGE_PIN U53 [get_ports "QSFP3_RX1_P"] ;# Bank 132 - MGTYRXP0_132 +#set_property PACKAGE_PIN U49 [get_ports "QSFP3_RX2_P"] ;# Bank 132 - MGTYRXP1_132 +#set_property PACKAGE_PIN T51 [get_ports "QSFP3_RX3_P"] ;# Bank 132 - MGTYRXP2_132 +#set_property PACKAGE_PIN R53 [get_ports "QSFP3_RX4_P"] ;# Bank 132 - MGTYRXP3_132 +#set_property PACKAGE_PIN V47 [get_ports "QSFP3_TX1_N"] ;# Bank 132 - MGTYTXN0_132 +#set_property PACKAGE_PIN U45 [get_ports "QSFP3_TX2_N"] ;# Bank 132 - MGTYTXN1_132 +#set_property PACKAGE_PIN T47 [get_ports "QSFP3_TX3_N"] ;# Bank 132 - MGTYTXN2_132 +#set_property PACKAGE_PIN R45 [get_ports "QSFP3_TX4_N"] ;# Bank 132 - MGTYTXN3_132 +#set_property PACKAGE_PIN V46 [get_ports "QSFP3_TX1_P"] ;# Bank 132 - MGTYTXP0_132 +#set_property PACKAGE_PIN U44 [get_ports "QSFP3_TX2_P"] ;# Bank 132 - MGTYTXP1_132 +#set_property PACKAGE_PIN T46 [get_ports "QSFP3_TX3_P"] ;# Bank 132 - MGTYTXP2_132 +#set_property PACKAGE_PIN R44 [get_ports "QSFP3_TX4_P"] ;# Bank 132 - MGTYTXP3_132 +#set_property PACKAGE_PIN V43 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK0N_133 +#set_property PACKAGE_PIN V42 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK0P_133 +#set_property PACKAGE_PIN U41 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK1N_133 +#set_property PACKAGE_PIN U40 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK1P_133 +#set_property PACKAGE_PIN N41 [get_ports "N22119065"] ;# Bank 133 - MGTRREF_LN +#set_property PACKAGE_PIN R50 [get_ports "GND"] ;# Bank 133 - MGTYRXN0_133 +#set_property PACKAGE_PIN P52 [get_ports "GND"] ;# Bank 133 - MGTYRXN1_133 +#set_property PACKAGE_PIN N54 [get_ports "GND"] ;# Bank 133 - MGTYRXN2_133 +#set_property PACKAGE_PIN M52 [get_ports "GND"] ;# Bank 133 - MGTYRXN3_133 +#set_property PACKAGE_PIN R49 [get_ports "GND"] ;# Bank 133 - MGTYRXP0_133 +#set_property PACKAGE_PIN P51 [get_ports "GND"] ;# Bank 133 - MGTYRXP1_133 +#set_property PACKAGE_PIN N53 [get_ports "GND"] ;# Bank 133 - MGTYRXP2_133 +#set_property PACKAGE_PIN M51 [get_ports "GND"] ;# Bank 133 - MGTYRXP3_133 +#set_property PACKAGE_PIN P47 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN0_133 +#set_property PACKAGE_PIN N49 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN1_133 +#set_property PACKAGE_PIN N45 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN2_133 +#set_property PACKAGE_PIN M47 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN3_133 +#set_property PACKAGE_PIN P46 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP0_133 +#set_property PACKAGE_PIN N48 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP1_133 +#set_property PACKAGE_PIN N44 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP2_133 +#set_property PACKAGE_PIN M46 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP3_133 +#set_property PACKAGE_PIN T43 [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 134 - MGTREFCLK0N_134 +#set_property PACKAGE_PIN T42 [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 134 - MGTREFCLK0P_134 +#set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 134 - MGTREFCLK1N_134 +#set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 134 - MGTREFCLK1P_134 +#set_property PACKAGE_PIN L54 [get_ports "QSFP2_RX1_N"] ;# Bank 134 - MGTYRXN0_134 +#set_property PACKAGE_PIN K52 [get_ports "QSFP2_RX2_N"] ;# Bank 134 - MGTYRXN1_134 +#set_property PACKAGE_PIN J54 [get_ports "QSFP2_RX3_N"] ;# Bank 134 - MGTYRXN2_134 +#set_property PACKAGE_PIN H52 [get_ports "QSFP2_RX4_N"] ;# Bank 134 - MGTYRXN3_134 +#set_property PACKAGE_PIN L53 [get_ports "QSFP2_RX1_P"] ;# Bank 134 - MGTYRXP0_134 +#set_property PACKAGE_PIN K51 [get_ports "QSFP2_RX2_P"] ;# Bank 134 - MGTYRXP1_134 +#set_property PACKAGE_PIN J53 [get_ports "QSFP2_RX3_P"] ;# Bank 134 - MGTYRXP2_134 +#set_property PACKAGE_PIN H51 [get_ports "QSFP2_RX4_P"] ;# Bank 134 - MGTYRXP3_134 +#set_property PACKAGE_PIN L49 [get_ports "QSFP2_TX1_N"] ;# Bank 134 - MGTYTXN0_134 +#set_property PACKAGE_PIN L45 [get_ports "QSFP2_TX2_N"] ;# Bank 134 - MGTYTXN1_134 +#set_property PACKAGE_PIN K47 [get_ports "QSFP2_TX3_N"] ;# Bank 134 - MGTYTXN2_134 +#set_property PACKAGE_PIN J49 [get_ports "QSFP2_TX4_N"] ;# Bank 134 - MGTYTXN3_134 +#set_property PACKAGE_PIN L48 [get_ports "QSFP2_TX1_P"] ;# Bank 134 - MGTYTXP0_134 +#set_property PACKAGE_PIN L44 [get_ports "QSFP2_TX2_P"] ;# Bank 134 - MGTYTXP1_134 +#set_property PACKAGE_PIN K46 [get_ports "QSFP2_TX3_P"] ;# Bank 134 - MGTYTXP2_134 +#set_property PACKAGE_PIN J48 [get_ports "QSFP2_TX4_P"] ;# Bank 134 - MGTYTXP3_134 +#set_property PACKAGE_PIN P43 [get_ports "QSFP1_SI570_CLOCK_N"] ;# Bank 135 - MGTREFCLK0N_135 +#set_property PACKAGE_PIN P42 [get_ports "QSFP1_SI570_CLOCK_P"] ;# Bank 135 - MGTREFCLK0P_135 +#set_property PACKAGE_PIN M43 [get_ports "No Connect"] ;# Bank 135 - MGTREFCLK1N_135 +#set_property PACKAGE_PIN M42 [get_ports "No Connect"] ;# Bank 135 - MGTREFCLK1P_135 +#set_property PACKAGE_PIN G54 [get_ports "QSFP1_RX1_N"] ;# Bank 135 - MGTYRXN0_135 +#set_property PACKAGE_PIN F52 [get_ports "QSFP1_RX2_N"] ;# Bank 135 - MGTYRXN1_135 +#set_property PACKAGE_PIN E54 [get_ports "QSFP1_RX3_N"] ;# Bank 135 - MGTYRXN2_135 +#set_property PACKAGE_PIN D52 [get_ports "QSFP1_RX4_N"] ;# Bank 135 - MGTYRXN3_135 +#set_property PACKAGE_PIN G53 [get_ports "QSFP1_RX1_P"] ;# Bank 135 - MGTYRXP0_135 +#set_property PACKAGE_PIN F51 [get_ports "QSFP1_RX2_P"] ;# Bank 135 - MGTYRXP1_135 +#set_property PACKAGE_PIN E53 [get_ports "QSFP1_RX3_P"] ;# Bank 135 - MGTYRXP2_135 +#set_property PACKAGE_PIN D51 [get_ports "QSFP1_RX4_P"] ;# Bank 135 - MGTYRXP3_135 +#set_property PACKAGE_PIN G49 [get_ports "QSFP1_TX1_N"] ;# Bank 135 - MGTYTXN0_135 +#set_property PACKAGE_PIN E49 [get_ports "QSFP1_TX2_N"] ;# Bank 135 - MGTYTXN1_135 +#set_property PACKAGE_PIN C49 [get_ports "QSFP1_TX3_N"] ;# Bank 135 - MGTYTXN2_135 +#set_property PACKAGE_PIN A50 [get_ports "QSFP1_TX4_N"] ;# Bank 135 - MGTYTXN3_135 +#set_property PACKAGE_PIN G48 [get_ports "QSFP1_TX1_P"] ;# Bank 135 - MGTYTXP0_135 +#set_property PACKAGE_PIN E48 [get_ports "QSFP1_TX2_P"] ;# Bank 135 - MGTYTXP1_135 +#set_property PACKAGE_PIN C48 [get_ports "QSFP1_TX3_P"] ;# Bank 135 - MGTYTXP2_135 +#set_property PACKAGE_PIN A49 [get_ports "QSFP1_TX4_P"] ;# Bank 135 - MGTYTXP3_135 +#set_property PACKAGE_PIN AV12 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK0N_224 +#set_property PACKAGE_PIN AV13 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK0P_224 +#set_property PACKAGE_PIN AT12 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK1N_224 +#set_property PACKAGE_PIN AT13 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK1P_224 +#set_property PACKAGE_PIN BC1 [get_ports "PCIE_EP_RX15_N"] ;# Bank 224 - MGTYRXN0_224 +#set_property PACKAGE_PIN BB3 [get_ports "PCIE_EP_RX14_N"] ;# Bank 224 - MGTYRXN1_224 +#set_property PACKAGE_PIN BA1 [get_ports "PCIE_EP_RX13_N"] ;# Bank 224 - MGTYRXN2_224 +#set_property PACKAGE_PIN BA5 [get_ports "PCIE_EP_RX12_N"] ;# Bank 224 - MGTYRXN3_224 +#set_property PACKAGE_PIN BC2 [get_ports "PCIE_EP_RX15_P"] ;# Bank 224 - MGTYRXP0_224 +#set_property PACKAGE_PIN BB4 [get_ports "PCIE_EP_RX14_P"] ;# Bank 224 - MGTYRXP1_224 +#set_property PACKAGE_PIN BA2 [get_ports "PCIE_EP_RX13_P"] ;# Bank 224 - MGTYRXP2_224 +#set_property PACKAGE_PIN BA6 [get_ports "PCIE_EP_RX12_P"] ;# Bank 224 - MGTYRXP3_224 +#set_property PACKAGE_PIN BC6 [get_ports "PCIE_EP_TX15_N"] ;# Bank 224 - MGTYTXN0_224 +#set_property PACKAGE_PIN BC10 [get_ports "PCIE_EP_TX14_N"] ;# Bank 224 - MGTYTXN1_224 +#set_property PACKAGE_PIN BB8 [get_ports "PCIE_EP_TX13_N"] ;# Bank 224 - MGTYTXN2_224 +#set_property PACKAGE_PIN BA10 [get_ports "PCIE_EP_TX12_N"] ;# Bank 224 - MGTYTXN3_224 +#set_property PACKAGE_PIN BC7 [get_ports "PCIE_EP_TX15_P"] ;# Bank 224 - MGTYTXP0_224 +#set_property PACKAGE_PIN BC11 [get_ports "PCIE_EP_TX14_P"] ;# Bank 224 - MGTYTXP1_224 +#set_property PACKAGE_PIN BB9 [get_ports "PCIE_EP_TX13_P"] ;# Bank 224 - MGTYTXP2_224 +#set_property PACKAGE_PIN BA11 [get_ports "PCIE_EP_TX12_P"] ;# Bank 224 - MGTYTXP3_224 +#set_property PACKAGE_PIN AR14 [get_ports "PCIE_CLK1_N"] ;# Bank 225 - MGTREFCLK0N_225 +#set_property PACKAGE_PIN AR15 [get_ports "PCIE_CLK1_P"] ;# Bank 225 - MGTREFCLK0P_225 +#set_property PACKAGE_PIN AP12 [get_ports "No Connect"] ;# Bank 225 - MGTREFCLK1N_225 +#set_property PACKAGE_PIN AP13 [get_ports "No Connect"] ;# Bank 225 - MGTREFCLK1P_225 +#set_property PACKAGE_PIN AU14 [get_ports "N22119509"] ;# Bank 225 - MGTRREF_RS +#set_property PACKAGE_PIN AY3 [get_ports "PCIE_EP_RX11_N"] ;# Bank 225 - MGTYRXN0_225 +#set_property PACKAGE_PIN AW1 [get_ports "PCIE_EP_RX10_N"] ;# Bank 225 - MGTYRXN1_225 +#set_property PACKAGE_PIN AW5 [get_ports "PCIE_EP_RX9_N"] ;# Bank 225 - MGTYRXN2_225 +#set_property PACKAGE_PIN AV3 [get_ports "PCIE_EP_RX8_N"] ;# Bank 225 - MGTYRXN3_225 +#set_property PACKAGE_PIN AY4 [get_ports "PCIE_EP_RX11_P"] ;# Bank 225 - MGTYRXP0_225 +#set_property PACKAGE_PIN AW2 [get_ports "PCIE_EP_RX10_P"] ;# Bank 225 - MGTYRXP1_225 +#set_property PACKAGE_PIN AW6 [get_ports "PCIE_EP_RX9_P"] ;# Bank 225 - MGTYRXP2_225 +#set_property PACKAGE_PIN AV4 [get_ports "PCIE_EP_RX8_P"] ;# Bank 225 - MGTYRXP3_225 +#set_property PACKAGE_PIN AY8 [get_ports "PCIE_EP_TX11_N"] ;# Bank 225 - MGTYTXN0_225 +#set_property PACKAGE_PIN AW10 [get_ports "PCIE_EP_TX10_N"] ;# Bank 225 - MGTYTXN1_225 +#set_property PACKAGE_PIN AV8 [get_ports "PCIE_EP_TX9_N"] ;# Bank 225 - MGTYTXN2_225 +#set_property PACKAGE_PIN AU6 [get_ports "PCIE_EP_TX8_N"] ;# Bank 225 - MGTYTXN3_225 +#set_property PACKAGE_PIN AY9 [get_ports "PCIE_EP_TX11_P"] ;# Bank 225 - MGTYTXP0_225 +#set_property PACKAGE_PIN AW11 [get_ports "PCIE_EP_TX10_P"] ;# Bank 225 - MGTYTXP1_225 +#set_property PACKAGE_PIN AV9 [get_ports "PCIE_EP_TX9_P"] ;# Bank 225 - MGTYTXP2_225 +#set_property PACKAGE_PIN AU7 [get_ports "PCIE_EP_TX8_P"] ;# Bank 225 - MGTYTXP3_225 +#set_property PACKAGE_PIN AN14 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK0N_226 +#set_property PACKAGE_PIN AN15 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK0P_226 +#set_property PACKAGE_PIN AM12 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK1N_226 +#set_property PACKAGE_PIN AM13 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK1P_226 +#set_property PACKAGE_PIN AU1 [get_ports "PCIE_EP_RX7_N"] ;# Bank 226 - MGTYRXN0_226 +#set_property PACKAGE_PIN AT3 [get_ports "PCIE_EP_RX6_N"] ;# Bank 226 - MGTYRXN1_226 +#set_property PACKAGE_PIN AR1 [get_ports "PCIE_EP_RX5_N"] ;# Bank 226 - MGTYRXN2_226 +#set_property PACKAGE_PIN AP3 [get_ports "PCIE_EP_RX4_N"] ;# Bank 226 - MGTYRXN3_226 +#set_property PACKAGE_PIN AU2 [get_ports "PCIE_EP_RX7_P"] ;# Bank 226 - MGTYRXP0_226 +#set_property PACKAGE_PIN AT4 [get_ports "PCIE_EP_RX6_P"] ;# Bank 226 - MGTYRXP1_226 +#set_property PACKAGE_PIN AR2 [get_ports "PCIE_EP_RX5_P"] ;# Bank 226 - MGTYRXP2_226 +#set_property PACKAGE_PIN AP4 [get_ports "PCIE_EP_RX4_P"] ;# Bank 226 - MGTYRXP3_226 +#set_property PACKAGE_PIN AU10 [get_ports "PCIE_EP_TX7_N"] ;# Bank 226 - MGTYTXN0_226 +#set_property PACKAGE_PIN AT8 [get_ports "PCIE_EP_TX6_N"] ;# Bank 226 - MGTYTXN1_226 +#set_property PACKAGE_PIN AR6 [get_ports "PCIE_EP_TX5_N"] ;# Bank 226 - MGTYTXN2_226 +#set_property PACKAGE_PIN AR10 [get_ports "PCIE_EP_TX4_N"] ;# Bank 226 - MGTYTXN3_226 +#set_property PACKAGE_PIN AU11 [get_ports "PCIE_EP_TX7_P"] ;# Bank 226 - MGTYTXP0_226 +#set_property PACKAGE_PIN AT9 [get_ports "PCIE_EP_TX6_P"] ;# Bank 226 - MGTYTXP1_226 +#set_property PACKAGE_PIN AR7 [get_ports "PCIE_EP_TX5_P"] ;# Bank 226 - MGTYTXP2_226 +#set_property PACKAGE_PIN AR11 [get_ports "PCIE_EP_TX4_P"] ;# Bank 226 - MGTYTXP3_226 +#set_property PACKAGE_PIN AL14 [get_ports "PCIE_CLK2_N"] ;# Bank 227 - MGTREFCLK0N_227 +#set_property PACKAGE_PIN AL15 [get_ports "PCIE_CLK2_P"] ;# Bank 227 - MGTREFCLK0P_227 +#set_property PACKAGE_PIN AK12 [get_ports "No Connect"] ;# Bank 227 - MGTREFCLK1N_227 +#set_property PACKAGE_PIN AK13 [get_ports "No Connect"] ;# Bank 227 - MGTREFCLK1P_227 +#set_property PACKAGE_PIN AN1 [get_ports "PCIE_EP_RX3_N"] ;# Bank 227 - MGTYRXN0_227 +#set_property PACKAGE_PIN AN5 [get_ports "PCIE_EP_RX2_N"] ;# Bank 227 - MGTYRXN1_227 +#set_property PACKAGE_PIN AM3 [get_ports "PCIE_EP_RX1_N"] ;# Bank 227 - MGTYRXN2_227 +#set_property PACKAGE_PIN AL1 [get_ports "PCIE_EP_RX0_N"] ;# Bank 227 - MGTYRXN3_227 +#set_property PACKAGE_PIN AN2 [get_ports "PCIE_EP_RX3_P"] ;# Bank 227 - MGTYRXP0_227 +#set_property PACKAGE_PIN AN6 [get_ports "PCIE_EP_RX2_P"] ;# Bank 227 - MGTYRXP1_227 +#set_property PACKAGE_PIN AM4 [get_ports "PCIE_EP_RX1_P"] ;# Bank 227 - MGTYRXP2_227 +#set_property PACKAGE_PIN AL2 [get_ports "PCIE_EP_RX0_P"] ;# Bank 227 - MGTYRXP3_227 +#set_property PACKAGE_PIN AP8 [get_ports "PCIE_EP_TX3_N"] ;# Bank 227 - MGTYTXN0_227 +#set_property PACKAGE_PIN AN10 [get_ports "PCIE_EP_TX2_N"] ;# Bank 227 - MGTYTXN1_227 +#set_property PACKAGE_PIN AM8 [get_ports "PCIE_EP_TX1_N"] ;# Bank 227 - MGTYTXN2_227 +#set_property PACKAGE_PIN AL10 [get_ports "PCIE_EP_TX0_N"] ;# Bank 227 - MGTYTXN3_227 +#set_property PACKAGE_PIN AP9 [get_ports "PCIE_EP_TX3_P"] ;# Bank 227 - MGTYTXP0_227 +#set_property PACKAGE_PIN AN11 [get_ports "PCIE_EP_TX2_P"] ;# Bank 227 - MGTYTXP1_227 +#set_property PACKAGE_PIN AM9 [get_ports "PCIE_EP_TX1_P"] ;# Bank 227 - MGTYTXP2_227 +#set_property PACKAGE_PIN AL11 [get_ports "PCIE_EP_TX0_P"] ;# Bank 227 - MGTYTXP3_227 +#set_property PACKAGE_PIN AJ14 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK0N_228 +#set_property PACKAGE_PIN AJ15 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK0P_228 +#set_property PACKAGE_PIN AH12 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK1N_228 +#set_property PACKAGE_PIN AH13 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK1P_228 +#set_property PACKAGE_PIN AL5 [get_ports "GND"] ;# Bank 228 - MGTYRXN0_228 +#set_property PACKAGE_PIN AK3 [get_ports "GND"] ;# Bank 228 - MGTYRXN1_228 +#set_property PACKAGE_PIN AJ1 [get_ports "GND"] ;# Bank 228 - MGTYRXN2_228 +#set_property PACKAGE_PIN AH3 [get_ports "GND"] ;# Bank 228 - MGTYRXN3_228 +#set_property PACKAGE_PIN AL6 [get_ports "GND"] ;# Bank 228 - MGTYRXP0_228 +#set_property PACKAGE_PIN AK4 [get_ports "GND"] ;# Bank 228 - MGTYRXP1_228 +#set_property PACKAGE_PIN AJ2 [get_ports "GND"] ;# Bank 228 - MGTYRXP2_228 +#set_property PACKAGE_PIN AH4 [get_ports "GND"] ;# Bank 228 - MGTYRXP3_228 +#set_property PACKAGE_PIN AK8 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN0_228 +#set_property PACKAGE_PIN AJ6 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN1_228 +#set_property PACKAGE_PIN AJ10 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN2_228 +#set_property PACKAGE_PIN AH8 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN3_228 +#set_property PACKAGE_PIN AK9 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP0_228 +#set_property PACKAGE_PIN AJ7 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP1_228 +#set_property PACKAGE_PIN AJ11 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP2_228 +#set_property PACKAGE_PIN AH9 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP3_228 +#set_property PACKAGE_PIN AG14 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK0N_229 +#set_property PACKAGE_PIN AG15 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK0P_229 +#set_property PACKAGE_PIN AF12 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK1N_229 +#set_property PACKAGE_PIN AF13 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK1P_229 +#set_property PACKAGE_PIN AE14 [get_ports "N22480070"] ;# Bank 229 - MGTRREF_RC +#set_property PACKAGE_PIN AG1 [get_ports "GND"] ;# Bank 229 - MGTYRXN0_229 +#set_property PACKAGE_PIN AF3 [get_ports "GND"] ;# Bank 229 - MGTYRXN1_229 +#set_property PACKAGE_PIN AE1 [get_ports "GND"] ;# Bank 229 - MGTYRXN2_229 +#set_property PACKAGE_PIN AE5 [get_ports "GND"] ;# Bank 229 - MGTYRXN3_229 +#set_property PACKAGE_PIN AG2 [get_ports "GND"] ;# Bank 229 - MGTYRXP0_229 +#set_property PACKAGE_PIN AF4 [get_ports "GND"] ;# Bank 229 - MGTYRXP1_229 +#set_property PACKAGE_PIN AE2 [get_ports "GND"] ;# Bank 229 - MGTYRXP2_229 +#set_property PACKAGE_PIN AE6 [get_ports "GND"] ;# Bank 229 - MGTYRXP3_229 +#set_property PACKAGE_PIN AG6 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN0_229 +#set_property PACKAGE_PIN AG10 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN1_229 +#set_property PACKAGE_PIN AF8 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN2_229 +#set_property PACKAGE_PIN AE10 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN3_229 +#set_property PACKAGE_PIN AG7 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP0_229 +#set_property PACKAGE_PIN AG11 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP1_229 +#set_property PACKAGE_PIN AF9 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP2_229 +#set_property PACKAGE_PIN AE11 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP3_229 +#set_property PACKAGE_PIN AD12 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK0N_230 +#set_property PACKAGE_PIN AD13 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK0P_230 +#set_property PACKAGE_PIN AC14 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK1N_230 +#set_property PACKAGE_PIN AC15 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK1P_230 +#set_property PACKAGE_PIN AD3 [get_ports "GND"] ;# Bank 230 - MGTYRXN0_230 +#set_property PACKAGE_PIN AC1 [get_ports "GND"] ;# Bank 230 - MGTYRXN1_230 +#set_property PACKAGE_PIN AC5 [get_ports "GND"] ;# Bank 230 - MGTYRXN2_230 +#set_property PACKAGE_PIN AB3 [get_ports "GND"] ;# Bank 230 - MGTYRXN3_230 +#set_property PACKAGE_PIN AD4 [get_ports "GND"] ;# Bank 230 - MGTYRXP0_230 +#set_property PACKAGE_PIN AC2 [get_ports "GND"] ;# Bank 230 - MGTYRXP1_230 +#set_property PACKAGE_PIN AC6 [get_ports "GND"] ;# Bank 230 - MGTYRXP2_230 +#set_property PACKAGE_PIN AB4 [get_ports "GND"] ;# Bank 230 - MGTYRXP3_230 +#set_property PACKAGE_PIN AD8 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN0_230 +#set_property PACKAGE_PIN AC10 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN1_230 +#set_property PACKAGE_PIN AB8 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN2_230 +#set_property PACKAGE_PIN AA6 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN3_230 +#set_property PACKAGE_PIN AD9 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP0_230 +#set_property PACKAGE_PIN AC11 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP1_230 +#set_property PACKAGE_PIN AB9 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP2_230 +#set_property PACKAGE_PIN AA7 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP3_230 +#set_property PACKAGE_PIN AB12 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK0N_231 +#set_property PACKAGE_PIN AB13 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK0P_231 +#set_property PACKAGE_PIN AA14 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK1N_231 +#set_property PACKAGE_PIN AA15 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK1P_231 +#set_property PACKAGE_PIN AA1 [get_ports "GND"] ;# Bank 231 - MGTYRXN0_231 +#set_property PACKAGE_PIN Y3 [get_ports "GND"] ;# Bank 231 - MGTYRXN1_231 +#set_property PACKAGE_PIN W1 [get_ports "GND"] ;# Bank 231 - MGTYRXN2_231 +#set_property PACKAGE_PIN V3 [get_ports "GND"] ;# Bank 231 - MGTYRXN3_231 +#set_property PACKAGE_PIN AA2 [get_ports "GND"] ;# Bank 231 - MGTYRXP0_231 +#set_property PACKAGE_PIN Y4 [get_ports "GND"] ;# Bank 231 - MGTYRXP1_231 +#set_property PACKAGE_PIN W2 [get_ports "GND"] ;# Bank 231 - MGTYRXP2_231 +#set_property PACKAGE_PIN V4 [get_ports "GND"] ;# Bank 231 - MGTYRXP3_231 +#set_property PACKAGE_PIN AA10 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN0_231 +#set_property PACKAGE_PIN Y8 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN1_231 +#set_property PACKAGE_PIN W6 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN2_231 +#set_property PACKAGE_PIN W10 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN3_231 +#set_property PACKAGE_PIN AA11 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP0_231 +#set_property PACKAGE_PIN Y9 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP1_231 +#set_property PACKAGE_PIN W7 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP2_231 +#set_property PACKAGE_PIN W11 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP3_231 +#set_property PACKAGE_PIN Y12 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK0N_232 +#set_property PACKAGE_PIN Y13 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK0P_232 +#set_property PACKAGE_PIN W14 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK1N_232 +#set_property PACKAGE_PIN W15 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK1P_232 +#set_property PACKAGE_PIN U1 [get_ports "GND"] ;# Bank 232 - MGTYRXN0_232 +#set_property PACKAGE_PIN U5 [get_ports "GND"] ;# Bank 232 - MGTYRXN1_232 +#set_property PACKAGE_PIN T3 [get_ports "GND"] ;# Bank 232 - MGTYRXN2_232 +#set_property PACKAGE_PIN R1 [get_ports "GND"] ;# Bank 232 - MGTYRXN3_232 +#set_property PACKAGE_PIN U2 [get_ports "GND"] ;# Bank 232 - MGTYRXP0_232 +#set_property PACKAGE_PIN U6 [get_ports "GND"] ;# Bank 232 - MGTYRXP1_232 +#set_property PACKAGE_PIN T4 [get_ports "GND"] ;# Bank 232 - MGTYRXP2_232 +#set_property PACKAGE_PIN R2 [get_ports "GND"] ;# Bank 232 - MGTYRXP3_232 +#set_property PACKAGE_PIN V8 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN0_232 +#set_property PACKAGE_PIN U10 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN1_232 +#set_property PACKAGE_PIN T8 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN2_232 +#set_property PACKAGE_PIN R10 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN3_232 +#set_property PACKAGE_PIN V9 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP0_232 +#set_property PACKAGE_PIN U11 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP1_232 +#set_property PACKAGE_PIN T9 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP2_232 +#set_property PACKAGE_PIN R11 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP3_232 +#set_property PACKAGE_PIN V12 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK0N_233 +#set_property PACKAGE_PIN V13 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK0P_233 +#set_property PACKAGE_PIN U14 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK1N_233 +#set_property PACKAGE_PIN U15 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK1P_233 +#set_property PACKAGE_PIN N14 [get_ports "N22119643"] ;# Bank 233 - MGTRREF_RN +#set_property PACKAGE_PIN R5 [get_ports "GND"] ;# Bank 233 - MGTYRXN0_233 +#set_property PACKAGE_PIN P3 [get_ports "GND"] ;# Bank 233 - MGTYRXN1_233 +#set_property PACKAGE_PIN N1 [get_ports "GND"] ;# Bank 233 - MGTYRXN2_233 +#set_property PACKAGE_PIN M3 [get_ports "GND"] ;# Bank 233 - MGTYRXN3_233 +#set_property PACKAGE_PIN R6 [get_ports "GND"] ;# Bank 233 - MGTYRXP0_233 +#set_property PACKAGE_PIN P4 [get_ports "GND"] ;# Bank 233 - MGTYRXP1_233 +#set_property PACKAGE_PIN N2 [get_ports "GND"] ;# Bank 233 - MGTYRXP2_233 +#set_property PACKAGE_PIN M4 [get_ports "GND"] ;# Bank 233 - MGTYRXP3_233 +#set_property PACKAGE_PIN P8 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN0_233 +#set_property PACKAGE_PIN N6 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN1_233 +#set_property PACKAGE_PIN N10 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN2_233 +#set_property PACKAGE_PIN M8 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN3_233 +#set_property PACKAGE_PIN P9 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP0_233 +#set_property PACKAGE_PIN N7 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP1_233 +#set_property PACKAGE_PIN N11 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP2_233 +#set_property PACKAGE_PIN M9 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP3_233 +#set_property PACKAGE_PIN T12 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK0N_234 +#set_property PACKAGE_PIN T13 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK0P_234 +#set_property PACKAGE_PIN R14 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK1N_234 +#set_property PACKAGE_PIN R15 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK1P_234 +#set_property PACKAGE_PIN L1 [get_ports "GND"] ;# Bank 234 - MGTYRXN0_234 +#set_property PACKAGE_PIN K3 [get_ports "GND"] ;# Bank 234 - MGTYRXN1_234 +#set_property PACKAGE_PIN J1 [get_ports "GND"] ;# Bank 234 - MGTYRXN2_234 +#set_property PACKAGE_PIN H3 [get_ports "GND"] ;# Bank 234 - MGTYRXN3_234 +#set_property PACKAGE_PIN L2 [get_ports "GND"] ;# Bank 234 - MGTYRXP0_234 +#set_property PACKAGE_PIN K4 [get_ports "GND"] ;# Bank 234 - MGTYRXP1_234 +#set_property PACKAGE_PIN J2 [get_ports "GND"] ;# Bank 234 - MGTYRXP2_234 +#set_property PACKAGE_PIN H4 [get_ports "GND"] ;# Bank 234 - MGTYRXP3_234 +#set_property PACKAGE_PIN L6 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN0_234 +#set_property PACKAGE_PIN L10 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN1_234 +#set_property PACKAGE_PIN K8 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN2_234 +#set_property PACKAGE_PIN J6 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN3_234 +#set_property PACKAGE_PIN L7 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP0_234 +#set_property PACKAGE_PIN L11 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP1_234 +#set_property PACKAGE_PIN K9 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP2_234 +#set_property PACKAGE_PIN J7 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP3_234 +#set_property PACKAGE_PIN P12 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK0N_235 +#set_property PACKAGE_PIN P13 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK0P_235 +#set_property PACKAGE_PIN M12 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK1N_235 +#set_property PACKAGE_PIN M13 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK1P_235 +#set_property PACKAGE_PIN G1 [get_ports "GND"] ;# Bank 235 - MGTYRXN0_235 +#set_property PACKAGE_PIN F3 [get_ports "GND"] ;# Bank 235 - MGTYRXN1_235 +#set_property PACKAGE_PIN E1 [get_ports "GND"] ;# Bank 235 - MGTYRXN2_235 +#set_property PACKAGE_PIN D3 [get_ports "GND"] ;# Bank 235 - MGTYRXN3_235 +#set_property PACKAGE_PIN G2 [get_ports "GND"] ;# Bank 235 - MGTYRXP0_235 +#set_property PACKAGE_PIN F4 [get_ports "GND"] ;# Bank 235 - MGTYRXP1_235 +#set_property PACKAGE_PIN E2 [get_ports "GND"] ;# Bank 235 - MGTYRXP2_235 +#set_property PACKAGE_PIN D4 [get_ports "GND"] ;# Bank 235 - MGTYRXP3_235 +#set_property PACKAGE_PIN G6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN0_235 +#set_property PACKAGE_PIN E6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN1_235 +#set_property PACKAGE_PIN C6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN2_235 +#set_property PACKAGE_PIN A5 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN3_235 +#set_property PACKAGE_PIN G7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP0_235 +#set_property PACKAGE_PIN E7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP1_235 +#set_property PACKAGE_PIN C7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP2_235 +#set_property PACKAGE_PIN A6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP3_235 + +set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] +set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] +set_property PACKAGE_PIN BH51 [get_ports sys_clk_p] +set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n] + +#set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +#connect_debug_port dbg_hub/clk [get_nets clk] diff --git a/target/xilinx/flavor_vanilla/flavor_vanilla.mk b/target/xilinx/flavor_vanilla/flavor_vanilla.mk new file mode 100644 index 00000000..5446ab89 --- /dev/null +++ b/target/xilinx/flavor_vanilla/flavor_vanilla.mk @@ -0,0 +1,62 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +# Output bitstream +xilinx_bit_vanilla := $(CHS_XIL_DIR)/flavor_vanilla/out/cheshire_top_xilinx.bit + +# +# IPs +# + +# This flavor requires pre-compiled Xilinx IPs (which may depend on the board) +xilinx_ips_names_vanilla_vcu128 := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio +xilinx_ips_names_vanilla_genesys2 := xlnx_clk_wiz xlnx_vio xlnx_mig_7_ddr3 +xilinx_ips_names_vanilla := $(xilinx_ips_names_vanilla_${XILINX_BOARD}) +# Path to compiled ips +xilinx_ips_paths_vanilla := $(foreach ip-name,$(xilinx_ips_names_vanilla),$(xilinx_ip_dir)/$(ip-name)/$(ip-name).srcs/sources_1/ip/$(ip-name)/$(ip-name).xci) + +# +# Bender +# + +# Flavor specific bender args +# (add the enabled ips in bender args, used by phy_definitions.svh) +xilinx_targs_vanilla := $(foreach ip-name,$(xilinx_ips_names_vanilla),$(addprefix -t ,$(ip-name))) +xilinx_targs_vanilla += -t xilinx_vanilla + +# Vivado variables +vivado_env_vanilla := \ + XILINX_PROJECT=$(XILINX_PROJECT) \ + XILINX_BOARD=$(XILINX_BOARD) \ + XILINX_PART=$(xilinx_part) \ + XILINX_BOARD_LONG=$(xilinx_board_long) \ + XILINX_PORT=$(XILINX_PORT) \ + XILINX_HOST=$(XILINX_HOST) \ + XILINX_FPGA_PATH=$(XILINX_FPGA_PATH) \ + XILINX_BIT=$(xilinx_bit) \ + XILINX_IP_PATHS="$(xilinx_ips_paths_vanilla)" \ + ROUTED_DCP=$(ROUTED_DCP) \ + XILINX_CHECK_TIMING=$(XILINX_CHECK_TIMING) \ + XILINX_ELABORATION_ONLY=$(XILINX_ELABORATION_ONLY) + +# +# Rules +# + +# Generate bender script +$(CHS_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl: Bender.yml + $(BENDER) script vivado $(xilinx_targs) $(xilinx_targs_vanilla) > $@ + +# Compile bitstream +$(CHS_XIL_DIR)/flavor_vanilla/out/%.bit: $(xilinx_ips_paths_vanilla) $(CHS_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl + @mkdir -p $(CHS_XIL_DIR)/flavor_vanilla/out + cd $(CHS_XIL_DIR)/flavor_vanilla && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl + find $(CHS_XIL_DIR)/flavor_vanilla -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CHS_XIL_DIR)/flavor_vanilla/out + +chs-xil-clean-vanilla: + cd $(CHS_XIL_DIR)/flavor_vanilla && rm -rf scripts/add_sources.tcl* *.log *.jou *.str *.mif carfield.* .Xil/ + +.PHONY: chs-xil-clean-vanilla \ No newline at end of file diff --git a/target/xilinx/flavor_vanilla/scripts/run.tcl b/target/xilinx/flavor_vanilla/scripts/run.tcl new file mode 100644 index 00000000..d0a83baf --- /dev/null +++ b/target/xilinx/flavor_vanilla/scripts/run.tcl @@ -0,0 +1,141 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Florian Zaruba +# Nils Wistoff +# Cyril Koenig + +set project $::env(XILINX_PROJECT) + +create_project $project . -force -part $::env(XILINX_PART) +set_property board_part $::env(XILINX_BOARD_LONG) [current_project] + +# set number of threads to 8 (maximum, unfortunately) +set_param general.maxThreads 8 + +# Ips selection +read_ip $::env(XILINX_IP_PATHS) + +# Contraints files selection +switch $::env(XILINX_BOARD) { + "genesys2" - "kc705" - "vc707" - "vcu128" - "zcu102" { + import_files -fileset constrs_1 -norecurse constraints/cheshire.xdc + import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc + } + default { + exit 1 + } +} + +source scripts/add_sources.tcl + +set_property top ${project}_top_xilinx [current_fileset] + +update_compile_order -fileset sources_1 + +set_property strategy Flow_PerfOptimized_high [get_runs synth_1] +set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] + +set_property XPM_LIBRARIES XPM_MEMORY [current_project] + +synth_design -rtl -name rtl_1 + +set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] + +# Synthesis +launch_runs synth_1 +wait_on_run synth_1 +open_run synth_1 -name synth_1 + +exec mkdir -p reports/ +exec rm -rf reports/* + +check_timing -verbose -file reports/$project.check_timing.rpt +report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt +report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt +report_utilization -hierarchical -file reports/$project.utilization.rpt +report_cdc -file reports/$project.cdc.rpt +report_clock_interaction -file reports/$project.clock_interaction.rpt + +# Remove black-boxed unreads +remove_cell [get_cells -hier -filter {ORIG_REF_NAME == "unread" || REF_NAME == "unread"}] + +# Instantiate ILA +set DEBUG [llength [get_nets -hier -filter {MARK_DEBUG == 1}]] +if ($DEBUG) { + # Create core + puts "Creating debug core..." + create_debug_core u_ila_0 ila + set_property -dict "ALL_PROBE_SAME_MU true ALL_PROBE_SAME_MU_CNT 4 C_ADV_TRIGGER true C_DATA_DEPTH 16384 \ + C_EN_STRG_QUAL true C_INPUT_PIPE_STAGES 0 C_TRIGIN_EN false C_TRIGOUT_EN false" [get_debug_cores u_ila_0] + ## Clock + set_property port_width 1 [get_debug_ports u_ila_0/clk] + connect_debug_port u_ila_0/clk [get_nets soc_clk] + # Get nets to debug + set debugNets [lsort -dictionary [get_nets -hier -filter {MARK_DEBUG == 1}]] + set netNameLast "" + set probe_i 0 + # Loop through all nets (add extra list element to ensure last net is processed) + foreach net [concat $debugNets {""}] { + # Remove trailing array index + regsub {\[[0-9]*\]$} $net {} netName + # Create probe after all signals with the same name have been collected + if {$netNameLast != $netName} { + if {$netNameLast != ""} { + puts "Creating probe $probe_i with width [llength $sigList] for signal '$netNameLast'" + # probe0 already exists, and does not need to be created + if {$probe_i != 0} { + create_debug_port u_ila_0 probe + } + set_property port_width [llength $sigList] [get_debug_ports u_ila_0/probe$probe_i] + set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe$probe_i] + connect_debug_port u_ila_0/probe$probe_i [get_nets $sigList] + incr probe_i + } + set sigList "" + } + lappend sigList $net + set netNameLast $netName + } + # Need to save save constraints before implementing the core + # set_property target_constrs_file cheshire.srcs/constrs_1/imports/constraints/$::env(XILINX_BOARD).xdc [current_fileset -constrset] + save_constraints -force + implement_debug_core + write_debug_probes -force probes.ltx +} + +# Incremental implementation +if {[info exists ::env(XILINX_ROUTED_DCP)] && [file exists $::env(XILINX_ROUTED_DCP)]} { + set_property incremental_checkpoint $ $::env(XILINX_ROUTED_DCP) [get_runs impl_1] +} + +# Implementation +launch_runs impl_1 +wait_on_run impl_1 +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 + +# Check timing constraints +set timingrep [report_timing_summary -no_header -no_detailed_paths -return_string] +if {[info exists ::env(CHECK_TIMING)] && $::env(XILINX_CHECK_TIMING)==1} { + if {! [string match -nocase {*timing constraints are met*} $timingrep]} { + send_msg_id {USER 1-1} ERROR {Timing constraints were not met.} + return -code error + } +} + +# Output Verilog netlist + SDC for timing simulation +if {[info exists ::env(EXPORT_SDF)] && $::env(XILINX_EXPORT_SDF)==1} { + write_verilog -force -mode funcsim out/${project}_funcsim.v + write_verilog -force -mode timesim out/${project}_timesim.v + write_sdf -force out/${project}_timesim.sdf +} + +# Reports +exec mkdir -p reports/ +exec rm -rf reports/* +check_timing -file reports/${project}.check_timing.rpt +report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt +report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt +report_utilization -hierarchical -file reports/${project}.utilization.rpt diff --git a/target/xilinx/flavor_vanilla/sim/run_simulation.tcl b/target/xilinx/flavor_vanilla/sim/run_simulation.tcl new file mode 100644 index 00000000..b0260460 --- /dev/null +++ b/target/xilinx/flavor_vanilla/sim/run_simulation.tcl @@ -0,0 +1,48 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +source ../scripts/add_sources_vsim.tcl + +if {[string first "xlnx_clk_wiz" $::env(IPS)] != -1} { + source ips/xlnx_clk_wiz/questa/compile.do + +if {[string first "xlnx_vio" $::env(IPS)] != -1} { + source ips/xlnx_vio/questa/compile.do +}} + +if {[string first "xlnx_mig_7_ddr3" $::env(IPS)] != -1} { + source ips/xlnx_mig_7_ddr3_ex/questa/compile.do + source ips/xlnx_mig_7_ddr3/questa/compile.do + vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_7_ddr3_ex/questa/srcs/sim_tb_top.v" +} + +if {[string first "xlnx_mig_ddr4" $::env(IPS)] != -1} { + source ips/xlnx_mig_ddr4_ex/questa/compile.do + source ips/xlnx_mig_ddr4/questa/compile.do + vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_ddr4_ex/questa/srcs/sim_tb_top.sv" +} + +# Note : this testbench does not implenent the ddr4 memory model +set TESTBENCH "work.sim_tb_top xil_defaultlib.glbl" + +set XLIB_ARGS "-L secureip -L xpm -L unisims_ver -L unimacro_ver -L work -L xil_defaultlib" + +if {![info exists VOPTARGS]} { + set VOPTARGS "+acc" +} + +set flags "-permissive -suppress 3009 -suppress 8386 -error 7" + +set pargs "" +if {[info exists BOOTMODE]} { append pargs "+BOOTMODE=${BOOTMODE} " } +if {[info exists PRELMODE]} { append pargs "+PRELMODE=${PRELMODE} " } +if {[info exists BINARY]} { append pargs "+BINARY=${BINARY} " } +if {[info exists IMAGE]} { append pargs "+IMAGE=${IMAGE} " } + +eval "vsim ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${XLIB_ARGS} ${pargs} ${flags} + +set StdArithNoWarnings 1 +set NumericStdNoWarnings 1 diff --git a/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl b/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl new file mode 100644 index 00000000..a14d1b92 --- /dev/null +++ b/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl @@ -0,0 +1,32 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set command "" +set script_path [ file dirname [ file normalize [ info script ] ] ] + +if { $argc == 1 } { + set command [lindex $argv 0] +} + +puts "Running with SIMULATOR_PATH=$::env(SIMULATOR_PATH) ; GCC_PATH=$::env(GCC_PATH) ; XILINX_SIMLIB_PATH=$::env(XILINX_SIMLIB_PATH)" + +# Compile the vivado simlib to XILINX_SIMLIB_PATH +if { $command == "compile_simlib" } { + set command "compile_simlib -simulator questa -simulator_exec_path {$::env(SIMULATOR_PATH)} \ + -gcc_exec_path {$::env(GCC_PATH)} -family all -language verilog -library all -dir {$::env(XILINX_SIMLIB_PATH)} -force" + # For some reason this command does not work well when not eval from the string + eval $command + +# Export simulation scripts for each ip +} elseif { $command == "export_simulation" } { + open_project $::env(VIVADO_PROJECT) + export_simulation -simulator questa -directory "./ips" -lib_map_path "$::env(XILINX_SIMLIB_PATH)" \ + -absolute_path -force -of_objects [get_ips *] + +# Unknown command +} else { + puts "[$argv0] Unknown command: $command" +} diff --git a/target/xilinx/flavor_vanilla/sim/sim.mk b/target/xilinx/flavor_vanilla/sim/sim.mk new file mode 100644 index 00000000..72449d83 --- /dev/null +++ b/target/xilinx/flavor_vanilla/sim/sim.mk @@ -0,0 +1,58 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +CHS_XIL_SIM_DIR ?= $(CHS_XIL_DIR)/sim + +XILINX_SIMLIB_PATH ?= /home/$(USER)/xlib_questa-2022.3_vivado-2022.1 +SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin +GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin + +ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names))) + +# Pre-generated/modified example projects (contain the simulation top level) +ifneq ($(filter xlnx_mig_ddr4,$(ips-names)),) + ip-example-projects := xlnx_mig_ddr4_ex +endif +ifneq ($(filter xlnx_mig_7_ddr3,$(ips-names)),) + ip-example-projects := xlnx_mig_7_ddr3_ex +endif + +ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ip-example-projects))) + +VIVADOENV_SIM := $(VIVADOENV) \ + XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \ + SIMULATOR_PATH=$(SIMULATOR_PATH) \ + GCC_PATH=$(GCC_PATH) \ + VIVADO_PROJECT=../${PROJECT}.xpr +VLOG_ARGS := -suppress 2583 -suppress 13314 + +# Fetch example projects at IIS (containing SRAM behavioral models) +$(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: + mkdir -p $(CHS_XIL_SIM_DIR)/ips + tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C $(CHS_XIL_SIM_DIR)/ips + +# Generate simulation libraries +$(XILINX_SIMLIB_PATH)/modelsim.ini: + cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" + +# +$(CHS_XIL_SIM_DIR)/ips/%/questa/compile.do: + mkdir -p $(CHS_XIL_SIM_DIR)/ips + cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" + +$(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl: + $(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(VLOG_ARGS)" > $@ + +chs-xil-sim: $(CHS_XIL_DIR)/${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) $(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl + mkdir -p $(CHS_XIL_SIM_DIR)/questa_lib + cp $(XILINX_SIMLIB_PATH)/modelsim.ini $(CHS_XIL_SIM_DIR) + chmod +w $(CHS_XIL_SIM_DIR)/modelsim.ini + cd $(CHS_XIL_SIM_DIR) && IPS="$(ips-names)" questa-2022.3 vsim -work work -do "run_simulation.tcl" + +chs-xil-clean-sim: + cd $(CHS_XIL_DIR) && rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini + +.PHONY: clean-sim sim diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/flavor_vanilla/src/cheshire_top_xilinx.sv similarity index 51% rename from target/xilinx/src/cheshire_top_xilinx.sv rename to target/xilinx/flavor_vanilla/src/cheshire_top_xilinx.sv index 188e0ce3..402fd68a 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/cheshire_top_xilinx.sv @@ -1,69 +1,99 @@ -// Copyright 2022 ETH Zurich and University of Bologna. +// Copyright 2023 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // // Nicole Narr // Christopher Reinwardt +// Cyril Koenig +// Yann Picod `include "cheshire/typedef.svh" +`include "phy_definitions.svh" module cheshire_top_xilinx import cheshire_pkg::*; ( - input logic sysclk_p, - input logic sysclk_n, +`ifdef USE_RESET + input logic cpu_reset, +`endif +`ifdef USE_RESETN input logic cpu_resetn, +`endif - input logic test_mode_i, + // System clock for clk_wiz + input logic sys_clk_p, + input logic sys_clk_n, +`ifdef USE_SWITCHES + input logic testmode_i, input logic [1:0] boot_mode_i, +`endif - output logic uart_tx_o, - input logic uart_rx_i, - +`ifdef USE_JTAG input logic jtag_tck_i, - input logic jtag_trst_ni, input logic jtag_tms_i, input logic jtag_tdi_i, output logic jtag_tdo_o, - +`ifdef USE_JTAG_TRSTN + input logic jtag_trst_ni, +`endif +`ifdef USE_JTAG_VDDGND + output logic jtag_vdd_o, + output logic jtag_gnd_o, +`endif +`endif + +`ifdef USE_I2C inout wire i2c_scl_io, inout wire i2c_sda_io, +`endif +`ifdef USE_SD input logic sd_cd_i, output logic sd_cmd_o, inout wire [3:0] sd_d_io, output logic sd_reset_o, output logic sd_sclk_o, +`endif +`ifdef USE_FAN input logic [3:0] fan_sw, output logic fan_pwm, +`endif - // DDR3 DRAM interface - output wire [14:0] ddr3_addr, - output wire [2:0] ddr3_ba, - output wire ddr3_cas_n, - output wire [0:0] ddr3_ck_n, - output wire [0:0] ddr3_ck_p, - output wire [0:0] ddr3_cke, - output wire [0:0] ddr3_cs_n, - output wire [3:0] ddr3_dm, - inout wire [31:0] ddr3_dq, - inout wire [3:0] ddr3_dqs_n, - inout wire [3:0] ddr3_dqs_p, - output wire [0:0] ddr3_odt, - output wire ddr3_ras_n, - output wire ddr3_reset_n, - output wire ddr3_we_n, +`ifdef USE_QSPI +`ifndef USE_STARTUPE3 + // TODO: off-chip qspi interface +`endif // USE_STARTUPE3 +`endif // USE_QSPI +`ifdef USE_VGA // VGA Colour signals output logic [4:0] vga_b, output logic [5:0] vga_g, output logic [4:0] vga_r, - // VGA Sync signals output logic vga_hs, - output logic vga_vs + output logic vga_vs, +`endif + +`ifdef USE_SERIAL + // DDR Link + output logic [4:0] ddr_link_o, + output logic ddr_link_clk_o, +`endif + + // Phy interface for DRAMs +`ifdef USE_DDR4 + `DDR4_INTF +`endif +`ifdef USE_DDR3 + `DDR3_INTF +`endif + + output logic uart_tx_o, + input logic uart_rx_i + ); // Configure cheshire for FPGA mapping @@ -157,40 +187,74 @@ module cheshire_top_xilinx localparam cheshire_cfg_t CheshireFPGACfg = FPGACfg; `CHESHIRE_TYPEDEF_ALL(, CheshireFPGACfg) - axi_llc_req_t axi_llc_mst_req, dram_req, dram_req_cdc; - axi_llc_rsp_t axi_llc_mst_rsp, dram_resp, dram_resp_cdc; + axi_llc_req_t axi_llc_mst_req; + axi_llc_rsp_t axi_llc_mst_rsp; - wire dram_clock_out; - wire dram_sync_reset; - wire soc_clk; + /////////////////////////// + // Clk reset definitions // + /////////////////////////// - logic rst_n; + `ifdef USE_RESET + logic cpu_resetn; + assign cpu_resetn = ~cpu_reset; + `elsif USE_RESETN + logic cpu_reset; + assign cpu_reset = ~cpu_resetn; + `endif + logic sys_rst; - // Statically assign the response user signals - // B Channel user - assign dram_resp.b.user = '0; - - // R Channel user - assign dram_resp.r.user = '0; + wire soc_clk; + wire rst_n; /////////////////// - // Clock Divider // + // GPIOs // /////////////////// - clk_int_div #( - .DIV_VALUE_WIDTH ( 4 ), - .DEFAULT_DIV_VALUE ( 4'h4 ), - .ENABLE_CLOCK_IN_RESET ( 1'b0 ) - ) i_sys_clk_div ( - .clk_i ( dram_clock_out ), - .rst_ni ( ~dram_sync_reset ), - .en_i ( 1'b1 ), - .test_mode_en_i ( testmode_i ), - .div_i ( 4'h4 ), - .div_valid_i ( 1'b0 ), - .div_ready_o ( ), - .clk_o ( soc_clk ), - .cycl_count_o ( ) + // Tie off signals if no switches on the board +`ifndef USE_SWITCHES + logic testmode_i; + logic [1:0] boot_mode_i; + assign testmode_i = '0; + assign boot_mode_i = 2'b00; +`endif + + // Give VDD and GND to JTAG dongle +`ifdef USE_JTAG_VDDGND + assign jtag_vdd_o = '1; + assign jtag_gnd_o = '0; +`endif +`ifndef USE_JTAG_TRSTN + logic jtag_trst_ni; + assign jtag_trst_ni = '1; +`endif + + ////////////////// + // Clock Wizard // + ////////////////// + + wire sys_clk; + + // Get from the diff board pins a single ended buffered clock that + // can be sent to clk_wiz and DDR separately (without cascading MMCMs) + // As sys_clk frequency depends on the boards /!\ in IPs configurations + IBUFDS # + ( + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_sys_clk + ( + .I (sys_clk_p), + .IB (sys_clk_n), + .O (sys_clk) + ); + + xlnx_clk_wiz i_xlnx_clk_wiz ( + .clk_in1 ( sys_clk ), + .reset ( '0 ), + .clk_100 ( ), + .clk_50 ( soc_clk ), + .clk_20 ( ), + .clk_10 ( ) ); ///////////////////// @@ -199,133 +263,62 @@ module cheshire_top_xilinx rstgen i_rstgen_main ( .clk_i ( soc_clk ), - .rst_ni ( ~dram_sync_reset ), - .test_mode_i ( test_en ), + .rst_ni ( ~sys_rst ), + .test_mode_i ( testmode_i ), .rst_no ( rst_n ), .init_no ( ) // keep open ); + /////////////////// + // VIOs // + /////////////////// - /////////////////////////////////////////// - // AXI Clock Domain Crossing SoC -> DRAM // - /////////////////////////////////////////// - - axi_cdc #( - .aw_chan_t ( axi_llc_aw_chan_t ), - .w_chan_t ( axi_llc_w_chan_t ), - .b_chan_t ( axi_llc_b_chan_t ), - .ar_chan_t ( axi_llc_ar_chan_t ), - .r_chan_t ( axi_llc_r_chan_t ), - .axi_req_t ( axi_llc_req_t ), - .axi_resp_t ( axi_llc_rsp_t ), - .LogDepth ( 1 ) - ) i_axi_cdc_mig ( - .src_clk_i ( soc_clk ), - .src_rst_ni ( rst_n ), - .src_req_i ( axi_llc_mst_req ), - .src_resp_o ( axi_llc_mst_rsp ), - .dst_clk_i ( dram_clock_out ), - .dst_rst_ni ( rst_n ), - .dst_req_o ( dram_req_cdc ), - .dst_resp_i ( dram_resp_cdc ) - ); + logic vio_reset, vio_boot_mode_sel; + logic [1:0] boot_mode, vio_boot_mode; - // AXI CUT (spill register) between the AXI CDC and the MIG to - // reduce timing pressure - axi_cut #( - .Bypass ( 1'b0 ), - .aw_chan_t ( axi_llc_aw_chan_t ), - .w_chan_t ( axi_llc_w_chan_t ), - .b_chan_t ( axi_llc_b_chan_t ), - .ar_chan_t ( axi_llc_ar_chan_t ), - .r_chan_t ( axi_llc_r_chan_t ), - .axi_req_t ( axi_llc_req_t ), - .axi_resp_t ( axi_llc_rsp_t ) - ) i_axi_cut_soc_dram ( - .clk_i ( dram_clock_out ), - .rst_ni ( rst_n ), - - .slv_req_i ( dram_req_cdc ), - .slv_resp_o ( dram_resp_cdc ), - - .mst_req_o ( dram_req ), - .mst_resp_i ( dram_resp ) +`ifdef USE_VIO + xlnx_vio i_xlnx_vio ( + .clk(soc_clk), + .probe_out0(vio_reset), + .probe_out1(vio_boot_mode), + .probe_out2(vio_boot_mode_sel) ); +`else + assign vio_reset = '0; + assign vio_boot_mode = '0; + assign vio_boot_mode_sel = '0; +`endif + + assign sys_rst = ~cpu_resetn | vio_reset; + assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i; ////////////// // DRAM MIG // ////////////// - xlnx_mig_7_ddr3 i_dram ( - .sys_clk_p ( sysclk_p ), - .sys_clk_n ( sysclk_n ), - .ddr3_dq, - .ddr3_dqs_n, - .ddr3_dqs_p, - .ddr3_addr, - .ddr3_ba, - .ddr3_ras_n, - .ddr3_cas_n, - .ddr3_we_n, - .ddr3_reset_n, - .ddr3_ck_p, - .ddr3_ck_n, - .ddr3_cke, - .ddr3_cs_n, - .ddr3_dm, - .ddr3_odt, - .mmcm_locked ( ), // keep open - .app_sr_req ( '0 ), - .app_ref_req ( '0 ), - .app_zq_req ( '0 ), - .app_sr_active ( ), // keep open - .app_ref_ack ( ), // keep open - .app_zq_ack ( ), // keep open - .ui_clk ( dram_clock_out ), - .ui_clk_sync_rst ( dram_sync_reset ), - .aresetn ( rst_n ), - .s_axi_awid ( dram_req.aw.id ), - .s_axi_awaddr ( dram_req.aw.addr[29:0] ), - .s_axi_awlen ( dram_req.aw.len ), - .s_axi_awsize ( dram_req.aw.size ), - .s_axi_awburst ( dram_req.aw.burst ), - .s_axi_awlock ( dram_req.aw.lock ), - .s_axi_awcache ( dram_req.aw.cache ), - .s_axi_awprot ( dram_req.aw.prot ), - .s_axi_awqos ( dram_req.aw.qos ), - .s_axi_awvalid ( dram_req.aw_valid ), - .s_axi_awready ( dram_resp.aw_ready ), - .s_axi_wdata ( dram_req.w.data ), - .s_axi_wstrb ( dram_req.w.strb ), - .s_axi_wlast ( dram_req.w.last ), - .s_axi_wvalid ( dram_req.w_valid ), - .s_axi_wready ( dram_resp.w_ready ), - .s_axi_bready ( dram_req.b_ready ), - .s_axi_bid ( dram_resp.b.id ), - .s_axi_bresp ( dram_resp.b.resp ), - .s_axi_bvalid ( dram_resp.b_valid ), - .s_axi_arid ( dram_req.ar.id ), - .s_axi_araddr ( dram_req.ar.addr[29:0] ), - .s_axi_arlen ( dram_req.ar.len ), - .s_axi_arsize ( dram_req.ar.size ), - .s_axi_arburst ( dram_req.ar.burst ), - .s_axi_arlock ( dram_req.ar.lock ), - .s_axi_arcache ( dram_req.ar.cache ), - .s_axi_arprot ( dram_req.ar.prot ), - .s_axi_arqos ( dram_req.ar.qos ), - .s_axi_arvalid ( dram_req.ar_valid ), - .s_axi_arready ( dram_resp.ar_ready ), - .s_axi_rready ( dram_req.r_ready ), - .s_axi_rid ( dram_resp.r.id ), - .s_axi_rdata ( dram_resp.r.data ), - .s_axi_rresp ( dram_resp.r.resp ), - .s_axi_rlast ( dram_resp.r.last ), - .s_axi_rvalid ( dram_resp.r_valid ), - .init_calib_complete ( ), // keep open - .device_temp ( ), // keep open - .sys_rst ( cpu_resetn ) +`ifdef USE_DDR + dram_wrapper_xilinx #( + .axi_soc_aw_chan_t ( axi_llc_aw_chan_t ), + .axi_soc_w_chan_t ( axi_llc_w_chan_t ), + .axi_soc_b_chan_t ( axi_llc_b_chan_t ), + .axi_soc_ar_chan_t ( axi_llc_ar_chan_t ), + .axi_soc_r_chan_t ( axi_llc_r_chan_t ), + .axi_soc_req_t ( axi_llc_req_t ), + .axi_soc_resp_t ( axi_llc_rsp_t ) + ) i_dram_wrapper ( + // Rst + .sys_rst_i ( sys_rst ), + .soc_resetn_i ( rst_n ), + .soc_clk_i ( soc_clk ), + // Sys clk + .dram_clk_i ( sys_clk ), + // Axi + .soc_req_i ( axi_llc_mst_req ), + .soc_rsp_o ( axi_llc_mst_rsp ), + // Phy + .* ); - +`endif ////////////////// // I2C Adaption // @@ -338,6 +331,7 @@ module cheshire_top_xilinx logic i2c_sda_en; logic i2c_scl_en; +`ifdef USE_I2C // Three state buffer for SCL IOBUF #( .DRIVE ( 12 ), @@ -363,51 +357,100 @@ module cheshire_top_xilinx .I ( i2c_sda_soc_out ), .T ( ~i2c_sda_en ) ); +`endif ////////////////// // SPI Adaption // ////////////////// - logic spi_sck_soc; - logic [1:0] spi_cs_soc; - logic [3:0] spi_sd_soc_out; - logic [3:0] spi_sd_soc_in; + (* mark_debug = "true" *) logic spi_sck_soc; + (* mark_debug = "true" *) logic [1:0] spi_cs_soc; + (* mark_debug = "true" *) logic [3:0] spi_sd_soc_out; + (* mark_debug = "true" *) logic [3:0] spi_sd_soc_in; - logic spi_sck_en; - logic [1:0] spi_cs_en; - logic [3:0] spi_sd_en; + (* mark_debug = "true" *) logic spi_sck_en; + (* mark_debug = "true" *) logic [1:0] spi_cs_en; + (* mark_debug = "true" *) logic [3:0] spi_sd_en; +`ifdef USE_SD // Assert reset low => Apply power to the SD Card assign sd_reset_o = 1'b0; - // SCK - SD CLK signal assign sd_sclk_o = spi_sck_en ? spi_sck_soc : 1'b1; - // CS - SD DAT3 signal assign sd_d_io[3] = spi_cs_en[0] ? spi_cs_soc[0] : 1'b1; - // MOSI - SD CMD signal assign sd_cmd_o = spi_sd_en[0] ? spi_sd_soc_out[0] : 1'b1; - // MISO - SD DAT0 signal assign spi_sd_soc_in[1] = sd_d_io[0]; - // SD DAT1 and DAT2 signal tie-off - Not used for SPI mode assign sd_d_io[2:1] = 2'b11; - // Bind input side of SoC low for output signals assign spi_sd_soc_in[0] = 1'b0; assign spi_sd_soc_in[2] = 1'b0; assign spi_sd_soc_in[3] = 1'b0; +`endif + ////////////////// + // QSPI // + ////////////////// + +`ifdef USE_QSPI + logic qspi_clk; + logic qspi_clk_ts; + logic [3:0] qspi_dqi; + logic [3:0] qspi_dqo_ts; + logic [3:0] qspi_dqo; + logic [SpihNumCs-1:0] qspi_cs_b; + logic [SpihNumCs-1:0] qspi_cs_b_ts; + + assign qspi_clk = spi_sck_soc; + assign qspi_cs_b = spi_cs_soc; + assign qspi_dqo = spi_sd_soc_out; + assign spi_sd_soc_in = qspi_dqi; + // Tristate - Enable + assign qspi_clk_ts = ~spi_sck_en; + assign qspi_cs_b_ts = ~spi_cs_en; + assign qspi_dqo_ts = ~spi_sd_en; + + // On VCU128/ZCU102, SPI ports are not directly available +`ifdef USE_STARTUPE3 + STARTUPE3 #( + .PROG_USR("FALSE"), + .SIM_CCLK_FREQ(0.0) + ) + STARTUPE3_inst ( + .CFGCLK (), + .CFGMCLK (), + .DI (qspi_dqi), + .EOS (), + .PREQ (), + .DO (qspi_dqo), + .DTS (qspi_dqo_ts), + .FCSBO (qspi_cs_b[1]), + .FCSBTS (qspi_cs_b_ts[1]), + .GSR (1'b0), + .GTS (1'b0), + .KEYCLEARB (1'b1), + .PACK (1'b0), + .USRCCLKO (qspi_clk), + .USRCCLKTS (qspi_clk_ts), + .USRDONEO (1'b1), + .USRDONETS (1'b1) + ); +`else + // TODO: off-chip qspi interface +`endif // USE_STARTUPE3 + +`endif // USE_QSPI ///////////////////////// // "RTC" Clock Divider // ///////////////////////// logic rtc_clk_d, rtc_clk_q; - logic [4:0] counter_d, counter_q; + logic [15:0] counter_d, counter_q; // Divide soc_clk (50 MHz) by 50 => 1 MHz RTC Clock always_comb begin @@ -415,14 +458,14 @@ module cheshire_top_xilinx rtc_clk_d = rtc_clk_q; if(counter_q == 24) begin - counter_d = 5'b0; + counter_d = '0; rtc_clk_d = ~rtc_clk_q; end end always_ff @(posedge soc_clk, negedge rst_n) begin if(~rst_n) begin - counter_q <= 5'b0; + counter_q <= '0; rtc_clk_q <= 0; end else begin counter_q <= counter_d; @@ -430,18 +473,18 @@ module cheshire_top_xilinx end end - ///////////////// // Fan Control // ///////////////// +`ifdef USE_FAN fan_ctrl i_fan_ctrl ( .clk_i ( soc_clk ), .rst_ni ( rst_n ), .pwm_setting_i ( fan_sw ), .fan_pwm_o ( fan_pwm ) ); - +`endif //////////////////////// // Regbus Error Slave // @@ -460,7 +503,6 @@ module cheshire_top_xilinx .rsp_o ( ext_rsp ) ); - ////////////////// // Cheshire SoC // ////////////////// @@ -479,9 +521,9 @@ module cheshire_top_xilinx ) i_cheshire_soc ( .clk_i ( soc_clk ), .rst_ni ( rst_n ), - .test_mode_i, - .boot_mode_i, - .rtc_i ( rtc_clk_q ), + .test_mode_i ( testmode_i ), + .boot_mode_i ( boot_mode ), + .rtc_i ( rtc_clk_q ), .axi_llc_mst_req_o ( axi_llc_mst_req ), .axi_llc_mst_rsp_i ( axi_llc_mst_rsp ), .axi_ext_mst_req_i ( '0 ), @@ -498,45 +540,47 @@ module cheshire_top_xilinx .dbg_active_o ( ), .dbg_ext_req_o ( ), .dbg_ext_unavail_i ( '0 ), +// Serial Link may be disabled +`ifdef USE_SERIAL + .ddr_link_i ( '0 ), + .ddr_link_o, + .ddr_link_clk_i ( 1'b1 ), + .ddr_link_clk_o, +`endif +// External JTAG may be disabled +`ifdef USE_JTAG .jtag_tck_i, .jtag_trst_ni, .jtag_tms_i, .jtag_tdi_i, .jtag_tdo_o, - .jtag_tdo_oe_o ( ), + // TODO: connect to the tdo pad + .jtag_tdo_oe_o( ), +`endif +// I2C Uses internal signals that are always defined + .i2c_sda_o ( i2c_sda_soc_out ), + .i2c_sda_i ( i2c_sda_soc_in ), + .i2c_sda_en_o ( i2c_sda_en ), + .i2c_scl_o ( i2c_scl_soc_out ), + .i2c_scl_i ( i2c_scl_soc_in ), + .i2c_scl_en_o ( i2c_scl_en ), +// SPI Uses internal signals that are always defined + .spih_sck_o ( spi_sck_soc ), + .spih_sck_en_o ( spi_sck_en ), + .spih_csb_o ( spi_cs_soc ), + .spih_csb_en_o ( spi_cs_en ), + .spih_sd_o ( spi_sd_soc_out ), + .spih_sd_en_o ( spi_sd_en ), + .spih_sd_i ( spi_sd_soc_in ), +`ifdef USE_VGA + .vga_hsync_o ( vga_hs ), + .vga_vsync_o ( vga_vs ), + .vga_red_o ( vga_r ), + .vga_green_o ( vga_g ), + .vga_blue_o ( vga_b ), +`endif .uart_tx_o, - .uart_rx_i, - .uart_rts_no ( ), - .uart_dtr_no ( ), - .uart_cts_ni ( 1'b0 ), - .uart_dsr_ni ( 1'b0 ), - .uart_dcd_ni ( 1'b0 ), - .uart_rin_ni ( 1'b0 ), - .i2c_sda_o ( i2c_sda_soc_out ), - .i2c_sda_i ( i2c_sda_soc_in ), - .i2c_sda_en_o ( i2c_sda_en ), - .i2c_scl_o ( i2c_scl_soc_out ), - .i2c_scl_i ( i2c_scl_soc_in ), - .i2c_scl_en_o ( i2c_scl_en ), - .spih_sck_o ( spi_sck_soc ), - .spih_sck_en_o ( spi_sck_en ), - .spih_csb_o ( spi_cs_soc ), - .spih_csb_en_o ( spi_cs_en ), - .spih_sd_o ( spi_sd_soc_out ), - .spih_sd_en_o ( spi_sd_en ), - .spih_sd_i ( spi_sd_soc_in ), - .gpio_i ( '0 ), - .gpio_o ( ), - .gpio_en_o ( ), - .slink_rcv_clk_i ( '1 ), - .slink_rcv_clk_o ( ), - .slink_i ( '0 ), - .slink_o ( ), - .vga_hsync_o ( vga_hs ), - .vga_vsync_o ( vga_vs ), - .vga_red_o ( vga_r ), - .vga_green_o ( vga_g ), - .vga_blue_o ( vga_b ) + .uart_rx_i ); endmodule diff --git a/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv b/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv new file mode 100644 index 00000000..10698616 --- /dev/null +++ b/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv @@ -0,0 +1,377 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + + +`include "cheshire/typedef.svh" +`include "phy_definitions.svh" +`include "common_cells/registers.svh" + +module dram_wrapper_xilinx #( + parameter type axi_soc_aw_chan_t = logic, + parameter type axi_soc_w_chan_t = logic, + parameter type axi_soc_b_chan_t = logic, + parameter type axi_soc_ar_chan_t = logic, + parameter type axi_soc_r_chan_t = logic, + parameter type axi_soc_req_t = logic, + parameter type axi_soc_resp_t = logic +) ( + // System reset + input sys_rst_i, + input dram_clk_i, + // Controller reset + input soc_resetn_i, + input soc_clk_i, + // Phy interfaces +`ifdef USE_DDR4 + `DDR4_INTF +`endif +`ifdef USE_DDR3 + `DDR3_INTF +`endif + // Dram axi interface + input axi_soc_req_t soc_req_i, + output axi_soc_resp_t soc_rsp_o +); + + //////////////////////////////////// + // Configurations and definitions // + //////////////////////////////////// + + typedef struct packed { + bit EnCDC; + integer IdWidth; + integer AddrWidth; + integer DataWidth; + integer StrobeWidth; + } dram_cfg_t; + +`ifdef TARGET_VCU128 + localparam dram_cfg_t cfg = '{ + EnCDC : 1, // 333 MHz axi (attention CDC logdepth) + IdWidth : 4, + AddrWidth : 32, + DataWidth : 512, + StrobeWidth : 64 + }; +`endif + +`ifdef TARGET_ZCU102 + localparam dram_cfg_t cfg = '{ + EnCDC : 1, // ??? MHz axi (attention CDC logdepth) + IdWidth : 4, + AddrWidth : 29, + DataWidth : 128, + StrobeWidth : 16 + }; +`endif + +`ifdef TARGET_GENESYS2 + localparam dram_cfg_t cfg = '{ + EnCDC : 1, // 200 MHz axi (attention CDC logdepth) + IdWidth : 4, + AddrWidth : 30, + DataWidth : 64, + StrobeWidth : 8 + }; +`endif + + localparam SoC_DataWidth = $bits(soc_req_i.w.data); + localparam SoC_IdWidth = $bits(soc_req_i.ar.id); + localparam SoC_UserWidth = $bits(soc_req_i.ar.user); + localparam SoC_AddrWidth = $bits(soc_req_i.ar.addr); + + // Define type after data width and address resizer + `AXI_TYPEDEF_ALL(axi_dw, logic[SoC_AddrWidth-1:0], logic[SoC_IdWidth-1:0], + logic[cfg.DataWidth-1:0], logic[cfg.StrobeWidth-1:0], + logic[SoC_UserWidth-1:0]) + + // Define type after data & id width resizers + `AXI_TYPEDEF_ALL(axi_dw_iw, logic[SoC_AddrWidth-1:0], logic[cfg.IdWidth-1:0], + logic[cfg.DataWidth-1:0], logic[cfg.StrobeWidth-1:0], + logic[SoC_UserWidth-1:0]) + + // Clock on which is clocked the DRAM AXI + logic dram_axi_clk, dram_rst_o; + + // Signals before resizing + axi_soc_req_t soc_dresizer_req; + axi_soc_resp_t soc_dresizer_rsp; + + // Signals after data width resizing + axi_dw_req_t dresizer_iresizer_req; + axi_dw_resp_t dresizer_iresizer_rsp; + + // Signals after id width resizing + axi_dw_iw_req_t iresizer_cdc_req, cdc_dram_req; + axi_dw_iw_resp_t iresizer_cdc_rsp, cdc_dram_rsp; + + // Entry signals + assign soc_dresizer_req = soc_req_i; + assign soc_rsp_o = soc_dresizer_rsp; + + ///////////////////////////////////// + // Instianciate data width resizer // + ///////////////////////////////////// + + if (cfg.DataWidth != SoC_DataWidth) begin : gen_dw_converter + axi_dw_converter #( + .AxiMaxReads (8), + .AxiSlvPortDataWidth(SoC_DataWidth), + .AxiMstPortDataWidth(cfg.DataWidth), + .AxiAddrWidth (SoC_AddrWidth), + .AxiIdWidth (SoC_IdWidth ), + // Common aw, ar, b + .aw_chan_t (axi_soc_aw_chan_t), + .b_chan_t (axi_soc_b_chan_t), + .ar_chan_t (axi_soc_ar_chan_t), + // Master w, r + .mst_w_chan_t (axi_dw_w_chan_t), + .mst_r_chan_t (axi_dw_r_chan_t), + .axi_mst_req_t (axi_dw_req_t), + .axi_mst_resp_t (axi_dw_resp_t), + // Slave w, r + .slv_w_chan_t (axi_soc_w_chan_t), + .slv_r_chan_t (axi_soc_r_chan_t), + .axi_slv_req_t (axi_soc_req_t), + .axi_slv_resp_t (axi_soc_resp_t) + ) axi_dw_converter_ddr4 ( + .clk_i (soc_clk_i), + .rst_ni (soc_resetn_i), + .slv_req_i (soc_dresizer_req), + .slv_resp_o(soc_dresizer_rsp), + .mst_req_o (dresizer_iresizer_req), + .mst_resp_i(dresizer_iresizer_rsp) + ); + end else begin : gen_no_dw_converter + assign dresizer_iresizer_req = soc_dresizer_req; + assign soc_dresizer_rsp = dresizer_iresizer_rsp; + end + + ///////////////// + // ID resizer // + ///////////////// + +if (cfg.IdWidth != SoC_IdWidth) begin : gen_iw_converter + axi_iw_converter #( + .AxiAddrWidth ( SoC_AddrWidth ), + .AxiDataWidth ( cfg.DataWidth ), + .AxiUserWidth ( SoC_UserWidth ), + .AxiSlvPortIdWidth ( SoC_IdWidth ), + .AxiSlvPortMaxUniqIds ( 1 ), + .AxiSlvPortMaxTxnsPerId( 1 ), + .AxiSlvPortMaxTxns ( 1 ), + .AxiMstPortIdWidth ( cfg.IdWidth ), + .AxiMstPortMaxUniqIds ( 1 ), + .AxiMstPortMaxTxnsPerId( 1 ), + .slv_req_t ( axi_dw_req_t ), + .slv_resp_t ( axi_dw_resp_t ), + .mst_req_t ( axi_dw_iw_req_t ), + .mst_resp_t ( axi_dw_iw_resp_t ) + ) i_axi_iw_convert ( + .clk_i ( soc_clk_i ), + .rst_ni ( soc_resetn_i ), + .slv_req_i ( dresizer_iresizer_req ), + .slv_resp_o ( dresizer_iresizer_rsp ), + .mst_req_o ( iresizer_cdc_req ), + .mst_resp_i ( iresizer_cdc_rsp ) + ); + end else begin : gen_no_iw_converter + assign iresizer_cdc_req = dresizer_iresizer_req; + assign dresizer_iresizer_rsp = iresizer_cdc_rsp; + end + + ////////////////////// + // Instianciate CDC // + ////////////////////// + + if (cfg.EnCDC) begin : gen_cdc + axi_cdc #( + .aw_chan_t (axi_dw_iw_aw_chan_t), + .w_chan_t (axi_dw_iw_w_chan_t), + .b_chan_t (axi_dw_iw_b_chan_t), + .ar_chan_t (axi_dw_iw_ar_chan_t), + .r_chan_t (axi_dw_iw_r_chan_t), + .axi_req_t (axi_dw_iw_req_t), + .axi_resp_t(axi_dw_iw_resp_t), + .LogDepth (4) + ) i_axi_cdc_mig ( + .src_clk_i (soc_clk_i), + .src_rst_ni(soc_resetn_i), + .src_req_i (iresizer_cdc_req), + .src_resp_o(iresizer_cdc_rsp), + .dst_clk_i (dram_axi_clk), + .dst_rst_ni(~dram_rst_o), + .dst_req_o (cdc_dram_req), + .dst_resp_i(cdc_dram_rsp) + ); + end else begin : gen_no_cdc + assign cdc_dram_req = iresizer_cdc_req; + assign iresizer_cdc_rsp = cdc_dram_rsp; + end + + /////////////////////// + // User and address // + /////////////////////// + + assign cdc_dram_rsp.b.user = '0; + assign cdc_dram_rsp.r.user = '0; + + logic [cfg.AddrWidth-1:0] cdc_dram_req_aw_addr; + logic [cfg.AddrWidth-1:0] cdc_dram_req_ar_addr; + + assign cdc_dram_req_aw_addr = cdc_dram_req.aw.addr[cfg.AddrWidth-1:0]; + assign cdc_dram_req_ar_addr = cdc_dram_req.ar.addr[cfg.AddrWidth-1:0]; + + + /////////////////////// + // Instianciate DDR4 // + /////////////////////// + +`ifdef USE_DDR4 + + xlnx_mig_ddr4 i_dram ( + // Rst + .sys_rst (sys_rst_i), // Active high + .c0_sys_clk_i (dram_clk_i), + .c0_ddr4_aresetn (soc_resetn_i), + // Clk rst out + .c0_ddr4_ui_clk (dram_axi_clk), + .c0_ddr4_ui_clk_sync_rst (dram_rst_o), + // Axi + .c0_ddr4_s_axi_awid (cdc_dram_req.aw.id), + .c0_ddr4_s_axi_awaddr (cdc_dram_req_aw_addr), + .c0_ddr4_s_axi_awlen (cdc_dram_req.aw.len), + .c0_ddr4_s_axi_awsize (cdc_dram_req.aw.size), + .c0_ddr4_s_axi_awburst (cdc_dram_req.aw.burst), + .c0_ddr4_s_axi_awlock (cdc_dram_req.aw.lock), + .c0_ddr4_s_axi_awcache (cdc_dram_req.aw.cache), + .c0_ddr4_s_axi_awprot (cdc_dram_req.aw.prot), + .c0_ddr4_s_axi_awqos (cdc_dram_req.aw.qos), + .c0_ddr4_s_axi_awvalid (cdc_dram_req.aw_valid), + .c0_ddr4_s_axi_awready (cdc_dram_rsp.aw_ready), + .c0_ddr4_s_axi_wdata (cdc_dram_req.w.data), + .c0_ddr4_s_axi_wstrb (cdc_dram_req.w.strb), + .c0_ddr4_s_axi_wlast (cdc_dram_req.w.last), + .c0_ddr4_s_axi_wvalid (cdc_dram_req.w_valid), + .c0_ddr4_s_axi_wready (cdc_dram_rsp.w_ready), + .c0_ddr4_s_axi_bready (cdc_dram_req.b_ready), + .c0_ddr4_s_axi_bid (cdc_dram_rsp.b.id), + .c0_ddr4_s_axi_bresp (cdc_dram_rsp.b.resp), + .c0_ddr4_s_axi_bvalid (cdc_dram_rsp.b_valid), + .c0_ddr4_s_axi_arid (cdc_dram_req.ar.id), + .c0_ddr4_s_axi_araddr (cdc_dram_req_ar_addr), + .c0_ddr4_s_axi_arlen (cdc_dram_req.ar.len), + .c0_ddr4_s_axi_arsize (cdc_dram_req.ar.size), + .c0_ddr4_s_axi_arburst (cdc_dram_req.ar.burst), + .c0_ddr4_s_axi_arlock (cdc_dram_req.ar.lock), + .c0_ddr4_s_axi_arcache (cdc_dram_req.ar.cache), + .c0_ddr4_s_axi_arprot (cdc_dram_req.ar.prot), + .c0_ddr4_s_axi_arqos (cdc_dram_req.ar.qos), + .c0_ddr4_s_axi_arvalid (cdc_dram_req.ar_valid), + .c0_ddr4_s_axi_arready (cdc_dram_rsp.ar_ready), + .c0_ddr4_s_axi_rready (cdc_dram_req.r_ready), + .c0_ddr4_s_axi_rid (cdc_dram_rsp.r.id), + .c0_ddr4_s_axi_rdata (cdc_dram_rsp.r.data), + .c0_ddr4_s_axi_rresp (cdc_dram_rsp.r.resp), + .c0_ddr4_s_axi_rlast (cdc_dram_rsp.r.last), + .c0_ddr4_s_axi_rvalid (cdc_dram_rsp.r_valid), +`ifdef TARGET_VCU128 + // Axi ctrl + .c0_ddr4_s_axi_ctrl_awvalid('0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr ('0), + .c0_ddr4_s_axi_ctrl_wvalid ('0), + .c0_ddr4_s_axi_ctrl_wready (), + .c0_ddr4_s_axi_ctrl_wdata ('0), + .c0_ddr4_s_axi_ctrl_bvalid (), + .c0_ddr4_s_axi_ctrl_bready ('0), + .c0_ddr4_s_axi_ctrl_bresp (), + .c0_ddr4_s_axi_ctrl_arvalid('0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr ('0), + .c0_ddr4_s_axi_ctrl_rvalid (), + .c0_ddr4_s_axi_ctrl_rready ('0), + .c0_ddr4_s_axi_ctrl_rdata (), + .c0_ddr4_s_axi_ctrl_rresp (), + .c0_ddr4_interrupt (), +`endif + // Others + .c0_init_calib_complete (), // keep open + .addn_ui_clkout1 (dram_clk_o), + .dbg_clk (), + .dbg_bus (), + // Phy + .* + ); + +`endif // USE_DDR4 + + + /////////////////////// + // Instianciate DDR3 // + /////////////////////// + + +`ifdef USE_DDR3 + + xlnx_mig_7_ddr3 i_dram ( + .sys_rst (sys_rst_i), // Active high + .sys_clk_i (dram_clk_i), + .ui_clk (dram_axi_clk), + .ui_clk_sync_rst (dram_rst_o), + .mmcm_locked (), // keep open + .app_sr_req ('0), + .app_ref_req ('0), + .app_zq_req ('0), + .app_sr_active (), // keep open + .app_ref_ack (), // keep open + .app_zq_ack (), // keep open + .aresetn (soc_resetn_i), + .s_axi_awid (cdc_dram_req.aw.id), + .s_axi_awaddr (cdc_dram_req_aw_addr), + .s_axi_awlen (cdc_dram_req.aw.len), + .s_axi_awsize (cdc_dram_req.aw.size), + .s_axi_awburst (cdc_dram_req.aw.burst), + .s_axi_awlock (cdc_dram_req.aw.lock), + .s_axi_awcache (cdc_dram_req.aw.cache), + .s_axi_awprot (cdc_dram_req.aw.prot), + .s_axi_awqos (cdc_dram_req.aw.qos), + .s_axi_awvalid (cdc_dram_req.aw_valid), + .s_axi_awready (cdc_dram_rsp.aw_ready), + .s_axi_wdata (cdc_dram_req.w.data), + .s_axi_wstrb (cdc_dram_req.w.strb), + .s_axi_wlast (cdc_dram_req.w.last), + .s_axi_wvalid (cdc_dram_req.w_valid), + .s_axi_wready (cdc_dram_rsp.w_ready), + .s_axi_bready (cdc_dram_req.b_ready), + .s_axi_bid (cdc_dram_rsp.b.id), + .s_axi_bresp (cdc_dram_rsp.b.resp), + .s_axi_bvalid (cdc_dram_rsp.b_valid), + .s_axi_arid (cdc_dram_req.ar.id), + .s_axi_araddr (cdc_dram_req_ar_addr), + .s_axi_arlen (cdc_dram_req.ar.len), + .s_axi_arsize (cdc_dram_req.ar.size), + .s_axi_arburst (cdc_dram_req.ar.burst), + .s_axi_arlock (cdc_dram_req.ar.lock), + .s_axi_arcache (cdc_dram_req.ar.cache), + .s_axi_arprot (cdc_dram_req.ar.prot), + .s_axi_arqos (cdc_dram_req.ar.qos), + .s_axi_arvalid (cdc_dram_req.ar_valid), + .s_axi_arready (cdc_dram_rsp.ar_ready), + .s_axi_rready (cdc_dram_req.r_ready), + .s_axi_rid (cdc_dram_rsp.r.id), + .s_axi_rdata (cdc_dram_rsp.r.data), + .s_axi_rresp (cdc_dram_rsp.r.resp), + .s_axi_rlast (cdc_dram_rsp.r.last), + .s_axi_rvalid (cdc_dram_rsp.r_valid), + .init_calib_complete(), // keep open + .device_temp (), // keep open + // Phy + .* + ); +`endif // USE_DDR3 + +endmodule diff --git a/target/xilinx/src/fan_ctrl.sv b/target/xilinx/flavor_vanilla/src/fan_ctrl.sv similarity index 100% rename from target/xilinx/src/fan_ctrl.sv rename to target/xilinx/flavor_vanilla/src/fan_ctrl.sv diff --git a/target/xilinx/flavor_vanilla/src/phy_definitions.svh b/target/xilinx/flavor_vanilla/src/phy_definitions.svh new file mode 100644 index 00000000..41e33536 --- /dev/null +++ b/target/xilinx/flavor_vanilla/src/phy_definitions.svh @@ -0,0 +1,93 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +`ifdef TARGET_VCU128 + `define USE_RESET + `define USE_JTAG + `define USE_JTAG_VDDGND + `define USE_DDR4 + `define USE_QSPI + `define USE_STARTUPE3 + `define USE_VIO +`endif + +`ifdef TARGET_GENESYS2 + `define USE_RESETN + `define USE_JTAG + `define USE_JTAG_TRSTN + `define USE_SD + `define USE_SWITCHES + `define USE_DDR3 + `define USE_FAN + `define USE_VIO + `define USE_I2C + `define USE_VGA +`endif + +`ifdef TARGET_ZCU102 + `define USE_RESET + `define USE_JTAG + `define USE_DDR4 + `define USE_VIO +`endif + +///////////////////// +// DRAM INTERFACES // +///////////////////// + +`ifdef USE_DDR4 +`define USE_DDR +`endif +`ifdef USE_DDR3 +`define USE_DDR +`endif + +`define DDR4_INTF \ + /* DDR4 intf */ \ + output c0_ddr4_reset_n, \ + output [0:0] c0_ddr4_ck_t, \ + output [0:0] c0_ddr4_ck_c, \ + output c0_ddr4_act_n, \ + output [16:0] c0_ddr4_adr, \ + output [1:0] c0_ddr4_ba, \ + output [0:0] c0_ddr4_bg, \ + output [0:0] c0_ddr4_cke, \ + output [0:0] c0_ddr4_odt, \ +`ifdef TARGET_VCU128 \ + output [1:0] c0_ddr4_cs_n, \ + inout [8:0] c0_ddr4_dm_dbi_n, \ + inout [71:0] c0_ddr4_dq, \ + inout [8:0] c0_ddr4_dqs_c, \ + inout [8:0] c0_ddr4_dqs_t, \ +`endif \ +`ifdef TARGET_ZCU102 \ + output [0:0] c0_ddr4_cs_n, \ + inout [1:0] c0_ddr4_dm_dbi_n, \ + inout [15:0] c0_ddr4_dq, \ + inout [1:0] c0_ddr4_dqs_c, \ + inout [1:0] c0_ddr4_dqs_t, \ +`endif + +`define DDR3_INTF \ + output ddr3_ck_p, \ + output ddr3_ck_n, \ + inout [31:0] ddr3_dq, \ + inout [3:0] ddr3_dqs_n, \ + inout [3:0] ddr3_dqs_p, \ + output [14:0] ddr3_addr, \ + output [2:0] ddr3_ba, \ + output ddr3_ras_n, \ + output ddr3_cas_n, \ + output ddr3_we_n, \ + output ddr3_reset_n, \ + output [0:0] ddr3_cke, \ + output [0:0] ddr3_cs_n, \ + output [3:0] ddr3_dm, \ + output [0:0] ddr3_odt, + +`define ila(__name, __signal) \ + (* dont_touch = "yes" *) (* mark_debug = "true" *) logic [$bits(__signal)-1:0] __name; \ + assign __name = __signal; diff --git a/target/xilinx/scripts/flash_spi.tcl b/target/xilinx/scripts/flash_spi.tcl new file mode 100644 index 00000000..c4e32311 --- /dev/null +++ b/target/xilinx/scripts/flash_spi.tcl @@ -0,0 +1,48 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nils Wistoff +# Noah Huetter + +open_hw_manager + +connect_hw_server -url $::env(XILINX_HOST):$::env(XILINX_PORT) +open_hw_target $::env(XILINX_HOST):$::env(XILINX_PORT)/$::env(XILINX_FPGA_PATH) + +set file $::env(FILE) +set offset $::env(OFFSET) +set mcs_file image.mcs + +if {$::env(BOARD) eq "vcu128"} { + set hw_device [get_hw_devices xcvu37p_0] + set hw_mem_device [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0] +} + +# Create flash configuration file +write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ + -loaddata "up $offset $file" \ + -checksum \ + -file $mcs_file + +set_property PARAM.FREQUENCY 15000000 [get_hw_targets *] + +create_hw_cfgmem -hw_device $hw_device $hw_mem_device +set hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_device] +set_property PROGRAM.ADDRESS_RANGE {use_file} $hw_cfgmem +set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem +set_property PROGRAM.PRM_FILE {} $hw_cfgmem +set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $hw_cfgmem +set_property PROGRAM.BLANK_CHECK 0 $hw_cfgmem +set_property PROGRAM.ERASE 1 $hw_cfgmem +set_property PROGRAM.CFG_PROGRAM 1 $hw_cfgmem +set_property PROGRAM.VERIFY 1 $hw_cfgmem +set_property PROGRAM.CHECKSUM 0 $hw_cfgmem + +# Create bitstream to access SPI flash +create_hw_bitstream -hw_device $hw_device [get_property PROGRAM.HW_CFGMEM_BITFILE $hw_device]; +program_hw_devices $hw_device; +refresh_hw_device $hw_device; + +# Program SPI flash +program_hw_cfgmem -hw_cfgmem $hw_cfgmem diff --git a/target/xilinx/scripts/program.tcl b/target/xilinx/scripts/program.tcl index 846519a6..c9bd8678 100644 --- a/target/xilinx/scripts/program.tcl +++ b/target/xilinx/scripts/program.tcl @@ -3,26 +3,22 @@ # SPDX-License-Identifier: SHL-0.51 # # Author: Florian Zaruba -# Description: Program Genesys II open_hw_manager -connect_hw_server -url $::env(HOST):$::env(PORT) +connect_hw_server -url $::env(XILINX_HOST):$::env(XILINX_PORT) +open_hw_target $::env(XILINX_HOST):$::env(XILINX_PORT)/$::env(XILINX_FPGA_PATH) if {$::env(BOARD) eq "genesys2"} { - open_hw_target $::env(HOST):$::env(PORT)/$::env(FPGA_PATH) + set hw_device [get_hw_devices xc7k325t_0] +} +if {$::env(BOARD) eq "vcu128"} { + set hw_device [get_hw_devices xcvu37p_0] +} - current_hw_device [get_hw_devices xc7k325t_0] - set_property PROGRAM.FILE $::env(BIT) [get_hw_devices xc7k325t_0] - program_hw_devices [get_hw_devices xc7k325t_0] - refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0] -} elseif {$::env(BOARD) eq "vc707"} { - open_hw_target {$::env(HOST):$::env(PORT)/$::env(FPGA_PATH)} +set_property PARAM.FREQUENCY 15000000 [get_hw_targets *] - current_hw_device [get_hw_devices xc7vx485t_0] - set_property PROGRAM.FILE $::env(BIT) [get_hw_devices xc7vx485t_0] - program_hw_devices [get_hw_devices xc7vx485t_0] - refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0] -} else { - exit 1 -} +current_hw_device $hw_device +set_property PROGRAM.FILE $::env(XILINX_BIT) $hw_device +program_hw_devices $hw_device +refresh_hw_device [lindex $hw_device 0] diff --git a/target/xilinx/scripts/prologue.tcl b/target/xilinx/scripts/prologue.tcl deleted file mode 100644 index 4985d3d1..00000000 --- a/target/xilinx/scripts/prologue.tcl +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Author: Florian Zaruba - -set project $::env(PROJECT) - -create_project $project . -force -part $::env(XILINX_PART) -set_property board_part $::env(XILINX_BOARD) [current_project] - -# set number of threads to 8 (maximum, unfortunately) -set_param general.maxThreads 8 - -#set_msg_config -id {[Synth 8-5858]} -new_severity "info" - -#set_msg_config -id {[Synth 8-4480]} -limit 1000 \ No newline at end of file diff --git a/target/xilinx/scripts/run.tcl b/target/xilinx/scripts/run.tcl deleted file mode 100644 index c99247e9..00000000 --- a/target/xilinx/scripts/run.tcl +++ /dev/null @@ -1,80 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Author: Florian Zaruba - -# hard-coded to Genesys 2 for the moment - -if {$::env(BOARD) eq "genesys2"} { - add_files -fileset constrs_1 -norecurse constraints/genesys2.xdc -} elseif {$::env(BOARD) eq "kc705"} { - add_files -fileset constrs_1 -norecurse constraints/kc705.xdc -} elseif {$::env(BOARD) eq "vc707"} { - add_files -fileset constrs_1 -norecurse constraints/vc707.xdc -} else { - exit 1 -} - -read_ip { \ - "xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \ -} - -source scripts/add_sources.tcl - -set_property top ${project}_top_xilinx [current_fileset] - -update_compile_order -fileset sources_1 - -add_files -fileset constrs_1 -norecurse constraints/$project.xdc - -set_property strategy Flow_PerfOptimized_high [get_runs synth_1] -set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] - -set_property XPM_LIBRARIES XPM_MEMORY [current_project] - -synth_design -rtl -name rtl_1 - -set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] - -launch_runs synth_1 -wait_on_run synth_1 -open_run synth_1 - -exec mkdir -p reports/ -exec rm -rf reports/* - -check_timing -verbose -file reports/$project.check_timing.rpt -report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt -report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt -report_utilization -hierarchical -file reports/$project.utilization.rpt -report_cdc -file reports/$project.cdc.rpt -report_clock_interaction -file reports/$project.clock_interaction.rpt - -launch_runs impl_1 -wait_on_run impl_1 -launch_runs impl_1 -to_step write_bitstream -wait_on_run impl_1 - -#Check timing constraints -open_run impl_1 -set timingrep [report_timing_summary -no_header -no_detailed_paths -return_string] -if {[info exists ::env(CHECK_TIMING)] && $::env(CHECK_TIMING)==1} { - if {! [string match -nocase {*timing constraints are met*} $timingrep]} { - send_msg_id {USER 1-1} ERROR {Timing constraints were not met.} - return -code error - } -} - -# output Verilog netlist + SDC for timing simulation -write_verilog -force -mode funcsim out/${project}_funcsim.v -write_verilog -force -mode timesim out/${project}_timesim.v -write_sdf -force out/${project}_timesim.sdf - -# reports -exec mkdir -p reports/ -exec rm -rf reports/* -check_timing -file reports/${project}.check_timing.rpt -report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt -report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt -report_utilization -hierarchical -file reports/${project}.utilization.rpt diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk new file mode 100644 index 00000000..2105756d --- /dev/null +++ b/target/xilinx/xilinx.mk @@ -0,0 +1,113 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +# +# User input Makefile variables +# + +CHS_XIL_DIR ?= $(CHS_ROOT)/target/xilinx + +XILINX_PROJECT ?= cheshire +XILINX_FLAVOR ?= vanilla +XILINX_BOARD ?= genesys2 +XILINX_ELABORATION_ONLY ?= 0 +XILINX_CHECK_TIMING ?= 0 +XILINX_USE_ARTIFACTS ?= 0 + +ifneq (,$(wildcard /etc/iis.version)) + VIVADO ?= vitis-2020.2 vivado +else + VIVADO ?= vivado +endif +VIVADO_MODE ?= batch +VIVADO_FLAGS ?= -nojournal -mode $(VIVADO_MODE) + +# +# Derived variables +# + +ifeq ($(XILINX_BOARD),genesys2) + xilinx_part := xc7k325tffg900-2 + xilinx_board_long := digilentinc.com:genesys2:part0:1.1 + XILINX_PORT ?= 3332 + XILINX_FPGA_PATH ?= xilinx_tcf/Digilent/200300A8C60DB + XILINX_HOST ?= bordcomputer +endif + +ifeq ($(XILINX_BOARD),vcu128) + xilinx_part := xcvu37p-fsvh2892-2L-e + xilinx_board_long := xilinx.com:vcu128:part0:1.0 + XILINX_PORT ?= 3232 + XILINX_FPGA_PATH ?= xilinx_tcf/Xilinx/091847100638A + XILINX_HOST ?= bordcomputer +endif + +xilinx_ip_dir := $(CHS_XIL_DIR)/xilinx_ips +xilinx_ip_dirs := $(wildcard $(xilinx_ip_dir)/*) + +xilinx_targs := -t cv64a6_imafdcsclic_sv39 -t cva6 +xilinx_targs += -t fpga $(addprefix -t ,$(XILINX_BOARD)) + +# +# Include flavors +# + +include $(CHS_XIL_DIR)/flavor_vanilla/flavor_vanilla.mk +include $(CHS_XIL_DIR)/flavor_bd/flavor_bd.mk + +# +# Flavor dependant variables +# + +xilinx_bit := $(CHS_XIL_DIR)/out/$(XILINX_PROJECT)_$(XILINX_FLAVOR)_$(XILINX_BOARD).bit +vivado_env := $(vivado_env_$(XILINX_FLAVOR)) + +# +# Targets +# + +# Generate ips +%.xci: + echo $@ + @echo "Generating IP $(basename $@)" + IP_NAME=$(basename $(notdir $@)) ; cd $(xilinx_ip_dir)/$$IP_NAME && make clean && XILINX_USE_ARTIFACTS=$(XILINX_USE_ARTIFACTS) vivado_env="$(subst ",\",$(vivado_env))" VIVADO="$(VIVADO)" make + +# Copy bitstream and probe file to final output location (/target/xilinx/out) +$(CHS_XIL_DIR)/out/%.bit: $(xilinx_bit_$(XILINX_FLAVOR)) + mkdir -p $(CHS_XIL_DIR)/out/ + if [ "$(XILINX_ELABORATION_ONLY)" -eq "0" ]; then \ + cp $< $@; \ + cp $(patsubst %.bit,%.ltx,$< $@); \ + fi + +# Build a bitstream +chs-xil-all: chs-xil-clean-ips $(xilinx_bit) + +# Program last bitstream +chs-xil-program: + @echo "Programming board $(XILINX_BOARD) ($(xilinx_part))" + $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source $(CHS_XIL_DIR)/scripts/program.tcl + +# Flash linux image +chs-xil-flash: $(CAR_SW_DIR)/boot/linux_carfield_$(XILINX_FLAVOR)_$(XILINX_BOARD).gpt.bin + $(vivado_env) FILE=$< OFFSET=0 $(VIVADO) $(VIVADO_FLAGS) -source $(CHS_XIL_DIR)/scripts/flash_spi.tcl + +# Clean a given IP folder +%-xlnx-ip-clean: % + make -C $< clean +# Clean all IP folder using rule above +chs-xil-clean-ips: $(addsuffix -xlnx-ip-clean,$(shell find $(xilinx_ip_dir)/ -maxdepth 1 -mindepth 1 -type d)) + +chs-xil-clean: chs-xil-clean-ips chs-xil-clean-vanilla chs-xil-clean-bd + +.PHONY: chs-xil-program chs-xil-flash chs-xil-clean chs-xil-all chs-xil-clean-ips diff --git a/target/xilinx/xilinx/common.mk b/target/xilinx/xilinx/common.mk deleted file mode 100644 index b75c9bfa..00000000 --- a/target/xilinx/xilinx/common.mk +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# select IIS-internal tool commands if we run on IIS machines -ifneq (,$(wildcard /etc/iis.version)) - VIVADO ?= vitis-2020.2 vivado -else - VIVADO ?= vivado -endif - -all: - $(VIVADO) -mode batch -source tcl/run.tcl - -gui: - $(VIVADO) -mode gui -source tcl/run.tcl & - -clean: - rm -rf ip/* - mkdir -p ip - rm -rf ${PROJECT}.* - rm -rf component.xml - rm -rf vivado*.jou - rm -rf vivado*.log - rm -rf vivado*.str - rm -rf xgui - rm -rf .Xil diff --git a/target/xilinx/xilinx/xlnx_protocol_checker/Makefile b/target/xilinx/xilinx/xlnx_protocol_checker/Makefile deleted file mode 100644 index f67c6a7b..00000000 --- a/target/xilinx/xilinx/xlnx_protocol_checker/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -PROJECT:=xlnx_protocol_checker -include ../common.mk \ No newline at end of file diff --git a/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl b/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl deleted file mode 100644 index 2e6ebfcf..00000000 --- a/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# - -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -set ipName xlnx_protocol_checker - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_protocol_checker -vendor xilinx.com -library ip -version 2.0 -module_name $ipName - -set_property -dict [list CONFIG.ADDR_WIDTH {48} \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ID_WIDTH {6} \ - CONFIG.AWUSER_WIDTH {1} \ - CONFIG.ARUSER_WIDTH {1} \ - CONFIG.RUSER_WIDTH {1} \ - CONFIG.WUSER_WIDTH {1} \ - CONFIG.BUSER_WIDTH {1} \ - CONFIG.MAX_AW_WAITS {1024} \ - CONFIG.MAX_AR_WAITS {1024} \ - CONFIG.MAX_W_WAITS {1024} \ - CONFIG.MAX_R_WAITS {1024} \ - CONFIG.MAX_B_WAITS {1024} \ - CONFIG.MAX_CONTINUOUS_WTRANSFERS_WAITS {1024} \ - CONFIG.MAX_WLAST_TO_AWVALID_WAITS {1024} \ - CONFIG.MAX_WRITE_TO_BVALID_WAITS {1024} \ - CONFIG.MAX_CONTINUOUS_RTRANSFERS_WAITS {1024} \ - ] [get_ips $ipName] - - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/target/xilinx/xilinx/.gitignore b/target/xilinx/xilinx_ips/.gitignore similarity index 100% rename from target/xilinx/xilinx/.gitignore rename to target/xilinx/xilinx_ips/.gitignore diff --git a/target/xilinx/xilinx_ips/common.mk b/target/xilinx/xilinx_ips/common.mk new file mode 100644 index 00000000..c1e8c4bd --- /dev/null +++ b/target/xilinx/xilinx_ips/common.mk @@ -0,0 +1,65 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +all: load-artifacts $(PROJECT).xpr save-artifacts + +# Build IP +xlnx_%.xpr: + $(vivado_env) $(VIVADO) -mode batch -source tcl/run.tcl + +save-artifacts: + +load-artifacts: + +clean: + @rm -rf ip/* + @mkdir -p ip + @rm -rf ${PROJECT}.* + @rm -rf component.xml + @rm -rf vivado*.jou + @rm -rf vivado*.log + @rm -rf vivado*.str + @rm -rf xgui + @rm -rf .Xil + @rm -rf tmp + @rm -rf .generated* + +.PHONY: clean save-artifacts load-artifacts + +# +# Artifacts management (IIS internal) +# + +ifeq ($(XILINX_USE_ARTIFACTS),1) + +# Note: We do not use Memora as it is bound to Git versionning +# and not standalone on files hash / environment variables +ARTIFACTS_PATH=/usr/scratch2/wuerzburg/cykoenig/memora/cheshire +TERM_GREEN='\033[0;32m' +TERM_NC='\033[0m' + +# Generate a sha based on env variables and artifacts_in +.generated_sha256: + @echo $(VIVADO) $(PROJECT) > .generated_env + @echo $(vivado_env) | tr " " "\n" | grep $(foreach var,$(ARTIFACTS_VARS), $(addprefix -e ,$(var))) >> .generated_env + @sha256sum $(ARTIFACTS_IN) >> .generated_env + @sha256sum .generated_env | awk '{print $$1}' > .generated_sha256 + +# Load artifacts based on .generated_sha256 +load-artifacts: .generated_sha256 + @if [ -d "$(ARTIFACTS_PATH)/`cat $<`" ]; then\ + echo -e $(TERM_GREEN)"Fetching $(PROJECT) from $(ARTIFACTS_PATH)/`cat $<`"$(TERM_NC); \ + cp -r $(ARTIFACTS_PATH)/`cat $<`/* .; \ + fi + +# Save artifacts (this folder) based on .generated_sha256 +save-artifacts: .generated_sha256 $(PROJECT).xpr + @if [ ! -d "$(ARTIFACTS_PATH)/`cat .generated_sha256`" ]; then \ + cp -r . $(ARTIFACTS_PATH)/`cat .generated_sha256`; \ + chmod -R g+rw $(ARTIFACTS_PATH)/`cat .generated_sha256`; \ + fi + +endif # ifeq ($(USE_ARTIFACTS),1) diff --git a/target/xilinx/xilinx_ips/xlnx_clk_wiz/Makefile b/target/xilinx/xilinx_ips/xlnx_clk_wiz/Makefile new file mode 100644 index 00000000..02481e51 --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_clk_wiz/Makefile @@ -0,0 +1,10 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +PROJECT:=xlnx_clk_wiz +# The files and variables on which the IP configuration depends +ARTIFACTS_IN:=Makefile tcl/run.tcl +ARTIFACTS_VARS:=XILINX_PART XILINX_BOARD_LONG XILINX_BOARD + +include ../common.mk diff --git a/target/xilinx/xilinx_ips/xlnx_clk_wiz/tcl/run.tcl b/target/xilinx/xilinx_ips/xlnx_clk_wiz/tcl/run.tcl new file mode 100644 index 00000000..5ae7ddb6 --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_clk_wiz/tcl/run.tcl @@ -0,0 +1,113 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD_LONG) + +set ipName xlnx_clk_wiz + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $ipName + +if {$::env(XILINX_BOARD) eq "vcu128"} { + set_property -dict [list CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.USE_RESET {true} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {120} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT2_JITTER {132.683} \ + CONFIG.CLKOUT2_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT3_JITTER {162.167} \ + CONFIG.CLKOUT3_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT4_JITTER {188.586} \ + CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ + ] [get_ips $ipName] +} + +if {$::env(XILINX_BOARD) eq "zcu102"} { + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {300.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {3.333} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {120} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {101.475} \ + CONFIG.CLKOUT1_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT2_JITTER {116.415} \ + CONFIG.CLKOUT2_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT3_JITTER {140.023} \ + CONFIG.CLKOUT3_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT4_JITTER {160.570} \ + CONFIG.CLKOUT4_PHASE_ERROR {77.836} \ + ] [get_ips $ipName] +} + +if {$::env(XILINX_BOARD) eq "genesys2"} { + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {200.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKIN1_JITTER_PS {50.0} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {20} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {50} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {100} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {112.316} \ + CONFIG.CLKOUT1_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT2_JITTER {129.198} \ + CONFIG.CLKOUT2_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT3_JITTER {155.330} \ + CONFIG.CLKOUT3_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT4_JITTER {178.053} \ + CONFIG.CLKOUT4_PHASE_ERROR {89.971} \ + ] [get_ips $ipName] +} + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/Makefile b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/Makefile similarity index 54% rename from target/xilinx/xilinx/xlnx_mig_7_ddr3/Makefile rename to target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/Makefile index 028b08d7..c076431d 100644 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/Makefile +++ b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/Makefile @@ -3,4 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 PROJECT:=xlnx_mig_7_ddr3 -include ../common.mk \ No newline at end of file +ARTIFACTS_IN:=Makefile tcl/run.tcl mig_genesys2.prj mig_kc705.prj mig_vc707.prj +ARTIFACTS_VARS:=XILINX_PART XILINX_BOARD_LONG XILINX_BOARD + +include ../common.mk diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_genesys2.prj similarity index 97% rename from target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj rename to target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_genesys2.prj index eca03782..d1551273 100755 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj +++ b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_genesys2.prj @@ -10,9 +10,9 @@ Enabled xc7k325t-ffg900/-2 4.1 - Differential + No Buffer Use System Clock - ACTIVE LOW + ACTIVE HIGH FALSE 0 50 Ohms @@ -116,9 +116,6 @@ - - - @@ -152,7 +149,7 @@ RD_PRI_REG 30 64 - 6 + 4 0 diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_kc705.prj similarity index 100% rename from target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj rename to target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_kc705.prj diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_vc707.prj similarity index 100% rename from target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj rename to target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_vc707.prj diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/tcl/run.tcl similarity index 93% rename from target/xilinx/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl rename to target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/tcl/run.tcl index 9fc5f5cd..d7224d28 100644 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl +++ b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/tcl/run.tcl @@ -5,8 +5,8 @@ # Author: Florian Zaruba set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) -set boardNameShort $::env(BOARD) +set boardName $::env(XILINX_BOARD_LONG) +set boardNameShort $::env(XILINX_BOARD) set ipName xlnx_mig_7_ddr3 diff --git a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile new file mode 100644 index 00000000..b8349e98 --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile @@ -0,0 +1,10 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +PROJECT:=xlnx_mig_ddr4 +# The files and variables on which the IP configuration depends +ARTIFACTS_IN:=Makefile tcl/run.tcl +ARTIFACTS_VARS:=XILINX_PART XILINX_BOARD_LONG XILINX_BOARD + +include ../common.mk diff --git a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl new file mode 100644 index 00000000..34fd776a --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl @@ -0,0 +1,62 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD_LONG) + +set ipName xlnx_mig_ddr4 + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name ddr4 -vendor xilinx.com -library ip -version 2.2 -module_name $ipName + + +if {$::env(XILINX_BOARD) eq "vcu128"} { + set_property -dict [list CONFIG.C0.DDR4_Clamshell {true} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.DDR4_InputClockPeriod {10000} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiAddressWidth {32} \ + CONFIG.C0.DDR4_AxiIDWidth {4} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.CS_WIDTH {2} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + ] [get_ips $ipName] + +} elseif {$::env(XILINX_BOARD) eq "zcu102"} { + set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_062} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16LY-062E} \ + CONFIG.C0.DDR4_DataWidth {16} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_AxiDataWidth {128} \ + CONFIG.C0.DDR4_AxiAddressWidth {29} \ + CONFIG.C0.DDR4_AxiIDWidth {4} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + ] [get_ips $ipName] +} + + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/target/xilinx/xilinx_ips/xlnx_vio/Makefile b/target/xilinx/xilinx_ips/xlnx_vio/Makefile new file mode 100644 index 00000000..33fb8912 --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_vio/Makefile @@ -0,0 +1,10 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +PROJECT:=xlnx_vio +# The files and variables on which the IP configuration depends +ARTIFACTS_IN:=Makefile tcl/run.tcl +ARTIFACTS_VARS:=XILINX_PART XILINX_BOARD_LONG XILINX_BOARD + +include ../common.mk diff --git a/target/xilinx/xilinx_ips/xlnx_vio/tcl/run.tcl b/target/xilinx/xilinx_ips/xlnx_vio/tcl/run.tcl new file mode 100644 index 00000000..381a13db --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_vio/tcl/run.tcl @@ -0,0 +1,41 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Cyril Koenig + +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD_LONG) + +set ipName xlnx_vio + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name $ipName + +if {$::env(XILINX_BOARD) eq "vcu128"} { +set_property -dict [list CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $ipName] +} elseif {$::env(XILINX_BOARD) eq "genesys2"} { +set_property -dict [list CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $ipName] +} + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/util/openocd_genesys2.cfg b/util/openocd_genesys2.cfg new file mode 100644 index 00000000..c7ca7d89 --- /dev/null +++ b/util/openocd_genesys2.cfg @@ -0,0 +1,34 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# OpenOCD script to connect to Cheshire through the internal VCU128 JTAG chain + +adapter driver ftdi +adapter speed 2000 +transport select jtag + +# FTF232 +ftdi_vid_pid 0x0403 0x6010 +ftdi_layout_init 0x00e8 0x60eb + +# If more than one FTDI is connected we can use the serial to differentiate. +ftdi_serial 200300A8C60D + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20002001 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +riscv set_ir idcode 0x9249 +riscv set_ir dtmcs 0x22924 +riscv set_ir dmi 0x23924 + +# Uncomment below to enable virtual addresses in GDB +#if { [catch {riscv set_enable_virtual on} ] } { +# echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } + +gdb_port 3333 +tcl_port 0 +telnet_port 0 \ No newline at end of file diff --git a/util/openocd_hs2.cfg b/util/openocd_hs2.cfg new file mode 100644 index 00000000..3888c577 --- /dev/null +++ b/util/openocd_hs2.cfg @@ -0,0 +1,35 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# OpenOCD script to connect to Cheshire through the Digilent JTAG-HS2 USB dongle + +adapter driver ftdi +adapter speed 2000 +transport select jtag + +# JTAG HS2 +ftdi_vid_pid 0x0403 0x6014 +ftdi_layout_init 0x00e8 0x60eb +ftdi_channel 0 + +# If more than one FTDI is connected we can use the serial to differentiate. +ftdi_serial 210249AEC334 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20002001 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +riscv set_ir idcode 0x9249 +riscv set_ir dtmcs 0x22924 +riscv set_ir dmi 0x23924 + +# Uncomment below to enable virtual addresses in GDB +#if { [catch {riscv set_enable_virtual on} ] } { +# echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } + +gdb_port 3333 +tcl_port 0 +telnet_port 0 \ No newline at end of file diff --git a/util/openocd_vcu128.cfg b/util/openocd_vcu128.cfg new file mode 100644 index 00000000..5b7e6fb8 --- /dev/null +++ b/util/openocd_vcu128.cfg @@ -0,0 +1,34 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# OpenOCD script to connect to Cheshire through the internal VCU128 JTAG chain + +adapter driver ftdi +adapter speed 2000 +transport select jtag + +# FTF232 +ftdi_vid_pid 0x0403 0x6011 +ftdi_layout_init 0x0008 0x05eb + +# If more than one FTDI is connected we can use the serial to differentiate. +ftdi_serial 091847100638 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 18 -expected-id 0x14B79093 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +riscv set_ir idcode 0x9249 +riscv set_ir dtmcs 0x22924 +riscv set_ir dmi 0x23924 + +# Uncomment below to enable virtual addresses in GDB +#if { [catch {riscv set_enable_virtual on} ] } { +# echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } + +gdb_port 3333 +tcl_port 0 +telnet_port 0 \ No newline at end of file