From eb0df30300ba1bf0398cbfdd3b81a60dcc9cb0af Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Fri, 13 Oct 2023 18:28:49 +0200 Subject: [PATCH] Disable AXI splitting checks in AXI-RT --- Bender.lock | 4 ++-- Bender.yml | 2 +- docs/um/arch.md | 6 +++++- hw/cheshire_pkg.sv | 1 + hw/cheshire_soc.sv | 47 +++++++++++++++++++++++----------------------- 5 files changed, 33 insertions(+), 27 deletions(-) diff --git a/Bender.lock b/Bender.lock index 3c3f4dc7..d683b2bd 100644 --- a/Bender.lock +++ b/Bender.lock @@ -44,8 +44,8 @@ packages: - common_cells - common_verification axi_rt: - revision: a9a5b3e91fe017da70c33b7e750b1a9eb35f31ee - version: 0.0.0-alpha.3 + revision: 2be9d4028cd3fd6617a0302a53212495a4c4e3fa + version: 0.0.0-alpha.4 source: Git: https://github.com/pulp-platform/axi_rt.git dependencies: diff --git a/Bender.yml b/Bender.yml index a6d050be..8b2b64e9 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 } axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 } axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 } - axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.3 } + axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.4 } axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 } clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 } clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 } diff --git a/docs/um/arch.md b/docs/um/arch.md index 01df2ff7..d56f4bff 100644 --- a/docs/um/arch.md +++ b/docs/um/arch.md @@ -154,7 +154,11 @@ The internal interconnect exposes the following parameters: | `(Axi|Reg)ExtNum(Mst|Slv)` | `0..15` | AXI4 and Regbus number of external Mgrs. or Subs. | | `(Axi|Reg)ExtNumRules` | `0..15` | AXI4 and Regbus number of external address rules | | `(Axi|Reg)ExtRegion*` | `doub_bt` | AXI4 and Regbus external address regions | -| `AxiRt*` | `word_bt` | AXI4 real-time traffic regulation parameters | +| `AxiRtNumPending` | `aw_bt` | Number of outstanding transactions in RT units | +| `AxiRtWBufferDepth` | `dw_bt` | The depth of the AXI-RT write buffer | +| `AxiRtNumAddrRegions` | `aw_bt` | Number of address regions for every AXI manager | +| `AxiRtCutPaths` | `bit` | Enable internal cuts in the RT units | +| `AxiRtEnableChecks` | `bit` | Enable transaction checks within the RT units | Both the AXI4 and Regbus interconnects support exposing a limited number of external manager and subordinate ports; this is the intended mechanism through which Cheshire can be integrated with wrapping SoCs' memory systems. diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 014f4ab3..5adf1ea4 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -186,6 +186,7 @@ package cheshire_pkg; dw_bt AxiRtWBufferDepth; aw_bt AxiRtNumAddrRegions; bit AxiRtCutPaths; + bit AxiRtEnableChecks; } cheshire_cfg_t; ////////////////// diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 52ba477a..a11cd1d6 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1096,29 +1096,30 @@ module cheshire_soc import cheshire_pkg::*; #( if (Cfg.AxiRt) begin : gen_axi_rt axi_rt_unit_top #( - .NumManagers ( AxiIn.num_in ), - .AddrWidth ( Cfg.AddrWidth ), - .DataWidth ( Cfg.AxiDataWidth ), - .IdWidth ( Cfg.AxiMstIdWidth ), - .UserWidth ( Cfg.AxiUserWidth ), - .NumPending ( Cfg.AxiRtNumPending ), - .WBufferDepth ( Cfg.AxiRtWBufferDepth ), - .NumAddrRegions ( Cfg.AxiRtNumAddrRegions ), - .PeriodWidth ( 32'd32 ), - .BudgetWidth ( 32'd32 ), - .RegIdWidth ( AxiSlvIdWidth ), - .CutSplitterPaths ( Cfg.AxiRtCutPaths ), - .CutDecErrors ( 1'b0 ), - .aw_chan_t ( axi_mst_aw_chan_t ), - .w_chan_t ( axi_mst_w_chan_t ), - .b_chan_t ( axi_mst_b_chan_t ), - .ar_chan_t ( axi_mst_ar_chan_t ), - .r_chan_t ( axi_mst_r_chan_t ), - .axi_req_t ( axi_mst_req_t ), - .axi_resp_t ( axi_mst_rsp_t ), - .req_req_t ( reg_req_t ), - .req_rsp_t ( reg_rsp_t ) - ) i_axi_rt_unit_top ( + .NumManagers ( AxiIn.num_in ), + .AddrWidth ( Cfg.AddrWidth ), + .DataWidth ( Cfg.AxiDataWidth ), + .IdWidth ( Cfg.AxiMstIdWidth ), + .UserWidth ( Cfg.AxiUserWidth ), + .NumPending ( Cfg.AxiRtNumPending ), + .WBufferDepth ( Cfg.AxiRtWBufferDepth ), + .NumAddrRegions ( Cfg.AxiRtNumAddrRegions ), + .PeriodWidth ( 32'd32 ), + .BudgetWidth ( 32'd32 ), + .RegIdWidth ( AxiSlvIdWidth ), + .CutSplitterPaths ( Cfg.AxiRtCutPaths ), + .DisableSplitChecks ( !Cfg.AxiRtEnableChecks ), + .CutDecErrors ( 1'b0 ), + .aw_chan_t ( axi_mst_aw_chan_t ), + .w_chan_t ( axi_mst_w_chan_t ), + .b_chan_t ( axi_mst_b_chan_t ), + .ar_chan_t ( axi_mst_ar_chan_t ), + .r_chan_t ( axi_mst_r_chan_t ), + .axi_req_t ( axi_mst_req_t ), + .axi_resp_t ( axi_mst_rsp_t ), + .req_req_t ( reg_req_t ), + .req_rsp_t ( reg_rsp_t ) + ) i_axi_rt_unit_top ( .clk_i, .rst_ni, .slv_req_i ( axi_in_req ),