From e6329161bb68f2de270d90f5a9a7c177582599a6 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 24 Nov 2023 12:12:53 +0100 Subject: [PATCH] Bump CVA6 and connect setback. --- Bender.lock | 2 +- Bender.yml | 4 ++-- hw/cva6_wrap.sv | 30 ++++++++++++++++-------------- 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/Bender.lock b/Bender.lock index 8b6a1e7b4..5d09c2639 100644 --- a/Bender.lock +++ b/Bender.lock @@ -92,7 +92,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: - revision: 498d241b3515840e828dd6d70c70b8d8e07a8592 + revision: 33557d22d4383bda7251fe5d5e854af6510349b7 version: null source: Git: https://github.com/pulp-platform/cva6.git diff --git a/Bender.yml b/Bender.yml index dd3c10430..155e25081 100644 --- a/Bender.yml +++ b/Bender.yml @@ -22,11 +22,11 @@ dependencies: clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } - cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: "498d241" } # branch: astral + cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: "33557d2" } # branch: astral iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: f5451c323350eebd5820e1c2e1772f50d8301c4a } # branch: astral + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: "f5451c32" } # branch: astral register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 } diff --git a/hw/cva6_wrap.sv b/hw/cva6_wrap.sv index fff1a5fda..010b9ec90 100644 --- a/hw/cva6_wrap.sv +++ b/hw/cva6_wrap.sv @@ -32,16 +32,16 @@ import rapid_recovery_pkg::*; input logic [NumHarts-1:0] ipi_i, input logic [NumHarts-1:0] time_irq_i, input logic [NumHarts-1:0] debug_req_i, - input logic [NumHarts-1:0] clic_irq_valid_i, // CLIC interrupt request - input logic [NumHarts-1:0][ClicNumIrqs-1:0] clic_irq_id_i, // interrupt source ID - input logic [NumHarts-1:0][7:0] clic_irq_level_i, // interrupt level is 8-bit from CLIC spec - input riscv::priv_lvl_t [NumHarts-1:0] clic_irq_priv_i, // CLIC interrupt privilege level - input logic [NumHarts-1:0] clic_irq_v_i, // CLIC interrupt virtualization bit - input logic [NumHarts-1:0][5:0] clic_irq_vsid_i, // CLIC interrupt Virtual Supervisor ID - input logic [NumHarts-1:0] clic_irq_shv_i, // selective hardware vectoring bit - output logic [NumHarts-1:0] clic_irq_ready_o, // core side interrupt hanshake (ready) - input logic [NumHarts-1:0] clic_kill_req_i, // kill request - output logic [NumHarts-1:0] clic_kill_ack_o, // kill acknowledge + input logic [NumHarts-1:0] clic_irq_valid_i, + input logic [NumHarts-1:0][ClicNumIrqs-1:0] clic_irq_id_i, + input logic [NumHarts-1:0][7:0] clic_irq_level_i, + input riscv::priv_lvl_t [NumHarts-1:0] clic_irq_priv_i, + input logic [NumHarts-1:0] clic_irq_v_i, + input logic [NumHarts-1:0][5:0] clic_irq_vsid_i, + input logic [NumHarts-1:0] clic_irq_shv_i, + output logic [NumHarts-1:0] clic_irq_ready_o, + input logic [NumHarts-1:0] clic_kill_req_i, + output logic [NumHarts-1:0] clic_kill_ack_o, output axi_req_t [NumHarts-1:0] axi_req_o, input axi_rsp_t [NumHarts-1:0] axi_rsp_i ); @@ -70,6 +70,7 @@ typedef struct packed { axi_req_t axi_req; } cva6_outputs_t; +logic [NumHarts-1:0] core_setback; cva6_inputs_t [NumHarts-1:0] sys2hmr, hmr2core; cva6_outputs_t [NumHarts-1:0] hmr2sys, core2hmr; @@ -110,6 +111,7 @@ for (genvar i = 0; i < NumHarts; i++) begin: gen_cva6_cores ) i_core_cva6 ( .clk_i ( clk_i ), .rst_ni ( rstn_i ), + .clear_i ( core_setback[i] ), .boot_addr_i ( hmr2core[i].bootaddress ), .hart_id_i ( hmr2core[i].hart_id ), .irq_i ( hmr2core[i].irq ), @@ -180,10 +182,10 @@ hmr_unit #( .sys_fetch_en_i ( '0 ), // TODO? .enable_bus_vote_i ( '0 ), // TODO? - .core_setback_o ( /* TODO */ ), - .core_inputs_o ( hmr2core ), - .core_nominal_outputs_i ( core2hmr ), - .core_bus_outputs_i ( '0 ) // TODO? + .core_setback_o ( core_setback ), + .core_inputs_o ( hmr2core ), + .core_nominal_outputs_i ( core2hmr ), + .core_bus_outputs_i ( '0 ) // TODO? ); endmodule: cva6_wrap