diff --git a/Bender.lock b/Bender.lock index 7a8fd5bff..70ff87a3f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -162,7 +162,7 @@ packages: - register_interface - tech_cells_generic pulp-ethernet: - revision: a80c246da972dabd7cd4fb6ec5ac8c83e613f0a3 + revision: 716b486b6c0e22ab31a75e162336cfe69738fc69 version: null source: Git: https://github.com/pulp-platform/pulp-ethernet.git diff --git a/Bender.yml b/Bender.yml index c738df3d3..e4c3328d9 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } - pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "a80c246" } # branch: chs-hs + pulp-ethernet: { git: "https://github.com/pulp-platform/pulp-ethernet.git", rev: "716b486" } # branch: chs-hs export_include_dirs: - hw/include diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 82edee3be..29022c51d 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1312,7 +1312,7 @@ module cheshire_soc import cheshire_pkg::*; #( .TFLenWidth ( 32'd20 ), .MemSysDepth ( 32'd0 ), .TxFifoLogDepth ( 32'd5 ), - .RxFifoLogDepth ( 32'd10 ), + .RxFifoLogDepth ( 32'd8 ), .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), .reg_req_t ( reg_req_t ), diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index e5bf3098f..5bfdbd2a7 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -21,6 +21,10 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clk] set SOC_TCK 20.0 set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]] +set_clock_groups -asynchronous \ + -group [get_clocks clk_50_clkwiz] \ + -group [get_clocks clk_pll_i] + ############ # Switches # ############ @@ -156,7 +160,7 @@ set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports { eth_rst_n ############################################# # Modified for 125MHz receive clock create_clock -period 8.000 -name eth_rxck [get_ports eth_rxck] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_rxck_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_rxck_IBUF] set_clock_groups -asynchronous -group [get_clocks eth_rxck -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_clkwiz/clk_125]]