From d2cae18844ef5d470770e8fd5a1613d8487975c7 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Thu, 25 Jan 2024 14:37:23 +0100 Subject: [PATCH] xilinx: Finishing vanilla makefile flow --- .gitignore | 14 ++- Bender.yml | 7 +- cheshire.mk | 2 +- sw/boot/cheshire_vcu128_bd.dts | 27 ----- .../xilinx/flavor_vanilla/flavor_vanilla.mk | 16 ++- .../flavor_vanilla/sim/run_simulation.tcl | 20 +--- .../flavor_vanilla/sim/setup_simulation.tcl | 14 ++- target/xilinx/flavor_vanilla/sim/sim.mk | 29 +++-- .../xilinx/flavor_vanilla/sim/sim_tb_top.diff | 107 +++++++++++++++++ .../flavor_vanilla/src/dram_wrapper_xilinx.sv | 108 +++++++----------- target/xilinx/xilinx.mk | 91 +++++++-------- target/xilinx/xilinx_ips/.gitignore | 5 - target/xilinx/xilinx_ips/common.mk | 65 ----------- target/xilinx/xilinx_ips/xilinx_ips.mk | 80 +++++++++++++ .../xilinx/xilinx_ips/xlnx_clk_wiz/Makefile | 10 -- .../xilinx_ips/xlnx_clk_wiz/xlnx_clk_wiz.mk | 8 ++ .../xilinx_ips/xlnx_mig_7_ddr3/Makefile | 9 -- .../xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.mk | 8 ++ .../xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile | 10 -- .../xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl | 20 +--- .../xilinx_ips/xlnx_mig_ddr4/xlnx_mig_ddr4.mk | 8 ++ target/xilinx/xilinx_ips/xlnx_vio/Makefile | 10 -- target/xilinx/xilinx_ips/xlnx_vio/xlnx_vio.mk | 8 ++ 23 files changed, 363 insertions(+), 313 deletions(-) delete mode 100644 sw/boot/cheshire_vcu128_bd.dts create mode 100644 target/xilinx/flavor_vanilla/sim/sim_tb_top.diff delete mode 100644 target/xilinx/xilinx_ips/.gitignore delete mode 100644 target/xilinx/xilinx_ips/common.mk create mode 100644 target/xilinx/xilinx_ips/xilinx_ips.mk delete mode 100644 target/xilinx/xilinx_ips/xlnx_clk_wiz/Makefile create mode 100644 target/xilinx/xilinx_ips/xlnx_clk_wiz/xlnx_clk_wiz.mk delete mode 100644 target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/Makefile create mode 100644 target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.mk delete mode 100644 target/xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile create mode 100644 target/xilinx/xilinx_ips/xlnx_mig_ddr4/xlnx_mig_ddr4.mk delete mode 100644 target/xilinx/xilinx_ips/xlnx_vio/Makefile create mode 100644 target/xilinx/xilinx_ips/xlnx_vio/xlnx_vio.mk diff --git a/.gitignore b/.gitignore index 6ff6a9bfc..e82b8d94e 100644 --- a/.gitignore +++ b/.gitignore @@ -28,10 +28,22 @@ sw/deps/.patched # Test models target/sim/models -# VSIM generated files +# VSIM generated files target/sim/vsim/compile.*.tcl target/sim/vsim/*.log target/sim/vsim/modelsim.ini target/sim/vsim/transcript target/sim/vsim/vsim.wlf target/sim/vsim/work/ + +# Xilinx flow generated files +*.generated_env +*.generated_sha256 + +# Vivado generated files +*.cache +*.gen +*.hw +*.runs +*.xpr +*.xci diff --git a/Bender.yml b/Bender.yml index f0eb15634..c5eb90b88 100644 --- a/Bender.yml +++ b/Bender.yml @@ -50,14 +50,9 @@ sources: - target/sim/src/fixture_cheshire_soc.sv - target/sim/src/tb_cheshire_soc.sv - - target: all(fpga, xilinx, xilinx_vanilla) + - target: all(fpga, xilinx, flavor_vanilla) files: - target/xilinx/flavor_vanilla/src/fan_ctrl.sv - target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv - target/xilinx/flavor_vanilla/src/phy_definitions.svh - target/xilinx/flavor_vanilla/src/cheshire_top_xilinx.sv - - - target: all(fpga, xilinx, xilinx_bd) - files: - - target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v - - target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv diff --git a/cheshire.mk b/cheshire.mk index e600ebbd6..04c02ceae 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -53,7 +53,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= d31389c3b559e48496b7264a55ae33eda994bded +CHS_NONFREE_COMMIT ?= 56c4095b3ecf88beb5b71867134d596904f3558d chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree diff --git a/sw/boot/cheshire_vcu128_bd.dts b/sw/boot/cheshire_vcu128_bd.dts deleted file mode 100644 index c2a3528d5..000000000 --- a/sw/boot/cheshire_vcu128_bd.dts +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Cyril Koenig - -/include/ "cheshire.dtsi" - -&spi { - boot-with = <1>; - nor@1 { - #address-cells = <0x1>; - #size-cells = <0x1>; - // Note : u-boot does not find mt25qu02g - compatible = "mt25qu02g", "jedec,spi-nor"; - reg = <0x1>; // CS - spi-max-frequency = <25000000>; - spi-rx-bus-width = <0x1>; - spi-tx-bus-width = <0x1>; - disable-wp; - partition@0 { - label = "all"; - reg = <0x0 0x6000000>; // 96 MB - read-only; - }; - }; -}; diff --git a/target/xilinx/flavor_vanilla/flavor_vanilla.mk b/target/xilinx/flavor_vanilla/flavor_vanilla.mk index 5446ab893..84bfb1974 100644 --- a/target/xilinx/flavor_vanilla/flavor_vanilla.mk +++ b/target/xilinx/flavor_vanilla/flavor_vanilla.mk @@ -24,8 +24,8 @@ xilinx_ips_paths_vanilla := $(foreach ip-name,$(xilinx_ips_names_vanil # Flavor specific bender args # (add the enabled ips in bender args, used by phy_definitions.svh) -xilinx_targs_vanilla := $(foreach ip-name,$(xilinx_ips_names_vanilla),$(addprefix -t ,$(ip-name))) -xilinx_targs_vanilla += -t xilinx_vanilla +xilinx_targs_vanilla := $(xilinx_targs_common) $(foreach ip-name,$(xilinx_ips_names_vanilla),$(addprefix -t ,$(ip-name))) +xilinx_targs_vanilla += -t flavor_vanilla # Vivado variables vivado_env_vanilla := \ @@ -48,15 +48,19 @@ vivado_env_vanilla := \ # Generate bender script $(CHS_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl: Bender.yml - $(BENDER) script vivado $(xilinx_targs) $(xilinx_targs_vanilla) > $@ + $(BENDER) script vivado $(xilinx_targs_vanilla) > $@ # Compile bitstream $(CHS_XIL_DIR)/flavor_vanilla/out/%.bit: $(xilinx_ips_paths_vanilla) $(CHS_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl @mkdir -p $(CHS_XIL_DIR)/flavor_vanilla/out - cd $(CHS_XIL_DIR)/flavor_vanilla && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl + cd $(CHS_XIL_DIR)/flavor_vanilla && $(vivado_env_vanilla) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl find $(CHS_XIL_DIR)/flavor_vanilla -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CHS_XIL_DIR)/flavor_vanilla/out chs-xil-clean-vanilla: - cd $(CHS_XIL_DIR)/flavor_vanilla && rm -rf scripts/add_sources.tcl* *.log *.jou *.str *.mif carfield.* .Xil/ + cd $(CHS_XIL_DIR)/flavor_vanilla && rm -rf scripts/add_sources.tcl *.log *.jou cheshire.* .Xil/ -.PHONY: chs-xil-clean-vanilla \ No newline at end of file +.PHONY: chs-xil-clean-vanilla + +# Add simulation rules to verify Xilinx IP integration + +include $(CHS_XIL_DIR)/flavor_vanilla/sim/sim.mk diff --git a/target/xilinx/flavor_vanilla/sim/run_simulation.tcl b/target/xilinx/flavor_vanilla/sim/run_simulation.tcl index b02604606..3152f52e7 100644 --- a/target/xilinx/flavor_vanilla/sim/run_simulation.tcl +++ b/target/xilinx/flavor_vanilla/sim/run_simulation.tcl @@ -3,46 +3,34 @@ # SPDX-License-Identifier: SHL-0.51 # # Cyril Koenig - -source ../scripts/add_sources_vsim.tcl - +source add_sources_vsim.tcl if {[string first "xlnx_clk_wiz" $::env(IPS)] != -1} { source ips/xlnx_clk_wiz/questa/compile.do - if {[string first "xlnx_vio" $::env(IPS)] != -1} { source ips/xlnx_vio/questa/compile.do }} - if {[string first "xlnx_mig_7_ddr3" $::env(IPS)] != -1} { source ips/xlnx_mig_7_ddr3_ex/questa/compile.do source ips/xlnx_mig_7_ddr3/questa/compile.do - vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_7_ddr3_ex/questa/srcs/sim_tb_top.v" + vlog -work work ips/xlnx_mig_7_ddr3_ex/imports/sim_tb_top.v -L xil_defaultlib } - if {[string first "xlnx_mig_ddr4" $::env(IPS)] != -1} { source ips/xlnx_mig_ddr4_ex/questa/compile.do source ips/xlnx_mig_ddr4/questa/compile.do - vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_ddr4_ex/questa/srcs/sim_tb_top.sv" + vlog -work work ips/xlnx_mig_ddr4_ex/imports/sim_tb_top.sv -L xil_defaultlib } - -# Note : this testbench does not implenent the ddr4 memory model +## Note : this testbench does not implenent the ddr4 memory model set TESTBENCH "work.sim_tb_top xil_defaultlib.glbl" - set XLIB_ARGS "-L secureip -L xpm -L unisims_ver -L unimacro_ver -L work -L xil_defaultlib" - if {![info exists VOPTARGS]} { set VOPTARGS "+acc" } - set flags "-permissive -suppress 3009 -suppress 8386 -error 7" - set pargs "" if {[info exists BOOTMODE]} { append pargs "+BOOTMODE=${BOOTMODE} " } if {[info exists PRELMODE]} { append pargs "+PRELMODE=${PRELMODE} " } if {[info exists BINARY]} { append pargs "+BINARY=${BINARY} " } if {[info exists IMAGE]} { append pargs "+IMAGE=${IMAGE} " } - eval "vsim ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${XLIB_ARGS} ${pargs} ${flags} - set StdArithNoWarnings 1 set NumericStdNoWarnings 1 diff --git a/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl b/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl index a14d1b922..adf361c12 100644 --- a/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl +++ b/target/xilinx/flavor_vanilla/sim/setup_simulation.tcl @@ -11,7 +11,7 @@ if { $argc == 1 } { set command [lindex $argv 0] } -puts "Running with SIMULATOR_PATH=$::env(SIMULATOR_PATH) ; GCC_PATH=$::env(GCC_PATH) ; XILINX_SIMLIB_PATH=$::env(XILINX_SIMLIB_PATH)" +puts "Running with SIMULATOR_PATH=$::env(SIMULATOR_PATH) ; GCC_PATH=$::env(GCC_PATH) ; XILINX_SIMLIB_PATH=$::env(XILINX_SIMLIB_PATH) ; VIVADO_PROJECT=$::env(VIVADO_PROJECT)" # Compile the vivado simlib to XILINX_SIMLIB_PATH if { $command == "compile_simlib" } { @@ -26,6 +26,18 @@ if { $command == "compile_simlib" } { export_simulation -simulator questa -directory "./ips" -lib_map_path "$::env(XILINX_SIMLIB_PATH)" \ -absolute_path -force -of_objects [get_ips *] +# Export simulation scripts for each ip +} elseif { $command == "export_example" } { + open_project $::env(VIVADO_PROJECT) + open_example_project -dir "./ips" -force [get_ips xlnx_mig_*] + +# Export simulation scripts for each ip +} elseif { $command == "export_example_simulation" } { + open_project $::env(VIVADO_PROJECT) + export_simulation -lib_map_path "$::env(XILINX_SIMLIB_PATH)" -directory "." -simulator questa \ + -ip_user_files_dir "./ips/$::env(DDR_EXAMPLE)/$::env(DDR_EXAMPLE).ip_user_files" \ + -ipstatic_source_dir "./ips/$::env(DDR_EXAMPLE)/$::env(DDR_EXAMPLE).ip_user_files/ipstatic" -use_ip_compiled_libs -directory "./ips/$::env(DDR_EXAMPLE)/" -absolute_path + # Unknown command } else { puts "[$argv0] Unknown command: $command" diff --git a/target/xilinx/flavor_vanilla/sim/sim.mk b/target/xilinx/flavor_vanilla/sim/sim.mk index 2153b9bde..042eb3465 100644 --- a/target/xilinx/flavor_vanilla/sim/sim.mk +++ b/target/xilinx/flavor_vanilla/sim/sim.mk @@ -11,27 +11,28 @@ SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin # Compile script for each IP model -chs-ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names))) +chs-ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(xilinx_ips_names_vanilla))) # Getting the DDR model requires exporting the Vivado example project for the controller's IP -chs-ddr-example-project := $(filter xlnx_mig_,$(ips-names))_ex -chs-ddr-sim-script := $(CHS_XIL_SIM_DIR)/ips/$(chs-ddr-example-projects)/questa/compile.do +chs-ddr-example-name := $(filter xlnx_mig_%,$(xilinx_ips_names_vanilla))_ex +chs-ddr-sim-script := $(CHS_XIL_SIM_DIR)/ips/$(chs-ddr-example-name)/questa/compile.do -chs-vivado-env-sim := $(VIVADOENV) \ +chs-vivado-env-sim := $(vivado_env_vanilla) \ XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \ SIMULATOR_PATH=$(SIMULATOR_PATH) \ GCC_PATH=$(GCC_PATH) \ - VIVADO_PROJECT=$(CHS_XIL_DIR)/flavor_vanilla/chesire.xpr + VIVADO_PROJECT=$(CHS_XIL_DIR)/flavor_vanilla/cheshire.xpr + chs-xil-vlog-args := -suppress 2583 -suppress 13314 # First generate the generic Xilinx simulation libraries for questa $(XILINX_SIMLIB_PATH)/modelsim.ini: - cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" + cd $(CHS_XIL_SIM_DIR) && $(chs-vivado-env-sim) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" # Then generate the IP models for the project cheshire.xpr $(CHS_XIL_SIM_DIR)/ips/%/questa/compile.do: mkdir -p $(CHS_XIL_SIM_DIR)/ips - cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" + cd $(CHS_XIL_SIM_DIR) && $(chs-vivado-env-sim) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" # Get the DRAM simulation models $(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: @@ -39,22 +40,26 @@ $(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: # First create the example project cd $(CHS_XIL_SIM_DIR) && $(chs-vivado-env-sim) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example" # Then export the simulation models - cd $(CHS_XIL_SIM_DIR) && $(chs-vivado-env-sim) VIVADO_PROJECT=$(CHS_XIL_SIM_DIR)/ips/$*_ex/$*_ex.xpr $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example_simulation" + cd $(CHS_XIL_SIM_DIR) && $(chs-vivado-env-sim) DDR_EXAMPLE=$(chs-ddr-example-name) VIVADO_PROJECT=$(CHS_XIL_SIM_DIR)/ips/$*_ex/$*_ex.xpr $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example_simulation" # And replace the DUT by cheshire top - patch $(CHS_XIL_SIM_DIR)/ips/$*_ex/imports/sim_tb_top.sv $(CHS_XIL_SIM_DIR)/sim_tb_top.diff + cp $(CHS_XIL_SIM_DIR)/ips/$*_ex/imports/sim_tb_top.*v $(CHS_XIL_SIM_DIR)/ips/$*_ex/imports/sim_tb_top_copy.*v + patch $(CHS_XIL_SIM_DIR)/ips/$*_ex/imports/sim_tb_top.*v $(CHS_XIL_SIM_DIR)/sim_tb_top.diff # Export the Cheshire questa compile script $(CHS_XIL_SIM_DIR)/add_sources_vsim.tcl: - $(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(chs-xil-vlog-args)" > $@ + $(BENDER) script vsim -t sim -t test $(xilinx_targs_vanilla) --vlog-arg="$(chs-xil-vlog-args)" > $@ # Run all chs-xil-sim: $(CHS_XIL_DIR)/flavor_vanilla/cheshire.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(chs-ddr-sim-script) $(chs-ip-sim-scripts) $(CHS_XIL_SIM_DIR)/add_sources_vsim.tcl mkdir -p $(CHS_XIL_SIM_DIR)/questa_lib cp $(XILINX_SIMLIB_PATH)/modelsim.ini $(CHS_XIL_SIM_DIR) chmod +w $(CHS_XIL_SIM_DIR)/modelsim.ini - cd $(CHS_XIL_SIM_DIR) && IPS="$(ips-names)" questa-2022.3 vsim -work work -do "run_simulation.tcl" + cd $(CHS_XIL_SIM_DIR) && IPS="$(xilinx_ips_names_vanilla)" questa-2022.3 vsim -work work -do "run_simulation.tcl" + +testt: + echo $(filter xlnx_mig_%,$(xilinx_ips_names_vanilla))_ex chs-xil-clean-sim: - cd $(CHS_XIL_SIM_DIR) && rm -rf *.log questa_lib work transcript vsim.wlf vsim_cheshire.tcl .Xil modelsim.ini + cd $(CHS_XIL_SIM_DIR) && rm -rf *.log questa_lib work transcript vsim.wlf vsim_cheshire.tcl .Xil modelsim.ini ips .PHONY: clean-sim sim diff --git a/target/xilinx/flavor_vanilla/sim/sim_tb_top.diff b/target/xilinx/flavor_vanilla/sim/sim_tb_top.diff new file mode 100644 index 000000000..4a75d2bbc --- /dev/null +++ b/target/xilinx/flavor_vanilla/sim/sim_tb_top.diff @@ -0,0 +1,107 @@ +437,438c437,463 +< example_top # +< ( +--- +> wire cpu_reset; +> wire cpu_resetn; +> `ifdef TARGET_XLNX_MIG_DDR4 +> wire sys_clk_p; +> wire sys_clk_n; +> `endif +> wire testmode_i; +> wire [1:0] boot_mode_i; +> wire jtag_tck_i; +> wire jtag_tms_i; +> wire jtag_tdi_i; +> wire jtag_tdo_o; +> wire jtag_trst_ni; +> wire jtag_vdd_o; +> wire jtag_gnd_o; +> wire uart_tx_o; +> wire uart_rx_i; +> +> assign cpu_reset = sys_rst; +> assign cpu_resetn = ~cpu_reset; +> assign boot_mode_i = '0; +> assign testmode_i = '0; +> assign jtag_tck_i = '0; +> assign jtag_tms_i = '0; +> assign jtag_tdi_i = '0; +> assign jtag_trst_ni = '0; +> assign uart_rx_i = '0; +440,443c465,468 +< .SIMULATION (SIMULATION), +< .BEGIN_ADDRESS (BEGIN_ADDRESS), +< .END_ADDRESS (END_ADDRESS), +< .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), +--- +> `ifdef TARGET_XLNX_MIG_DDR4 +> assign sys_clk_p = c0_sys_clk_p; +> assign sys_clk_n = c0_sys_clk_n; +> `endif +445,457d469 +< .COL_WIDTH (COL_WIDTH), +< .CS_WIDTH (CS_WIDTH), +< .DM_WIDTH (DM_WIDTH), +< +< .DQ_WIDTH (DQ_WIDTH), +< .DQS_CNT_WIDTH (DQS_CNT_WIDTH), +< .DRAM_WIDTH (DRAM_WIDTH), +< .ECC_TEST (ECC_TEST), +< .RANKS (RANKS), +< .ROW_WIDTH (ROW_WIDTH), +< .ADDR_WIDTH (ADDR_WIDTH), +< .BURST_MODE (BURST_MODE), +< .TCQ (TCQ), +459,473c471,472 +< +< .DRAM_TYPE (DRAM_TYPE), +< +< +< .nCK_PER_CLK (nCK_PER_CLK), +< +< +< .C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH), +< .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH), +< .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), +< .C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST), +< +< .DEBUG_PORT (DEBUG_PORT), +< +< .RST_ACT_LOW (RST_ACT_LOW) +--- +> cheshire_top_xilinx # +> ( +475c474 +< u_ip_top +--- +> u_cheshire_top_xilinx +477,502c476 +< +< .ddr3_dq (ddr3_dq_fpga), +< .ddr3_dqs_n (ddr3_dqs_n_fpga), +< .ddr3_dqs_p (ddr3_dqs_p_fpga), +< +< .ddr3_addr (ddr3_addr_fpga), +< .ddr3_ba (ddr3_ba_fpga), +< .ddr3_ras_n (ddr3_ras_n_fpga), +< .ddr3_cas_n (ddr3_cas_n_fpga), +< .ddr3_we_n (ddr3_we_n_fpga), +< .ddr3_reset_n (ddr3_reset_n), +< .ddr3_ck_p (ddr3_ck_p_fpga), +< .ddr3_ck_n (ddr3_ck_n_fpga), +< .ddr3_cke (ddr3_cke_fpga), +< .ddr3_cs_n (ddr3_cs_n_fpga), +< +< .ddr3_dm (ddr3_dm_fpga), +< +< .ddr3_odt (ddr3_odt_fpga), +< +< +< .sys_clk_i (sys_clk_i), +< +< .init_calib_complete (init_calib_complete), +< .tg_compare_error (tg_compare_error), +< .sys_rst (sys_rst) +--- +> .* diff --git a/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv b/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv index 106986164..4804745b1 100644 --- a/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv @@ -1,8 +1,10 @@ -// Copyright 2023 ETH Zurich and University of Bologna. +// Copyright 2024 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // // Cyril Koenig +// +// Resize AXI AW IW DW before connecting to a Xilinx DRAM controller `include "cheshire/typedef.svh" @@ -48,23 +50,23 @@ module dram_wrapper_xilinx #( integer StrobeWidth; } dram_cfg_t; -`ifdef TARGET_VCU128 +`ifdef TARGET_VCU118 localparam dram_cfg_t cfg = '{ EnCDC : 1, // 333 MHz axi (attention CDC logdepth) IdWidth : 4, - AddrWidth : 32, + AddrWidth : 31, DataWidth : 512, StrobeWidth : 64 }; `endif -`ifdef TARGET_ZCU102 +`ifdef TARGET_VCU128 localparam dram_cfg_t cfg = '{ - EnCDC : 1, // ??? MHz axi (attention CDC logdepth) - IdWidth : 4, - AddrWidth : 29, - DataWidth : 128, - StrobeWidth : 16 + EnCDC : 1, // 333 MHz axi (attention CDC logdepth) + IdWidth : 8, + AddrWidth : 32, + DataWidth : 512, + StrobeWidth : 64 }; `endif @@ -116,45 +118,39 @@ module dram_wrapper_xilinx #( // Instianciate data width resizer // ///////////////////////////////////// - if (cfg.DataWidth != SoC_DataWidth) begin : gen_dw_converter - axi_dw_converter #( - .AxiMaxReads (8), - .AxiSlvPortDataWidth(SoC_DataWidth), - .AxiMstPortDataWidth(cfg.DataWidth), - .AxiAddrWidth (SoC_AddrWidth), - .AxiIdWidth (SoC_IdWidth ), - // Common aw, ar, b - .aw_chan_t (axi_soc_aw_chan_t), - .b_chan_t (axi_soc_b_chan_t), - .ar_chan_t (axi_soc_ar_chan_t), - // Master w, r - .mst_w_chan_t (axi_dw_w_chan_t), - .mst_r_chan_t (axi_dw_r_chan_t), - .axi_mst_req_t (axi_dw_req_t), - .axi_mst_resp_t (axi_dw_resp_t), - // Slave w, r - .slv_w_chan_t (axi_soc_w_chan_t), - .slv_r_chan_t (axi_soc_r_chan_t), - .axi_slv_req_t (axi_soc_req_t), - .axi_slv_resp_t (axi_soc_resp_t) - ) axi_dw_converter_ddr4 ( - .clk_i (soc_clk_i), - .rst_ni (soc_resetn_i), - .slv_req_i (soc_dresizer_req), - .slv_resp_o(soc_dresizer_rsp), - .mst_req_o (dresizer_iresizer_req), - .mst_resp_i(dresizer_iresizer_rsp) - ); - end else begin : gen_no_dw_converter - assign dresizer_iresizer_req = soc_dresizer_req; - assign soc_dresizer_rsp = dresizer_iresizer_rsp; - end + axi_dw_converter #( + .AxiMaxReads (8), + .AxiSlvPortDataWidth(SoC_DataWidth), + .AxiMstPortDataWidth(cfg.DataWidth), + .AxiAddrWidth (SoC_AddrWidth), + .AxiIdWidth (SoC_IdWidth ), + // Common aw, ar, b + .aw_chan_t (axi_soc_aw_chan_t), + .b_chan_t (axi_soc_b_chan_t), + .ar_chan_t (axi_soc_ar_chan_t), + // Master w, r + .mst_w_chan_t (axi_dw_w_chan_t), + .mst_r_chan_t (axi_dw_r_chan_t), + .axi_mst_req_t (axi_dw_req_t), + .axi_mst_resp_t (axi_dw_resp_t), + // Slave w, r + .slv_w_chan_t (axi_soc_w_chan_t), + .slv_r_chan_t (axi_soc_r_chan_t), + .axi_slv_req_t (axi_soc_req_t), + .axi_slv_resp_t (axi_soc_resp_t) + ) axi_dw_converter_ddr4 ( + .clk_i (soc_clk_i), + .rst_ni (soc_resetn_i), + .slv_req_i (soc_dresizer_req), + .slv_resp_o(soc_dresizer_rsp), + .mst_req_o (dresizer_iresizer_req), + .mst_resp_i(dresizer_iresizer_rsp) + ); ///////////////// // ID resizer // ///////////////// -if (cfg.IdWidth != SoC_IdWidth) begin : gen_iw_converter axi_iw_converter #( .AxiAddrWidth ( SoC_AddrWidth ), .AxiDataWidth ( cfg.DataWidth ), @@ -178,10 +174,6 @@ if (cfg.IdWidth != SoC_IdWidth) begin : gen_iw_converter .mst_req_o ( iresizer_cdc_req ), .mst_resp_i ( iresizer_cdc_rsp ) ); - end else begin : gen_no_iw_converter - assign iresizer_cdc_req = dresizer_iresizer_req; - assign dresizer_iresizer_rsp = iresizer_cdc_rsp; - end ////////////////////// // Instianciate CDC // @@ -278,26 +270,6 @@ if (cfg.IdWidth != SoC_IdWidth) begin : gen_iw_converter .c0_ddr4_s_axi_rresp (cdc_dram_rsp.r.resp), .c0_ddr4_s_axi_rlast (cdc_dram_rsp.r.last), .c0_ddr4_s_axi_rvalid (cdc_dram_rsp.r_valid), -`ifdef TARGET_VCU128 - // Axi ctrl - .c0_ddr4_s_axi_ctrl_awvalid('0), - .c0_ddr4_s_axi_ctrl_awready(), - .c0_ddr4_s_axi_ctrl_awaddr ('0), - .c0_ddr4_s_axi_ctrl_wvalid ('0), - .c0_ddr4_s_axi_ctrl_wready (), - .c0_ddr4_s_axi_ctrl_wdata ('0), - .c0_ddr4_s_axi_ctrl_bvalid (), - .c0_ddr4_s_axi_ctrl_bready ('0), - .c0_ddr4_s_axi_ctrl_bresp (), - .c0_ddr4_s_axi_ctrl_arvalid('0), - .c0_ddr4_s_axi_ctrl_arready(), - .c0_ddr4_s_axi_ctrl_araddr ('0), - .c0_ddr4_s_axi_ctrl_rvalid (), - .c0_ddr4_s_axi_ctrl_rready ('0), - .c0_ddr4_s_axi_ctrl_rdata (), - .c0_ddr4_s_axi_ctrl_rresp (), - .c0_ddr4_interrupt (), -`endif // Others .c0_init_calib_complete (), // keep open .addn_ui_clkout1 (dram_clk_o), @@ -374,4 +346,4 @@ if (cfg.IdWidth != SoC_IdWidth) begin : gen_iw_converter ); `endif // USE_DDR3 -endmodule +endmodule \ No newline at end of file diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 2105756d1..b0f0d7842 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -15,26 +15,27 @@ # User input Makefile variables # +# +# Makefile variables (user inputs are in capital letters) +# + CHS_XIL_DIR ?= $(CHS_ROOT)/target/xilinx -XILINX_PROJECT ?= cheshire -XILINX_FLAVOR ?= vanilla -XILINX_BOARD ?= genesys2 -XILINX_ELABORATION_ONLY ?= 0 -XILINX_CHECK_TIMING ?= 0 -XILINX_USE_ARTIFACTS ?= 0 +VIVADO ?= vitis-2020.2 vivado -ifneq (,$(wildcard /etc/iis.version)) - VIVADO ?= vitis-2020.2 vivado -else - VIVADO ?= vivado -endif -VIVADO_MODE ?= batch -VIVADO_FLAGS ?= -nojournal -mode $(VIVADO_MODE) +XILINX_PROJECT ?= cheshire +# XILINX_FLAVOR in {vanilla} +XILINX_FLAVOR ?= vanilla +# XILINX_BOARD in {vcu128, genesys2} +XILINX_BOARD ?= vcu128 -# -# Derived variables -# +ifeq ($(XILINX_BOARD),vcu128) + xilinx_part := xcvu37p-fsvh2892-2L-e + xilinx_board_long := xilinx.com:vcu128:part0:1.0 + XILINX_PORT ?= 3232 + XILINX_FPGA_PATH ?= xilinx_tcf/Xilinx/091847100638A + XILINX_HOST ?= bordcomputer +endif ifeq ($(XILINX_BOARD),genesys2) xilinx_part := xc7k325tffg900-2 @@ -44,43 +45,45 @@ ifeq ($(XILINX_BOARD),genesys2) XILINX_HOST ?= bordcomputer endif -ifeq ($(XILINX_BOARD),vcu128) - xilinx_part := xcvu37p-fsvh2892-2L-e - xilinx_board_long := xilinx.com:vcu128:part0:1.0 - XILINX_PORT ?= 3232 - XILINX_FPGA_PATH ?= xilinx_tcf/Xilinx/091847100638A - XILINX_HOST ?= bordcomputer -endif +XILINX_USE_ARTIFACTS ?= 0 +XILINX_ARTIFACTS_ROOT ?= +XILINX_ELABORATION_ONLY ?= 0 +XILINX_CHECK_TIMING ?= 0 + +VIVADO_MODE ?= batch +VIVADO_FLAGS ?= -nojournal -mode $(VIVADO_MODE) -xilinx_ip_dir := $(CHS_XIL_DIR)/xilinx_ips -xilinx_ip_dirs := $(wildcard $(xilinx_ip_dir)/*) +xilinx_ip_dir := $(CHS_XIL_DIR)/xilinx_ips +xilinx_bit := $(CHS_XIL_DIR)/out/$(XILINX_PROJECT)_$(XILINX_FLAVOR)_$(XILINX_BOARD).bit -xilinx_targs := -t cv64a6_imafdcsclic_sv39 -t cva6 -xilinx_targs += -t fpga $(addprefix -t ,$(XILINX_BOARD)) +xilinx_targs_common := -t fpga -t xilinx -t cv64a6_imafdcsclic_sv39 -t cva6 +xilinx_targs_common += $(addprefix -t ,$(XILINX_BOARD)) # -# Include flavors +# Include other makefiles flavors # include $(CHS_XIL_DIR)/flavor_vanilla/flavor_vanilla.mk -include $(CHS_XIL_DIR)/flavor_bd/flavor_bd.mk # # Flavor dependant variables # -xilinx_bit := $(CHS_XIL_DIR)/out/$(XILINX_PROJECT)_$(XILINX_FLAVOR)_$(XILINX_BOARD).bit vivado_env := $(vivado_env_$(XILINX_FLAVOR)) +xilinx_targs := $(xilinx_targs_$(XILINX_FLAVOR)) +xilinx_defs := $(xilinx_defs_$(XILINX_FLAVOR)) # -# Targets +# IPs compile rules # -# Generate ips -%.xci: - echo $@ - @echo "Generating IP $(basename $@)" - IP_NAME=$(basename $(notdir $@)) ; cd $(xilinx_ip_dir)/$$IP_NAME && make clean && XILINX_USE_ARTIFACTS=$(XILINX_USE_ARTIFACTS) vivado_env="$(subst ",\",$(vivado_env))" VIVADO="$(VIVADO)" make +# Note: at the moment xilinx_ips uses vivado_env defined above, +# but it could re-define its own vivado_env and xilinx_targs +include $(CHS_XIL_DIR)/xilinx_ips/xilinx_ips.mk + +# +# Top level compile rules +# # Copy bitstream and probe file to final output location (/target/xilinx/out) $(CHS_XIL_DIR)/out/%.bit: $(xilinx_bit_$(XILINX_FLAVOR)) @@ -90,8 +93,8 @@ $(CHS_XIL_DIR)/out/%.bit: $(xilinx_bit_$(XILINX_FLAVOR)) cp $(patsubst %.bit,%.ltx,$< $@); \ fi -# Build a bitstream -chs-xil-all: chs-xil-clean-ips $(xilinx_bit) +# Build bitstream +chs-xil-all: $(xilinx_bit) # Program last bitstream chs-xil-program: @@ -99,15 +102,9 @@ chs-xil-program: $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source $(CHS_XIL_DIR)/scripts/program.tcl # Flash linux image -chs-xil-flash: $(CAR_SW_DIR)/boot/linux_carfield_$(XILINX_FLAVOR)_$(XILINX_BOARD).gpt.bin +chs-xil-flash: $(CHS_SW_DIR)/boot/linux_cheshire_$(XILINX_FLAVOR)_$(XILINX_BOARD).gpt.bin $(vivado_env) FILE=$< OFFSET=0 $(VIVADO) $(VIVADO_FLAGS) -source $(CHS_XIL_DIR)/scripts/flash_spi.tcl -# Clean a given IP folder -%-xlnx-ip-clean: % - make -C $< clean -# Clean all IP folder using rule above -chs-xil-clean-ips: $(addsuffix -xlnx-ip-clean,$(shell find $(xilinx_ip_dir)/ -maxdepth 1 -mindepth 1 -type d)) - -chs-xil-clean: chs-xil-clean-ips chs-xil-clean-vanilla chs-xil-clean-bd +chs-xil-clean: chs-xil-clean-vanilla xilinx-ip-clean-all -.PHONY: chs-xil-program chs-xil-flash chs-xil-clean chs-xil-all chs-xil-clean-ips +.PHONY: chs-xil-program chs-xil-flash chs-xil-clean chs-xil-all diff --git a/target/xilinx/xilinx_ips/.gitignore b/target/xilinx/xilinx_ips/.gitignore deleted file mode 100644 index 12ef7f9f2..000000000 --- a/target/xilinx/xilinx_ips/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -xlnx*/* -!xlnx*/tcl -!Makefile -!common.mk -!*.prj \ No newline at end of file diff --git a/target/xilinx/xilinx_ips/common.mk b/target/xilinx/xilinx_ips/common.mk deleted file mode 100644 index c1e8c4bdd..000000000 --- a/target/xilinx/xilinx_ips/common.mk +++ /dev/null @@ -1,65 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Cyril Koenig - -all: load-artifacts $(PROJECT).xpr save-artifacts - -# Build IP -xlnx_%.xpr: - $(vivado_env) $(VIVADO) -mode batch -source tcl/run.tcl - -save-artifacts: - -load-artifacts: - -clean: - @rm -rf ip/* - @mkdir -p ip - @rm -rf ${PROJECT}.* - @rm -rf component.xml - @rm -rf vivado*.jou - @rm -rf vivado*.log - @rm -rf vivado*.str - @rm -rf xgui - @rm -rf .Xil - @rm -rf tmp - @rm -rf .generated* - -.PHONY: clean save-artifacts load-artifacts - -# -# Artifacts management (IIS internal) -# - -ifeq ($(XILINX_USE_ARTIFACTS),1) - -# Note: We do not use Memora as it is bound to Git versionning -# and not standalone on files hash / environment variables -ARTIFACTS_PATH=/usr/scratch2/wuerzburg/cykoenig/memora/cheshire -TERM_GREEN='\033[0;32m' -TERM_NC='\033[0m' - -# Generate a sha based on env variables and artifacts_in -.generated_sha256: - @echo $(VIVADO) $(PROJECT) > .generated_env - @echo $(vivado_env) | tr " " "\n" | grep $(foreach var,$(ARTIFACTS_VARS), $(addprefix -e ,$(var))) >> .generated_env - @sha256sum $(ARTIFACTS_IN) >> .generated_env - @sha256sum .generated_env | awk '{print $$1}' > .generated_sha256 - -# Load artifacts based on .generated_sha256 -load-artifacts: .generated_sha256 - @if [ -d "$(ARTIFACTS_PATH)/`cat $<`" ]; then\ - echo -e $(TERM_GREEN)"Fetching $(PROJECT) from $(ARTIFACTS_PATH)/`cat $<`"$(TERM_NC); \ - cp -r $(ARTIFACTS_PATH)/`cat $<`/* .; \ - fi - -# Save artifacts (this folder) based on .generated_sha256 -save-artifacts: .generated_sha256 $(PROJECT).xpr - @if [ ! -d "$(ARTIFACTS_PATH)/`cat .generated_sha256`" ]; then \ - cp -r . $(ARTIFACTS_PATH)/`cat .generated_sha256`; \ - chmod -R g+rw $(ARTIFACTS_PATH)/`cat .generated_sha256`; \ - fi - -endif # ifeq ($(USE_ARTIFACTS),1) diff --git a/target/xilinx/xilinx_ips/xilinx_ips.mk b/target/xilinx/xilinx_ips/xilinx_ips.mk new file mode 100644 index 000000000..9122823d1 --- /dev/null +++ b/target/xilinx/xilinx_ips/xilinx_ips.mk @@ -0,0 +1,80 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Cyril Koenig + +# List available IPs +chs_xil_available_ips = xlnx_clk_wiz xlnx_mig_7_ddr3 xlnx_mig_ddr4 xlnx_vio + +# Include $ip.mk create a building rule to export the $ip.xci file. Also enable artifacts management +# See xlnx_vio.mk for an example of IP related variables +define chs_xlnx_ips_vars_and_deps = +include $(CHS_XIL_DIR)/xilinx_ips/$(1)/$(1).mk +ARTIFACTS_PATHS_$(1) := $$(addprefix $$(ROOT_$(1))/, $$(ARTIFACTS_FILES_$(1))) +ARTIFACTS_VALS_$(1) := $$(foreach var, $$(ARTIFACTS_VARS_$(1)), $$(var)=$$($$(var))) + +ifeq ($(XILINX_USE_ARTIFACTS)$$(XILINX_USE_ARTIFACTS_$(1)),11) +$(CHS_XIL_DIR)/xilinx_ips/$(1)/%.xci: xilinx-ip-load-artifacts-$(1) $$(IP_DEP_$(1)) $(CHS_XIL_DIR)/xilinx_ips/$(1)/$(1).xpr xilinx-ip-save-artifacts-$(1) +else +$(CHS_XIL_DIR)/xilinx_ips/$(1)/%.xci: $$(IP_DEP_$(1)) $(CHS_XIL_DIR)/xilinx_ips/$(1)/$(1).xpr +endif + @echo "IP $(1) : Done" + +$(CHS_XIL_DIR)/xilinx_ips/$(1)/$(1).xpr: + cd $$(ROOT_$(1)) && $(vivado_env) $(VIVADO) -mode batch -source tcl/run.tcl +.PRECIOUS: $(CHS_XIL_DIR)/xilinx_ips/$(1)/%.xci +endef + +# Call chs_xlnx_ips_vars_and_deps +$(foreach ip, $(chs_xil_available_ips), $(eval $(call chs_xlnx_ips_vars_and_deps,$(ip)))) + +# Define inputs used to differentiate pre-compiled IPs artifacts +$(CHS_XIL_DIR)/xilinx_ips/%/.generated_env: + echo $(VIVADO) $(XILINX_PROJECT) > $@ + echo $(ARTIFACTS_VALS_$*) >> $@ + echo $(ARTIFACTS_FILES_$*) >> $@ + sha256sum $(ARTIFACTS_PATHS_$*) | awk '{print $$1}' >> $@ + +# Define artifact hash +$(CHS_XIL_DIR)/xilinx_ips/%/.generated_sha256: $(CHS_XIL_DIR)/xilinx_ips/%/.generated_env + sha256sum $< | awk '{print $$1}' > $@ + +# Phonies can not use wildcards +define chs_xlnx_ips_phonies = +# Load artifact based on hash +xilinx-ip-load-artifacts-$(1): $(CHS_XIL_DIR)/xilinx_ips/$(1)/.generated_sha256 + @if [ -z "$(XILINX_ARTIFACTS_ROOT)" ]; then \ + echo "Error: XILINX_ARTIFACTS_ROOT missing"; \ + exit 1; \ + fi + @if [ -d "$(XILINX_ARTIFACTS_ROOT)/`cat $$<`" ]; then \ + echo -e $(TERM_GREEN)"Fetching $(1) from $(XILINX_ARTIFACTS_ROOT)/`cat $$<`"$(TERM_NC); \ + cp -r $(XILINX_ARTIFACTS_ROOT)/`cat $$<`/* $(ROOT_$(1)); \ + else \ + echo -e "$(1) not found in $(XILINX_ARTIFACTS_ROOT)/`cat $$<`"; \ + fi + +# Save artifact based on hash +xilinx-ip-save-artifacts-$(1): $(CHS_XIL_DIR)/xilinx_ips/$(1)/.generated_sha256 $(CHS_XIL_DIR)/xilinx_ips/$(1)/$(1).xpr + @if [ ! -d "$(XILINX_ARTIFACTS_ROOT)/`cat $$<`" ]; then \ + cp -r $(ROOT_$(1)) $(XILINX_ARTIFACTS_ROOT)/`cat $$<`; \ + chmod -R g+rw $(XILINX_ARTIFACTS_ROOT)/`cat $$<`; \ + fi + +# Delete all the project.* generated folders +xilinx-ip-clean-$(1): + @if [ -z "$$(ROOT_$(1))" ]; then echo "Error: Cannot find ROOT_$(1)" exit 1; fi; + find $$(ROOT_$(1)) -mindepth 1 -type d -name "$(1).*" -exec rm -r {} + + cd $$(ROOT_$(1)) && rm -rf $(1) .generated_env .generated_sha256 vivado* .Xil *.xpr tcl/add_sources* xgui component.xml +.PHONY: xilinx-ip-load-artifacts-$(1) xilinx-ip-save-artifacts-$(1) xilinx-ip-clean-$(1) +endef + +# Call chs_xlnx_ips_phonies +$(foreach ip, $(chs_xil_available_ips), $(eval $(call chs_xlnx_ips_phonies,$(ip)))) + +xilinx-ip-clean-all: $(addprefix xilinx-ip-clean-,$(chs_xil_available_ips)) + @echo "Xilinx IPs cleaned ($(chs_xil_available_ips))" + +# Note: We do not PHONY the three rules above for lisibility since +# PHONY rules cannot use wildcards... but these files won't exist anyways diff --git a/target/xilinx/xilinx_ips/xlnx_clk_wiz/Makefile b/target/xilinx/xilinx_ips/xlnx_clk_wiz/Makefile deleted file mode 100644 index 02481e515..000000000 --- a/target/xilinx/xilinx_ips/xlnx_clk_wiz/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -PROJECT:=xlnx_clk_wiz -# The files and variables on which the IP configuration depends -ARTIFACTS_IN:=Makefile tcl/run.tcl -ARTIFACTS_VARS:=XILINX_PART XILINX_BOARD_LONG XILINX_BOARD - -include ../common.mk diff --git a/target/xilinx/xilinx_ips/xlnx_clk_wiz/xlnx_clk_wiz.mk b/target/xilinx/xilinx_ips/xlnx_clk_wiz/xlnx_clk_wiz.mk new file mode 100644 index 000000000..0f3af4626 --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_clk_wiz/xlnx_clk_wiz.mk @@ -0,0 +1,8 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +ROOT_xlnx_clk_wiz := $(CHS_XIL_DIR)/xilinx_ips/xlnx_clk_wiz +ARTIFACTS_FILES_xlnx_clk_wiz := xlnx_clk_wiz.mk tcl/run.tcl +ARTIFACTS_VARS_xlnx_clk_wiz := xilinx_part XILINX_BOARD xilinx_board_long +XILINX_USE_ARTIFACTS_xlnx_clk_wiz := 1 diff --git a/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/Makefile b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/Makefile deleted file mode 100644 index c076431d8..000000000 --- a/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -PROJECT:=xlnx_mig_7_ddr3 -ARTIFACTS_IN:=Makefile tcl/run.tcl mig_genesys2.prj mig_kc705.prj mig_vc707.prj -ARTIFACTS_VARS:=XILINX_PART XILINX_BOARD_LONG XILINX_BOARD - -include ../common.mk diff --git a/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.mk b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.mk new file mode 100644 index 000000000..02ec18402 --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.mk @@ -0,0 +1,8 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +ROOT_xlnx_mig_7_ddr3 := $(CHS_XIL_DIR)/xilinx_ips/xlnx_mig_7_ddr3 +ARTIFACTS_FILES_xlnx_mig_7_ddr3 := xlnx_mig_7_ddr3.mk tcl/run.tcl +ARTIFACTS_VARS_xlnx_mig_7_ddr3 := xilinx_part XILINX_BOARD xilinx_board_long +XILINX_USE_ARTIFACTS_xlnx_mig_7_ddr3 := 1 diff --git a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile deleted file mode 100644 index b8349e984..000000000 --- a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -PROJECT:=xlnx_mig_ddr4 -# The files and variables on which the IP configuration depends -ARTIFACTS_IN:=Makefile tcl/run.tcl -ARTIFACTS_VARS:=XILINX_PART XILINX_BOARD_LONG XILINX_BOARD - -include ../common.mk diff --git a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl index 34fd776a8..5e1993215 100644 --- a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl +++ b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/tcl/run.tcl @@ -28,30 +28,12 @@ if {$::env(XILINX_BOARD) eq "vcu128"} { CONFIG.C0.DDR4_Ecc {true} \ CONFIG.C0.DDR4_AxiDataWidth {512} \ CONFIG.C0.DDR4_AxiAddressWidth {32} \ - CONFIG.C0.DDR4_AxiIDWidth {4} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ CONFIG.C0.BANK_GROUP_WIDTH {1} \ CONFIG.C0.CS_WIDTH {2} \ CONFIG.C0.DDR4_AxiSelection {true} \ ] [get_ips $ipName] - -} elseif {$::env(XILINX_BOARD) eq "zcu102"} { - set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_062} \ - CONFIG.C0.DDR4_TimePeriod {833} \ - CONFIG.C0.DDR4_InputClockPeriod {3332} \ - CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ - CONFIG.C0.DDR4_MemoryPart {MT40A256M16LY-062E} \ - CONFIG.C0.DDR4_DataWidth {16} \ - CONFIG.C0.DDR4_CasWriteLatency {12} \ - CONFIG.C0.DDR4_AxiDataWidth {128} \ - CONFIG.C0.DDR4_AxiAddressWidth {29} \ - CONFIG.C0.DDR4_AxiIDWidth {4} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ - CONFIG.System_Clock {No_Buffer} \ - CONFIG.Reference_Clock {No_Buffer} \ - CONFIG.C0.BANK_GROUP_WIDTH {1} \ - CONFIG.C0.DDR4_AxiSelection {true} \ - ] [get_ips $ipName] } diff --git a/target/xilinx/xilinx_ips/xlnx_mig_ddr4/xlnx_mig_ddr4.mk b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/xlnx_mig_ddr4.mk new file mode 100644 index 000000000..1975d0150 --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_mig_ddr4/xlnx_mig_ddr4.mk @@ -0,0 +1,8 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +ROOT_xlnx_mig_ddr4 := $(CHS_XIL_DIR)/xilinx_ips/xlnx_mig_ddr4 +ARTIFACTS_FILES_xlnx_mig_ddr4 := xlnx_mig_ddr4.mk tcl/run.tcl +ARTIFACTS_VARS_xlnx_mig_ddr4 := xilinx_part XILINX_BOARD xilinx_board_long +XILINX_USE_ARTIFACTS_xlnx_mig_ddr4 := 1 diff --git a/target/xilinx/xilinx_ips/xlnx_vio/Makefile b/target/xilinx/xilinx_ips/xlnx_vio/Makefile deleted file mode 100644 index 33fb89122..000000000 --- a/target/xilinx/xilinx_ips/xlnx_vio/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -PROJECT:=xlnx_vio -# The files and variables on which the IP configuration depends -ARTIFACTS_IN:=Makefile tcl/run.tcl -ARTIFACTS_VARS:=XILINX_PART XILINX_BOARD_LONG XILINX_BOARD - -include ../common.mk diff --git a/target/xilinx/xilinx_ips/xlnx_vio/xlnx_vio.mk b/target/xilinx/xilinx_ips/xlnx_vio/xlnx_vio.mk new file mode 100644 index 000000000..1adfbb8e8 --- /dev/null +++ b/target/xilinx/xilinx_ips/xlnx_vio/xlnx_vio.mk @@ -0,0 +1,8 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +ROOT_xlnx_vio := $(CHS_XIL_DIR)/xilinx_ips/xlnx_vio +ARTIFACTS_FILES_xlnx_vio := xlnx_vio.mk tcl/run.tcl +ARTIFACTS_VARS_xlnx_vio := xilinx_part XILINX_BOARD xilinx_board_long +XILINX_USE_ARTIFACTS_xlnx_vio := 1