From c8194f09678ce8e8ab0525e6fee209f43d003ca1 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 5 Dec 2023 16:29:43 +0100 Subject: [PATCH] Attempt to fix System Verilog lint. --- hw/cheshire_soc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 48828f6f..5516e989 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -610,7 +610,7 @@ module cheshire_soc import cheshire_pkg::*; #( if (Cfg.HmrUnit == 1) begin : gen_hmr_unit_reg_intf assign reg_out_core_req = reg_out_req[RegOut.hmr_unit]; assign reg_out_rsp[RegOut.hmr_unit] = reg_out_core_rsp; - end else begin + end else begin : gen_no_hmr_unit_reg_intf assign reg_out_core_req = '0; end