From a635f7a95e5e4487907f70811314b1f7045b15be Mon Sep 17 00:00:00 2001 From: Paul Scheffler Date: Tue, 19 Sep 2023 15:31:14 +0200 Subject: [PATCH] hw: Some cleanup --- docs/um/arch.md | 8 ++++---- hw/cheshire_pkg.sv | 8 ++++---- target/xilinx/src/cheshire_top_xilinx.sv | 5 +++++ 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/docs/um/arch.md b/docs/um/arch.md index e02ed0e4..83829bbc 100644 --- a/docs/um/arch.md +++ b/docs/um/arch.md @@ -236,18 +236,18 @@ The [Serial Link](https://github.com/pulp-platform/serial_link) is a fully digit ### DMA engine -The [iDMA engine](https://github.com/pulp-platform/iDMA) enables high-throughput asynchronous transfers between any two subordinate address ranges in the system. The hardware supports, if enabled, up to two dimensional transfers directly in hardware. It exposes the following parameters: +The [iDMA engine](https://github.com/pulp-platform/iDMA) enables high-throughput asynchronous transfers between any two subordinate address ranges in the system. The hardware supports, if enabled, up to two-dimensional transfers directly in hardware. It exposes the following parameters: | Parameter | Type / Range | Description | | ---------------------------- | ------------ | ------------------------------------------------- | | `DmaConfMax(Read|Write)Txns` | `dw_bt` | Max. number of outstanding requests to DMA config | | `DmaConfAmoNumCuts` | `aw_bt` | Number of timing cuts inside config AMO filter | -| `DmaNumAxInFlight` | `dw_bt` | Number of outstanding transfer the DMA launches | +| `DmaConfAmoPostCut` | `bit` | Whether to insert a cut after config AMO filter | +| `DmaConfEnableTwoD` | `bit` | Whether the 2D hardware extension is present | +| `DmaNumAxInFlight` | `dw_bt` | Number of outstanding transfers the DMA launches | | `DmaMemSysDepth` | `dw_bt` | The *approximate* depth of the memory system | | `DmaJobFifoDepth` | `aw_bt` | The depth of the job FIFO | | `DmaRAWCouplingAvail` | `bit` | Whether the R-AW coupling feature is available | -| `DmaConfAmoPostCut` | `bit` | Whether to insert a cut after config AMO filter | -| `DmaConfEnableTwoD` | `bit` | Whether the 2D hardware extension is present | ### I2C, SPI, GPIOs diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 530cecda..028fdb2e 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -171,12 +171,12 @@ package cheshire_pkg; dw_bt DmaConfMaxReadTxns; dw_bt DmaConfMaxWriteTxns; aw_bt DmaConfAmoNumCuts; + bit DmaConfAmoPostCut; + bit DmaConfEnableTwoD; dw_bt DmaNumAxInFlight; dw_bt DmaMemSysDepth; aw_bt DmaJobFifoDepth; bit DmaRAWCouplingAvail; - bit DmaConfAmoPostCut; - bit DmaConfEnableTwoD; // Parameters for GPIO bit GpioInputSyncs; // Parameters for AXI RT @@ -581,12 +581,12 @@ package cheshire_pkg; DmaConfMaxReadTxns : 4, DmaConfMaxWriteTxns : 4, DmaConfAmoNumCuts : 1, + DmaConfAmoPostCut : 1, + DmaConfEnableTwoD : 1, DmaNumAxInFlight : 16, DmaMemSysDepth : 8, DmaJobFifoDepth : 2, DmaRAWCouplingAvail : 1, - DmaConfAmoPostCut : 1, - DmaConfEnableTwoD : 1, // GPIOs GpioInputSyncs : 1, // AXI RT diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index f9763f54..188e0ce3 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -143,6 +143,11 @@ module cheshire_top_xilinx DmaConfMaxWriteTxns : 4, DmaConfAmoNumCuts : 1, DmaConfAmoPostCut : 1, + DmaConfEnableTwoD : 1, + DmaNumAxInFlight : 16, + DmaMemSysDepth : 8, + DmaJobFifoDepth : 2, + DmaRAWCouplingAvail : 1, // GPIOs GpioInputSyncs : 1, // All non-set values should be zero