From a0f929a1bba9d7d1407364a22728d2e348ce28e3 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Thu, 28 Sep 2023 18:54:52 +0200 Subject: [PATCH] treewide: Add clic virtualization support --- Bender.lock | 6 +++--- Bender.yml | 4 ++-- hw/cheshire_pkg.sv | 10 ++++++++++ hw/cheshire_soc.sv | 13 +++++++++++-- 4 files changed, 26 insertions(+), 7 deletions(-) diff --git a/Bender.lock b/Bender.lock index 3166ff8d3..e79313b46 100644 --- a/Bender.lock +++ b/Bender.lock @@ -62,8 +62,8 @@ packages: - common_cells - register_interface clic: - revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf - version: 2.0.0 + revision: 94e2a77143053f1a2a72c88989616c89e05854fc + version: null source: Git: https://github.com/pulp-platform/clic.git dependencies: @@ -92,7 +92,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: - revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5 + revision: 49942049e40f5e57455d7aff1e0a89cad4aedd8a version: null source: Git: https://github.com/pulp-platform/cva6.git diff --git a/Bender.yml b/Bender.yml index c460f28ff..802316ae7 100644 --- a/Bender.yml +++ b/Bender.yml @@ -18,11 +18,11 @@ dependencies: axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 } axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.4 } axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 } - clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 } + clic: { git: "https://github.com/pulp-platform/clic.git", rev: "94e2a77" } # branch: aottaviano/dev clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 } common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 } - cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 } + cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: "4994204" } # branch: aottaviano/vclic iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 867bf9810..9993164ca 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -85,6 +85,11 @@ package cheshire_pkg; byte_bt NumExtOutIntrTgts; shrt_bt NumExtOutIntrs; shrt_bt ClicIntCtlBits; + bit ClicUseSMode; + bit ClicUseUMode; + bit ClicUseVsMode; + bit ClicUseVsModePrio; + byte_bt ClicNumVsCtxts; shrt_bt NumExtIntrSyncs; // AXI parameters aw_bt AddrWidth; @@ -562,6 +567,11 @@ package cheshire_pkg; NumExtOutIntrTgts : 0, NumExtOutIntrs : 0, ClicIntCtlBits : 8, + ClicUseSMode : 0, + ClicUseUMode : 0, + ClicUseVsMode : 0, + ClicUseVsModePrio : 0, + ClicNumVsCtxts : 0, NumExtIntrSyncs : 2, // Interconnect AddrWidth : 48, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index f6ba75ee1..16022fc66 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -585,8 +585,10 @@ module cheshire_soc import cheshire_pkg::*; #( logic clic_irq_valid, clic_irq_ready; logic clic_irq_kill_req, clic_irq_kill_ack; logic clic_irq_shv; + logic clic_irq_v; logic [$clog2(NumClicIntrs)-1:0] clic_irq_id; logic [7:0] clic_irq_level; + logic [5:0] clic_irq_vsid; riscv::priv_lvl_t clic_irq_priv; cva6 #( @@ -612,6 +614,8 @@ module cheshire_soc import cheshire_pkg::*; #( .clic_irq_level_i ( clic_irq_level ), .clic_irq_priv_i ( clic_irq_priv ), .clic_irq_shv_i ( clic_irq_shv ), + .clic_irq_v_i ( clic_irq_v ), + .clic_irq_vsid_i ( clic_irq_vsid ), .clic_irq_ready_o ( clic_irq_ready ), .clic_kill_req_i ( clic_irq_kill_req ), .clic_kill_ack_o ( clic_irq_kill_ack ), @@ -669,8 +673,11 @@ module cheshire_soc import cheshire_pkg::*; #( .INTCTLBITS ( Cfg.ClicIntCtlBits ), .reg_req_t ( reg_req_t ), .reg_rsp_t ( reg_rsp_t ), - .SSCLIC ( 1 ), - .USCLIC ( 0 ) + .SSCLIC ( Cfg.ClicUseSMode ), + .USCLIC ( Cfg.ClicUseUMode ), + .VSCLIC ( Cfg.ClicUseVsMode ), + .VSPRIO ( Cfg.ClicUseVsModePrio ), + .N_VSCTXTS ( Cfg.ClicNumVsCtxts ) ) i_clic ( .clk_i, .rst_ni, @@ -683,6 +690,8 @@ module cheshire_soc import cheshire_pkg::*; #( .irq_level_o ( clic_irq_level ), .irq_shv_o ( clic_irq_shv ), .irq_priv_o ( clic_irq_priv ), + .irq_v_o ( clic_irq_v ), + .irq_vsid_o ( clic_irq_vsid ), .irq_kill_req_o ( clic_irq_kill_req ), .irq_kill_ack_i ( clic_irq_kill_ack ) );