From 9df58116e8863742af23b2bbf4da577fde1fcb3d Mon Sep 17 00:00:00 2001
From: Zexin Fu <zexifu@iis.ee.ethz.ch>
Date: Wed, 4 Dec 2024 19:32:17 +0100
Subject: [PATCH] xilinx: Use reset signal corresponding to input polarity in
 `sys_rst`

---
 target/xilinx/src/cheshire_top_xilinx.sv | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
index b0494052..579dbc13 100644
--- a/target/xilinx/src/cheshire_top_xilinx.sv
+++ b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -173,7 +173,11 @@ module cheshire_top_xilinx import cheshire_pkg::*; (
   assign vio_boot_mode_sel  = '0;
 `endif
 
+`ifdef USE_RESET
+  assign sys_rst = sys_reset | vio_reset;
+`elsif USE_RESETN
   assign sys_rst = ~sys_resetn | vio_reset;
+`endif
   assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i;
 
   //////////////////