diff --git a/Bender.lock b/Bender.lock index cdc4ee08..039721fc 100644 --- a/Bender.lock +++ b/Bender.lock @@ -131,7 +131,7 @@ packages: dependencies: - common_cells idma: - revision: 864e6af3155c99ea616121645546df40d872b718 + revision: f6ae9bef433cfce19a25e340518b8da5bd9bcbef version: null source: Git: https://github.com/pulp-platform/iDMA.git diff --git a/hw/cheshire_idma_wrap.sv b/hw/cheshire_idma_wrap.sv index ee5bd6fe..a3ce7457 100644 --- a/hw/cheshire_idma_wrap.sv +++ b/hw/cheshire_idma_wrap.sv @@ -22,8 +22,8 @@ module cheshire_idma_wrap #( parameter bit IsTwoD = 0, parameter type axi_mst_req_t = logic, parameter type axi_mst_rsp_t = logic, - parameter type axi_slv_req_t = logic, - parameter type axi_slv_rsp_t = logic + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -32,8 +32,8 @@ module cheshire_idma_wrap #( input axi_mst_rsp_t axi_mst_rsp_i, output axi_mst_req_t axi_ptw_req_o, input axi_mst_rsp_t axi_ptw_rsp_i, - input axi_slv_req_t axi_slv_req_i, - output axi_slv_rsp_t axi_slv_rsp_o + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o ); `include "axi/assign.svh" @@ -68,8 +68,6 @@ module cheshire_idma_wrap #( `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, tf_len_t, tf_len_t) - `REG_BUS_TYPEDEF_ALL(dma_regs, addr_t, data_t, strb_t) - typedef struct packed { axi_ar_chan_t ar_chan; } axi_read_meta_channel_t; @@ -86,9 +84,6 @@ module cheshire_idma_wrap #( axi_write_meta_channel_t axi; } write_meta_channel_t; - dma_regs_req_t dma_reg_req; - dma_regs_rsp_t dma_reg_rsp; - // 1D FE signals idma_req_t burst_req_d; logic burst_req_valid_d; @@ -134,39 +129,20 @@ module cheshire_idma_wrap #( logic smmu_f_update_tlb; logic [63:0] smmu_pt_root_adr; - axi_to_reg #( - .ADDR_WIDTH ( AxiAddrWidth ), - .DATA_WIDTH ( AxiDataWidth ), - .ID_WIDTH ( AxiSlvIdWidth ), - .USER_WIDTH ( AxiUserWidth ), - .axi_req_t ( axi_slv_req_t ), - .axi_rsp_t ( axi_slv_rsp_t ), - .reg_req_t ( dma_regs_req_t ), - .reg_rsp_t ( dma_regs_rsp_t ) - ) i_axi_translate ( - .clk_i, - .rst_ni, - .testmode_i, - .axi_req_i ( axi_slv_req_i ), - .axi_rsp_o ( axi_slv_rsp_o ), - .reg_req_o ( dma_reg_req ), - .reg_rsp_i ( dma_reg_rsp ) - ); - if (!IsTwoD) begin : gen_1d idma_reg64_1d #( - .NumRegs ( 32'd1 ), - .NumStreams ( 32'd1 ), - .IdCounterWidth ( IdCounterWidth ), - .reg_req_t ( dma_regs_req_t ), - .reg_rsp_t ( dma_regs_rsp_t ), - .dma_req_t ( idma_req_t ) + .NumRegs ( 32'd1 ), + .NumStreams ( 32'd1 ), + .IdCounterWidth ( IdCounterWidth ), + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ), + .dma_req_t ( idma_req_t ) ) i_dma_frontend_1d ( .clk_i, .rst_ni, - .dma_ctrl_req_i ( dma_reg_req ), - .dma_ctrl_rsp_o ( dma_reg_rsp ), + .dma_ctrl_req_i ( reg_req_i ), + .dma_ctrl_rsp_o ( reg_rsp_o ), .dma_req_o ( burst_req_d ), .req_valid_o ( burst_req_valid_d ), .req_ready_i ( burst_req_ready_d ), @@ -178,7 +154,7 @@ module cheshire_idma_wrap #( .smmu_f_update_tlb ( smmu_f_update_tlb ), .smmu_pt_root_adr ( smmu_pt_root_adr ), .done_id_i ( done_id ), - .busy_i ( idma_busy ), + .busy_i ( busy ), .midend_busy_i ( 1'b0 ) ); @@ -220,14 +196,14 @@ module cheshire_idma_wrap #( .NumRegs ( 1 ), .NumStreams ( 1 ), .IdCounterWidth ( IdCounterWidth ), - .reg_req_t ( dma_regs_req_t ), - .reg_rsp_t ( dma_regs_rsp_t ), + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ), .dma_req_t ( idma_nd_req_t ) ) idma_frontend_2d ( .clk_i, .rst_ni, - .dma_ctrl_req_i ( dma_reg_req ), - .dma_ctrl_rsp_o ( dma_reg_rsp ), + .dma_ctrl_req_i ( reg_req_i ), + .dma_ctrl_rsp_o ( reg_rsp_o ), .dma_req_o ( idma_nd_req_d ), .req_valid_o ( idma_nd_req_valid_d ), .req_ready_i ( idma_nd_req_ready_d ), diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 0d699564..b6c9f8ed 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -333,7 +333,6 @@ package cheshire_pkg; aw_bt reg_demux; aw_bt llc; aw_bt spm; - aw_bt dma; aw_bt slink; aw_bt ext_base; aw_bt num_out; @@ -359,7 +358,6 @@ package cheshire_pkg; r++; ret.map[r] = '{i, AmSpm, AmSpm + SizeSpm}; r++; ret.map[r] = '{i, AmSpm + 'h0400_0000, AmSpm + 'h0400_0000 + SizeSpm}; end - if (cfg.Dma) begin i++; r++; ret.dma = i; ret.map[r] = '{i, 'h0100_0000, 'h0100_1000}; end if (cfg.SerialLink) begin i++; r++; ret.slink = i; ret.map[r] = '{i, cfg.SlinkRegionStart, cfg.SlinkRegionEnd}; end // External port indices start after internal ones @@ -396,6 +394,7 @@ package cheshire_pkg; aw_bt slink; aw_bt vga; aw_bt usb; + aw_bt dma; aw_bt axirt; aw_bt irq_router; aw_bt [2**MaxCoresWidth-1:0] bus_err; @@ -421,6 +420,7 @@ package cheshire_pkg; if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end if (cfg.Usb) begin i++; ret.usb = i; r++; ret.map[r] = '{i, 'h0300_8000, 'h0300_9000}; end + if (cfg.Dma) begin i++; ret.dma = i; r++; ret.map[r] = '{i, 'h0300_b000, 'h0300_c000}; end if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin @@ -659,7 +659,7 @@ package cheshire_pkg; DmaConfMaxWriteTxns : 4, DmaConfAmoNumCuts : 1, DmaConfAmoPostCut : 1, - DmaConfEnableTwoD : 1, + DmaConfEnableTwoD : 0, DmaNumAxInFlight : 16, DmaMemSysDepth : 8, DmaJobFifoDepth : 2, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 989aa95c..02338193 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1369,50 +1369,6 @@ module cheshire_soc import cheshire_pkg::*; #( if (Cfg.Dma) begin : gen_dma - axi_slv_req_t dma_amo_req, dma_cut_req; - axi_slv_rsp_t dma_amo_rsp, dma_cut_rsp; - - axi_riscv_atomics_structs #( - .AxiAddrWidth ( Cfg.AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataWidth ), - .AxiIdWidth ( AxiSlvIdWidth ), - .AxiUserWidth ( Cfg.AxiUserWidth ), - .AxiMaxReadTxns ( Cfg.DmaConfMaxReadTxns ), - .AxiMaxWriteTxns ( Cfg.DmaConfMaxWriteTxns ), - .AxiUserAsId ( 1 ), - .AxiUserIdMsb ( Cfg.AxiUserAmoMsb ), - .AxiUserIdLsb ( Cfg.AxiUserAmoLsb ), - .RiscvWordWidth ( 64 ), - .NAxiCuts ( Cfg.DmaConfAmoNumCuts ), - .axi_req_t ( axi_slv_req_t ), - .axi_rsp_t ( axi_slv_rsp_t ) - ) i_dma_conf_atomics ( - .clk_i, - .rst_ni, - .axi_slv_req_i ( axi_out_req[AxiOut.dma] ), - .axi_slv_rsp_o ( axi_out_rsp[AxiOut.dma] ), - .axi_mst_req_o ( dma_amo_req ), - .axi_mst_rsp_i ( dma_amo_rsp ) - ); - - axi_cut #( - .Bypass ( ~Cfg.DmaConfAmoPostCut ), - .aw_chan_t ( axi_slv_aw_chan_t ), - .w_chan_t ( axi_slv_w_chan_t ), - .b_chan_t ( axi_slv_b_chan_t ), - .ar_chan_t ( axi_slv_ar_chan_t ), - .r_chan_t ( axi_slv_r_chan_t ), - .axi_req_t ( axi_slv_req_t ), - .axi_resp_t ( axi_slv_rsp_t ) - ) i_dma_conf_atomics_cut ( - .clk_i, - .rst_ni, - .slv_req_i ( dma_amo_req ), - .slv_resp_o ( dma_amo_rsp ), - .mst_req_o ( dma_cut_req ), - .mst_resp_i ( dma_cut_rsp ) - ); - axi_mst_req_t axi_dma_req; axi_mst_req_t axi_ptw_req; @@ -1443,18 +1399,16 @@ module cheshire_soc import cheshire_pkg::*; #( .IsTwoD ( Cfg.DmaConfEnableTwoD ), .axi_mst_req_t ( axi_mst_req_t ), .axi_mst_rsp_t ( axi_mst_rsp_t ), - .axi_slv_req_t ( axi_slv_req_t ), - .axi_slv_rsp_t ( axi_slv_rsp_t ) + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ) ) i_idma ( .clk_i, .rst_ni, .testmode_i ( test_mode_i ), .axi_mst_req_o ( axi_dma_req ), .axi_mst_rsp_i ( axi_in_rsp[AxiIn.dma] ), - .axi_ptw_req_o ( axi_ptw_req ), - .axi_ptw_rsp_i ( axi_in_rsp[AxiIn.dma_ptw] ), - .axi_slv_req_i ( dma_cut_req ), - .axi_slv_rsp_o ( dma_cut_rsp ) + .reg_req_i ( reg_out_req[RegOut.dma] ), + .reg_rsp_o ( reg_out_rsp[RegOut.dma] ) ); if (Cfg.BusErr) begin : gen_dma_bus_err diff --git a/sw/link/common.ldh b/sw/link/common.ldh index d55a5249..4e4b78b4 100644 --- a/sw/link/common.ldh +++ b/sw/link/common.ldh @@ -30,7 +30,7 @@ SECTIONS { __stack_pointer$ = 0; /* Further addresses */ - __base_dma = 0x01000000; + __base_dma = 0x0300b000; __base_bootrom = 0x02000000; __base_clint = 0x02040000; __base_axirt = 0x020C0000; diff --git a/sw/tests/smmu_test.c b/sw/tests/smmu_test.c index fbd75f4e..78be2654 100644 --- a/sw/tests/smmu_test.c +++ b/sw/tests/smmu_test.c @@ -47,7 +47,8 @@ int main(void) { sys_dma_smmu_set_pt_root(0x123456789ABCDEF0); // Start den Memory Transfer - sys_dma_memcpy((uintptr_t)(void *)dst, (uintptr_t)(void *)src, sizeof(src_cached)); + // sys_dma_memcpy((uintptr_t)(void *)dst, (uintptr_t)(void *)src, sizeof(src_cached)); + sys_dma_blk_memcpy((uintptr_t)(void *)dst, (uintptr_t)(void *)src, sizeof(src_cached)); // Write Destination Adress uart_write_str(&__base_uart, dst, sizeof(dst_cached));