From 9acd1d64d3b7dd772e5edbb8821229375f2e9c27 Mon Sep 17 00:00:00 2001 From: Raphael Roth Date: Thu, 5 Dec 2024 11:19:05 +0100 Subject: [PATCH] WIP Added Benchmark folder for benchmarks --- sw/benchmark/smmu_linear_1MB.c | 82 ++++++++++++++++++++++++++++++++++ sw/sw.mk | 15 ++++++- 2 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 sw/benchmark/smmu_linear_1MB.c diff --git a/sw/benchmark/smmu_linear_1MB.c b/sw/benchmark/smmu_linear_1MB.c new file mode 100644 index 000000000..d7ec14512 --- /dev/null +++ b/sw/benchmark/smmu_linear_1MB.c @@ -0,0 +1,82 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Raphael Roth +// +// Simple payload to test bootmodes + +#include +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "dif/uart.h" +#include "dif/dma.h" +#include "params.h" +#include "util.h" + +#include "sup_virt_adr.h" + +// This test copies 1MB a linear data +// To work properly the dma needs to be configured as 1D! + +// Define the Root Acess of the Page Table +#define PAGE_TABLE_ROOT_ADRESSE 0x0000000080000000 + +// Main Function +int main(void) { + + // Setup the USART Frequency + uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET); + uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500); + uart_init(&__base_uart, reset_freq, __BOOT_BAUDRATE); + + // All Vars to control the status of the page table + uint64_t nxt_free_page = (PAGE_TABLE_ROOT_ADRESSE + 0x1000); + zeros_page_table((void *) PAGE_TABLE_ROOT_ADRESSE); + + // Var to benchmark the system + char buf[] = "Cycle Num: 0x0000000000000000\r\n"; + uint64_t start_cycle = 0; + uint64_t end_cycle = 0; + + // Initialize an error + int error; + + // Könnte mit rand generaiert werden --> Attention if Overlapping Space + transfer_t tf; + tf.pa_src = (void *) 0x0000000081000000; + tf.pa_dst = (void *) 0x0000000082000000; + tf.va_src = tf.pa_src + 0x200000000; + tf.va_dst = tf.pa_dst + 0x200000000; + tf.len = 1048576; + + // Generate the Page Table for these adresses + reserve_array(tf.va_src, &nxt_free_page, tf.len, PAGE_TABLE_ROOT_ADRESSE); + reserve_array(tf.va_dst, &nxt_free_page, tf.len, PAGE_TABLE_ROOT_ADRESSE); + + // (Optional: Populate with data) + generate_data(tf.pa_src, 0, tf.len); + generate_data(tf.pa_dst, 1, tf.len); + + // Setup the sMMU Config + sys_dma_smmu_config(0,0,0,0); + sys_dma_smmu_set_pt_root(PAGE_TABLE_ROOT_ADRESSE); + + // to flush the cache to DRAM + fence(); + + // DMA Copy here + start_cycle = get_mcycle(); + sys_dma_blk_memcpy((uintptr_t)(void *) tf.va_dst, (uintptr_t)(void *) tf.va_src, tf.len); + end_cycle = get_mcycle(); + + // Verify Data Copy + error = verify_data(tf.pa_src, tf.pa_dst, tf.len); + + // Write the cycle count + convert_hex_to_string((end_cycle - start_cycle), &buf[13], 16); + uart_write_str(&__base_uart, buf, sizeof(buf)); + uart_write_flush(&__base_uart); + + return error; +} \ No newline at end of file diff --git a/sw/sw.mk b/sw/sw.mk index da5184427..126c7d8b4 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -28,7 +28,7 @@ CHS_SW_CCFLAGS ?= $(CHS_SW_FLAGS) -ggdb -mcmodel=medany -mexplicit-relocs -fno-b CHS_SW_LDFLAGS ?= $(CHS_SW_FLAGS) -nostartfiles -Wl,--gc-sections -Wl,-L$(CHS_SW_LD_DIR) CHS_SW_ARFLAGS ?= --plugin=$(CHS_SW_LTOPLUG) -CHS_SW_ALL += $(CHS_SW_LIBS) $(CHS_SW_GEN_HDRS) $(CHS_SW_TESTS) +CHS_SW_ALL += $(CHS_SW_LIBS) $(CHS_SW_GEN_HDRS) $(CHS_SW_TESTS) $(CHS_SW_BENCHMARK) .PRECIOUS: %.elf %.dtb @@ -166,3 +166,16 @@ CHS_SW_TEST_SPM_ROMH = $(CHS_SW_TEST_SRCS_S:.S=.rom.memh) $(CHS_SW_TEST_SRCS CHS_SW_TEST_SPM_GPTH = $(CHS_SW_TEST_SRCS_S:.S=.gpt.memh) $(CHS_SW_TEST_SRCS_C:.c=.gpt.memh) CHS_SW_TESTS = $(CHS_SW_TEST_DRAM_DUMP) $(CHS_SW_TEST_SPM_DUMP) $(CHS_SW_TEST_SPM_ROMH) $(CHS_SW_TEST_SPM_GPTH) + +############## +# Benchmarks # +############## + +CHS_SW_BENCHMARK_SRCS_S = $(wildcard $(CHS_SW_DIR)/benchmark/*.S) +CHS_SW_BENCHMARK_SRCS_C = $(wildcard $(CHS_SW_DIR)/benchmark/*.c) +CHS_SW_BENCHMARK_DRAM_DUMP = $(CHS_SW_BENCHMARK_SRCS_S:.S=.dram.dump) $(CHS_SW_BENCHMARK_SRCS_C:.c=.dram.dump) +CHS_SW_BENCHMARK_SPM_DUMP = $(CHS_SW_BENCHMARK_SRCS_S:.S=.spm.dump) $(CHS_SW_BENCHMARK_SRCS_C:.c=.spm.dump) +CHS_SW_BENCHMARK_SPM_ROMH = $(CHS_SW_BENCHMARK_SRCS_S:.S=.rom.memh) $(CHS_SW_BENCHMARK_SRCS_C:.c=.rom.memh) +CHS_SW_BENCHMARK_SPM_GPTH = $(CHS_SW_BENCHMARK_SRCS_S:.S=.gpt.memh) $(CHS_SW_BENCHMARK_SRCS_C:.c=.gpt.memh) + +CHS_SW_BENCHMARK = $(CHS_SW_BENCHMARK_DRAM_DUMP) $(CHS_SW_BENCHMARK_SPM_DUMP) $(CHS_SW_BENCHMARK_SPM_ROMH) $(CHS_SW_BENCHMARK_SPM_GPTH) \ No newline at end of file