From 99b654154f3c60db08d33d07e0885b44b5d846c1 Mon Sep 17 00:00:00 2001
From: bluew <bluewww@users.noreply.github.com>
Date: Tue, 14 Nov 2023 10:22:27 +0100
Subject: [PATCH] target/xilinx: Fix FPGA wrapper

---
 target/xilinx/src/cheshire_top_xilinx.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
index a05b9912..ae1786f7 100644
--- a/target/xilinx/src/cheshire_top_xilinx.sv
+++ b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -123,12 +123,12 @@ module cheshire_top_xilinx
     LlcOutConnect     : 1,
     LlcOutRegionStart : 'h8000_0000,
     LlcOutRegionEnd   : 'h1_0000_0000,
+    LlcUserMsb        : 0,
+    LlcUserLsb        : 0,
     // LLC partitioning
     LlcCachePartition : 0,
     LlcMaxPartition   : 0,
     LlcRemapHash      : axi_llc_pkg::Modulo,
-    LlcUserAmoMsb     : 0,
-    LlcUserAmoLsb     : 0,
     // VGA: RGB332
     VgaRedWidth       : 5,
     VgaGreenWidth     : 6,